JPS59114665U - image input device - Google Patents
image input deviceInfo
- Publication number
- JPS59114665U JPS59114665U JP814383U JP814383U JPS59114665U JP S59114665 U JPS59114665 U JP S59114665U JP 814383 U JP814383 U JP 814383U JP 814383 U JP814383 U JP 814383U JP S59114665 U JPS59114665 U JP S59114665U
- Authority
- JP
- Japan
- Prior art keywords
- image
- computer
- image display
- input device
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Studio Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来例の構成図、第2図はこの考案の実施例の
回路構成図、第3図は同例の動作を説明する信号波形図
、第4図は同例の要部の回路構成図である。
1・・・画像表示回路及び周辺回路、2・・・同期回路
、3・・・入力画像変換回路、4・・・画像書き込み制
御スイッチ、5・・・分周回路、6・・・垂直同期信号
、7・・・水平同期信号、8・・・アドレスカウンタ、
9・・ゼデオメモリ、10・・・パラレルシリアル変換
回路、11・・・インバータ、12.13・・・アンド
ゲート、14・・・オアゲート、15. 16. 17
. 18゜19・・・トライステートゲート、20・・
・ビデオメモリアクセス中信号、21・・・ビデオメモ
リ書き込み信号、22・・・リードライト信号、23・
・・映像信号。Fig. 1 is a block diagram of a conventional example, Fig. 2 is a circuit block diagram of an embodiment of this invention, Fig. 3 is a signal waveform diagram explaining the operation of the same example, and Fig. 4 is a circuit of the main part of the same example. FIG. DESCRIPTION OF SYMBOLS 1... Image display circuit and peripheral circuit, 2... Synchronization circuit, 3... Input image conversion circuit, 4... Image writing control switch, 5... Frequency division circuit, 6... Vertical synchronization Signal, 7...Horizontal synchronization signal, 8...Address counter,
9... Zedeo memory, 10... Parallel-serial conversion circuit, 11... Inverter, 12.13... AND gate, 14... OR gate, 15. 16. 17
.. 18゜19...tristate gate, 20...
- Video memory accessing signal, 21... Video memory write signal, 22... Read/write signal, 23.
...Video signal.
Claims (1)
ュータシステムで、その表示のためにコンピュータから
RAM(ランダムアクセスメモリ)にデータを書き込み
、コンピュータから独立した画像表示回路がこのデータ
を読み出し、テレビジョン画像信号に変換して表示する
方式の画像表示回路において、外部より入力したテレビ
ジョン画像信号にコンピュータの画像表示回路を同期さ
せ、同時に画像表示用のRAMに、その外部からの画像
信号を量子化したデータをじかに書き込む事により構成
される画像入力装置。A computer system that can display characters, figures, etc. on a television screen.The computer writes data into RAM (random access memory) for display, and an image display circuit independent of the computer reads this data and displays the television image. In an image display circuit that converts into a signal and displays it, the image display circuit of the computer is synchronized with the television image signal input from the outside, and at the same time, the image signal from the outside is quantized in the RAM for image display. An image input device configured by directly writing data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP814383U JPS59114665U (en) | 1983-01-24 | 1983-01-24 | image input device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP814383U JPS59114665U (en) | 1983-01-24 | 1983-01-24 | image input device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59114665U true JPS59114665U (en) | 1984-08-02 |
Family
ID=30139636
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP814383U Pending JPS59114665U (en) | 1983-01-24 | 1983-01-24 | image input device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59114665U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02162472A (en) * | 1988-12-16 | 1990-06-22 | Canon Inc | Electronic equipment |
-
1983
- 1983-01-24 JP JP814383U patent/JPS59114665U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02162472A (en) * | 1988-12-16 | 1990-06-22 | Canon Inc | Electronic equipment |
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