JPS58113145U - data display device - Google Patents
data display deviceInfo
- Publication number
- JPS58113145U JPS58113145U JP643182U JP643182U JPS58113145U JP S58113145 U JPS58113145 U JP S58113145U JP 643182 U JP643182 U JP 643182U JP 643182 U JP643182 U JP 643182U JP S58113145 U JPS58113145 U JP S58113145U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- control circuit
- periodic
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
- Computer And Data Communications (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案によるデータ表示装置のブロック図、第
２図は本考案による周期図形メモリ上のデータ構造図、
第３図は本考案による周期図形表示制御の処理のフロー
チャート、第４図は周期図形の例として時刻の表示のピ
ュアと周期図形メモリの内容を示す図である。
１・・・・・・外部計算機、２・・曲インターフェイス
回路、３・・・・・・表示制御回路、４・・・・・・タ
イミング制御回路、５・・・・・・リフレッシュ・メモ
リ、６・・曲バッファ、７・・・・・・映像信号形成回
路、８・・・・・・ピュア、 、９・・・・・・周期図
形表示制御回路、１０・・・・・・周期図形メモリー。FIG. 1 is a block diagram of a data display device according to the present invention, and FIG. 2 is a diagram of a data structure on a periodic figure memory according to the present invention.
FIG. 3 is a flowchart of the periodic figure display control processing according to the present invention, and FIG. 4 is a diagram showing pure time display and the contents of the periodic figure memory as an example of a periodic figure. 1... External computer, 2... Song interface circuit, 3... Display control circuit, 4... Timing control circuit, 5... Refresh memory, 6... Song buffer, 7... Video signal forming circuit, 8... Pure, , 9... Periodic figure display control circuit, 10... Periodic figure memory.
Claims (1)
回路と、前記表示データを制御する表示制御回路と、タ
イミング制御回路と、リフレッシュメモリーと、バッフ
ァと、映像信号形成回路とおよびピュアとから７成るも
のにおいて、周期的に変化する文字図形データを記憶す
る周期図形メモリーと、前記文字図形データを周期的に
更新し、ピュアに表示する周期図形表示制御回路とを設
けたことを特徴とするデータ表示装置。In a circuit consisting of an interface circuit for inputting display data from an external computer, a display control circuit for controlling the display data, a timing control circuit, a refresh memory, a buffer, a video signal forming circuit, and a pure circuit, the period What is claimed is: 1. A data display device comprising: a periodic figure memory that stores character and figure data that changes over time; and a periodic figure display control circuit that periodically updates the character and figure data and displays them in a pure manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP643182U JPS58113145U (en) | 1982-01-22 | 1982-01-22 | data display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP643182U JPS58113145U (en) | 1982-01-22 | 1982-01-22 | data display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58113145U true JPS58113145U (en) | 1983-08-02 |
Family
ID=30019210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP643182U Pending JPS58113145U (en) | 1982-01-22 | 1982-01-22 | data display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58113145U (en) |
-
1982
- 1982-01-22 JP JP643182U patent/JPS58113145U/en active Pending
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