JPS5811792U - image display device - Google Patents
image display deviceInfo
- Publication number
- JPS5811792U JPS5811792U JP10591381U JP10591381U JPS5811792U JP S5811792 U JPS5811792 U JP S5811792U JP 10591381 U JP10591381 U JP 10591381U JP 10591381 U JP10591381 U JP 10591381U JP S5811792 U JPS5811792 U JP S5811792U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- write
- image
- display device
- image data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例の要部回路図、第２図ａ、 ｂは゛同
上の動作説明図、第３図は本考案−実施例のブロック回
路図、第４図は同上の要部回路図、第５図および第６図
は同上の動作説明図である。
１は中央制御装置、２は端末表示装置、３はリフレッシ
ュメモリ、９は書込制御回路、Ｍ３は単安定マルチバイ
ブレークである。FIG. 1 is a circuit diagram of the main part of the conventional example, FIGS. 2a and b are explanatory diagrams of the same operation as above, FIG. FIG. 5 and FIG. 6 are explanatory diagrams of the same operation. 1 is a central control unit, 2 is a terminal display device, 3 is a refresh memory, 9 is a write control circuit, and M3 is a monostable multi-by-break.
Claims (1)
画像信号および書込要求信号を送出し、端末表示装置に
て上記画像信号を受信して画像データをアドレスデータ
に基いてリフレッシュメモリの所定メモリ番地に書込み
、リフレッシュメモリから順次読出された画像データに
基いてブラウン管上に画像を表示するためのビデオ信号
を形成するようにした画像表示装置において、画像デー
タ、アドレスデータおよび書込要求信号を保持するラッ
チ回路を端末表示装置に設けるとともに、書込要求信号
が得られかつビデオ信号のブランク信号が得られたとき
画像データをリフレッシュメモリに書込む書込信号を出
力するようにした書込制御回路を設け、ブランク信号の
前縁にてトリガ、される単安定マルチバイブレータによ
りブランク信号の前半区間に書込可能時間帯を設定して
この書込可能時間帯に書込要求信号が得られているとき
のみ書込制御回路から書込信号が出力されるようにして
成ることを特徴とする画像表示装置。An image signal consisting of image data and address data and a write request signal are sent from the central control unit, the terminal display device receives the image signal, and writes the image data to a predetermined memory address in the refresh memory based on the address data. , a latch circuit that holds image data, address data, and a write request signal in an image display device that forms a video signal for displaying an image on a cathode ray tube based on image data sequentially read from a refresh memory. is provided in the terminal display device, and a write control circuit configured to output a write signal for writing image data into the refresh memory when a write request signal is obtained and a blank signal of the video signal is obtained, A monostable multivibrator that is triggered at the leading edge of the blank signal sets a write-enabled time zone in the first half of the blank signal, and writes only when a write request signal is obtained during this write-enabled time zone. An image display device characterized in that a write signal is output from a write control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10591381U JPS5811792U (en) | 1981-07-15 | 1981-07-15 | image display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10591381U JPS5811792U (en) | 1981-07-15 | 1981-07-15 | image display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5811792U true JPS5811792U (en) | 1983-01-25 |
Family
ID=29900429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10591381U Pending JPS5811792U (en) | 1981-07-15 | 1981-07-15 | image display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5811792U (en) |
-
1981
- 1981-07-15 JP JP10591381U patent/JPS5811792U/en active Pending
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