JPS63102410U - - Google Patents
Info
- Publication number
- JPS63102410U JPS63102410U JP19816386U JP19816386U JPS63102410U JP S63102410 U JPS63102410 U JP S63102410U JP 19816386 U JP19816386 U JP 19816386U JP 19816386 U JP19816386 U JP 19816386U JP S63102410 U JPS63102410 U JP S63102410U
- Authority
- JP
- Japan
- Prior art keywords
- time
- display
- signal
- image
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- X-Ray Techniques (AREA)
- Apparatus For Radiation Diagnosis (AREA)
Description
第１図は本考案の一実施例の構成ブロツク図、
第２図は第１図の装置による表示画面の説明図、
第３図は本考案の他の実施例の構成ブロツク図、
第４図は第３図の装置による表示画面の説明図で
ある。
１…時計、２…画像メモリ、３，３Ａ，３Ｂ…
時刻バツフア、４…ＣＲＴ、５…時刻バツフア制
御回路、６…画像位置制御回路、１０…表示画面
、１１…画像（リアルタイム）、１２…時刻表示
（リアルタイム）、１３，１３Ａ，１３Ｂ…静止
画像、１４，１４Ａ，１４Ｂ…静止時刻表示。
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is an explanatory diagram of the display screen of the device shown in FIG.
FIG. 3 is a block diagram of another embodiment of the present invention;
FIG. 4 is an explanatory diagram of a display screen by the apparatus of FIG. 3. 1... Clock, 2... Image memory, 3, 3A, 3B...
Time buffer, 4... CRT, 5... Time buffer control circuit, 6... Image position control circuit, 10... Display screen, 11... Image (real time), 12... Time display (real time), 13, 13A, 13B... Still image, 14, 14A, 14B...Still time display.
Claims (1)
時刻表示用の信号を出力する時計と、該時計から
の時刻信号を書き込まれる少なくとも１個の時刻
バツフアと、画像データと共に前記時計からの時
刻信号と、時刻バツフアからの静止時刻信号とを
書き込まれる画像メモリと、該画像メモリに対す
る前記時刻バツフアからの時刻信号の書き込み及
び消去を制御する時刻バツフア制御回路と、前記
画像メモリからのデータを表示する表示回路とを
具備したことを特徴とする画像表示装置。 In an image display device having a time display function,
A clock that outputs a time display signal, at least one time buffer into which the time signal from the clock is written, and into which the time signal from the clock and the stationary time signal from the time buffer are written together with image data. An image display comprising an image memory, a time buffer control circuit that controls writing and erasing of a time signal from the time buffer into the image memory, and a display circuit that displays data from the image memory. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19816386U JPS63102410U (en) | 1986-12-23 | 1986-12-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19816386U JPS63102410U (en) | 1986-12-23 | 1986-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63102410U true JPS63102410U (en) | 1988-07-04 |
Family
ID=31158602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19816386U Pending JPS63102410U (en) | 1986-12-23 | 1986-12-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63102410U (en) |
-
1986
- 1986-12-23 JP JP19816386U patent/JPS63102410U/ja active Pending
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