JPS6327504Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory control device suitable for use, for example, in forming a video signal to be supplied to a television receiver displaying a display with twice the field frequency.

In the current television system, a scanning method called interlace is used. That is, 1
A single image (frame) is transmitted by two vertical scans (fields), and the aim is to increase the number of scanning lines as much as possible without causing flicker to the viewer's eyes in a limited frequency band. It was designed to do so.

However, in the CCIR method mainly used in Europe, the field frequency is 50 Hz, and flicker cannot be completely eliminated at this frequency, causing flickering to be felt, especially on screens with high brightness.

Therefore, conventionally, a television receiver has been proposed in which the field frequency is doubled. FIG. 1 shows an example.

In the figure, 1 indicates a video detection circuit, and a video signal Sv obtained from this video detection circuit 1 is supplied to a conversion circuit 2 to be converted into a double-speed field video signal whose field frequency is doubled. Ru.

The conversion circuit 2 includes field memories (random access memories 2a and 2b having a storage capacity for a pixel of 1V per field period, and a switch circuit 2c).
and 2d. The switch circuit 2c is
It is switched to the memory 2a and 2b side every 1V, while the switch circuit 2d is switched to the opposite side. Further, the memory selected by the switch circuit 2c is supplied with a write clock pulse having the above-mentioned pixel timing, and the memory selected by the switch circuit 2d is supplied with a read clock pulse of twice the frequency. be done.

The video signal Sv from the video detection circuit 1 is supplied to the memories 2a and 2b for one field every 1V via the switch circuit 2c, and is written therein, and the video signal Sv from the memory 2b and 2a is sent to the memories 2a and 2b for one field at a time.
The video signal for one field written in
It is read out twice in succession with a period of 1/2V, and this is obtained via the switch circuit 2d. In other words, a double-speed field video signal Sv' whose field frequency is doubled is obtained from this switch circuit 2d.

This field double speed video signal Sv' is supplied to the picture tube 4 through the signal processing circuit 3.

Further, the video signal Sv is supplied to a sync separation circuit 5, and the horizontal sync signal PH obtained from this sync separation circuit 5 is doubled by a multiplier 6 to become a signal with twice the frequency. It is supplied to a deflection coil 8 through a deflection circuit 7.

Further, the vertical synchronization signal Pv obtained from the synchronization separation circuit 5 is doubled by a multiplier 9 to produce a signal with twice the frequency, and this signal is supplied to the deflection coil 8 through the vertical deflection circuit 10.

In this example in FIG. 1, the picture tube 4
Field 2, where the field frequency is doubled
Since the double speed video signal Sv' is supplied and horizontal and vertical deflection scanning is performed at double speed, the picture tube 4
, the field frequency is displayed at twice the field frequency. Therefore, even in the CCIR method described above, the field frequency is doubled to 100 Hz, and no flicker is perceived.

However, in the case of the example shown in FIG. 1, two field memories are required, which increases the circuit size and costs, which is disadvantageous.

The present invention has been devised in view of this point, and is designed to enable similar operations to be performed using a single field memory.

Hereinafter, with reference to FIG. 2, an example will be explained in which the memory control device according to the present invention is applied to a television receiver that displays a display with twice the field frequency. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this example, the video signal from the video detection circuit 1
Sv is supplied to the field memory 11. Also,
The horizontal synchronization signal PH and vertical synchronization signal Pv obtained from the synchronization separation circuit 5 are supplied to the memory control circuit 12. Then, this memory control circuit 12 outputs an address control signal S _AD and a read/write control signal.
S _R/W and clock signal CLK are supplied to the field memory 11 mentioned above, and this field memory 1
1, a double-speed field video signal Sv' with the field frequency doubled, which will be described later, is obtained.

Here, the field memory 11 and the memory control circuit 12 constitute a memory control device according to the present invention.

In this memory control device, the information of the video signal Sv is sequentially written into the field memory 11, and when one piece of this information is written, two pieces of information that have already been written are read out. More field 2
A double-speed video signal Sv' is obtained.

This will be explained in more detail with reference to FIGS. 3 and 4.

A video signal Sv as shown in FIG. 3A is supplied to the field memory 11, and the field memory 1
When half of the information in field A is written to 1
From t ₁ , the information of the A field is subsequently written to this field memory 11, and the information of the A field written up to that point is written to the 2nd field.
It will begin to be read at twice the speed. Then, at time _t2 when all the information in the A field is written, all the information in the A field is read out. Therefore, all the information of the A field is read out from the field memory 11 during the 1/2V period from time t ₁ to t ₂ .

FIGS. 4A and 4B show that from time t ₁ to t ₂ ,
The address control signal S _AD and read/write signal supplied from the memory control circuit 12 to the field memory 11
This shows the write control signal S _R/W . When this control signal S _R/W is set to a high level and a low level, the field memory 11 is placed in a read and write state, respectively.

In this case, the information of one field, and therefore the address of field memory 11, is 2m from 0 to 2m-1.
It is assumed that there are individual.

As is clear from FIGS. 4A and 4B, during the 1/2V period from time _t1 to _t2 , addresses "m", "m+1", . . . of the field memory 11 are used.
..., after information is written to "2m-2" and "2m-1", addresses "0", "1",
"2""3", ......, "2m-4""2m-3","2m
-2 and 2m-1, respectively. Therefore, reading will not overtake writing during this period.

In addition, from time point _t2 in FIG. 3, the A field information already written in the field memory 11 starts to be read again at twice the writing speed, and the writing of the B field information starts. . Then, at time _t3 when half of the information in the B field has been written, all the information in the A field is read out again. Therefore, the information of the A field is read out again from the field memory 11 during the 1/2V period from time t ₂ to time t ₃ .

Figure 4 C and D show that from this point t ₂ to t ₃ ,
The address control signal S _AD and read/write signal supplied from the memory control circuit 12 to the field memory 11
This shows the write control signal S _R/W .

As is clear from these, from this point t ₂ to t ₃
During the 1/2V period, the addresses of field memory 11 are "0", "1", "2", "3", ...,
After reading the respective information from "2m-4", "2m-3", "2m-2", "2m-1", addresses "0", "1", ..., "m-2", " Information is written to each of "m-1". Therefore, during this period,
Writes never outpace reads.

Similarly, during the 1/2V period from time t ₃ when half of the information of the B field is written to the field memory 11 to time t ₄ when the entire information is written, all the information of the B field is read from the field memory 11 . From time t ₃ to t ₄ , the address control signal S _AD and read/write control signal S _R/W supplied from the memory control circuit 12 to the field memory 11 are the same as from time t ₁ to t ₂ described above. It is. Then, the point in time when writing of the C field information to the field memory 11 is started.
During the 1/2V period from t ₄ to half-written time t ₅ , all information in the B field is read out from the field memory 11 again. at the time
Address control signal supplied from memory control circuit 12 to field memory 11 from t ₄ to t ₅
S _AD and read/write control signal S _R/W are the same as from time t ₂ to t ₃ described above. and,
The same process is repeated below.

In this way, in the field memory 11, the information shown in FIG.
When a video signal Sv as shown in FIG. 3 is supplied, a double-speed field video signal Sv' as shown in FIG. 3B is obtained from the field memory 11.

In the example shown in FIG. 2, the video signal Sv' obtained from the field memory 11 is supplied to the picture tube 4 through the signal processing circuit 3.

The rest of the structure is the same as the example shown in FIG.

In this way, also in the example shown in FIG. 2, the field double-speed video signal Sv' is supplied to the picture tube 4, and horizontal and vertical deflection scanning is performed at twice the frequency. is displayed twice as much.

As is clear from the embodiments described above, according to the memory control device according to the present invention, it is possible to obtain, for example, a field double-speed video signal with a configuration of only one field memory. Therefore, compared to the conventional method that required two field memories to perform the same operation, memory can be saved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a television receiver configured to display images with twice the conventional field frequency, and Fig. 2 is a block diagram of a television receiver to which a memory control device according to the present invention is applied. The configuration diagram illustrating an example, and FIGS. 3 and 4 are diagrams for explaining the present invention, respectively. 11 is a field memory, and 12 is a memory control circuit.

Claims (1)

[Scope of utility model registration request] It consists of one field memory to which a video signal is supplied, and a memory control circuit that controls the address and read/write of this field memory, and in a field where the video signal is present, information of the field is stored in the field memory. In parallel with the writing operation, information on the certain field is read out from the field memory at twice the write speed from the time when half of the information has been written, and at the point when almost all of the information on the certain field is written, All the information in the field is read out, and in the field next to the certain field, the information in the certain field is read out again from the field memory at twice the writing speed, and in parallel with the reading operation, the information in the field is read out again from the field memory at twice the writing speed. A memory control device configured to control the memory so that the information of the next field is written in the memory, thereby obtaining a video signal whose field frequency is doubled at the output of the memory.