JPH10240219A - Screen division control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inexpensively constitute small-sized hardware without a complex address control. SOLUTION: In a screen division control system for dividing a display screen to plural areas and respectively displaying the different image data on respective divided areas, a serial access memory without having an address jump function is used. The pixel data A, B, C, D displayed in respective divided areas are written in this memory by shifting a spatial phase and at a period larger than a pixel arrangement period, and the image data are read out from the memory at the period larger than its arrangement period so that the image data in the relevant area are read out continuously at the display timing of respective divided areas.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a screen division control system for displaying multi-channel image data from a video or a television on a multi-screen.

[0002]

2. Description of the Related Art When one screen is divided into a plurality of areas and image data of a plurality of channels are displayed in each divided area, conventionally, a random access memory is used as a field memory and each memory area is stored in the memory area. A process of drawing one screen at a time while thinning out the image data of the area by a certain number of pixels is performed.

FIG. 11 shows a screen of 640 × 240 pixels as 4 pixels.
An example is shown in which four image data A, B, C, and D are divided and displayed. First, as shown in FIG. 3A, the first image data A is written to the memory while thinning out the pixels one by one in the horizontal and vertical directions. Assuming that the vertical / horizontal address is (Y, X), the writing of (y, 319) is completed, and when the horizontal synchronization signal is input, a line increment occurs, and the write address jumps to (y + 1, 0). . When the writing of the first image data A is completed, the write address is changed to (11) by the vertical synchronization signal.
Jump from (9,319) to (120,0).

Next, as shown in FIG. 1B, the second image data B is written to the memory while thinning out one pixel at a time in the horizontal and vertical directions. At this time, when the writing of (y, 319) is completed, the line increment by the horizontal synchronization signal occurs, and the write address becomes (y + 1, 319).
0), and when the writing of the second image data B is completed, the write address is changed to (2) by the vertical synchronization signal.
39,319) to (0,320).

Similarly, when writing the third image data C, the write address is changed from (y, 639) to (y + 1, 320) by the horizontal synchronization signal as shown in FIG.
The write address jumps from (119, 639) to (120, 320) by the vertical synchronizing signal, and when the fourth image data D is written, FIG.
As shown in (5), the write address jumps from (y, 639) to (y + 1, 320) by the horizontal synchronization signal,
The write address is changed to (239, 63) by the vertical synchronization signal.
Jump from (9) to (0,0).

If it takes one field time to write one divided screen, four-screen display requires four fields.
A multi-screen for one field is completed in the field time. At the time of reading from the memory, image data is read by a sequential reading operation according to general horizontal / vertical scanning. Normally, the memory has a double buffer configuration, and the same image data is continuously read from the other buffer four times while writing the multi-screen in one buffer.

[0007]

However, in the above-described conventional screen division control method, an expensive random access memory is used because an address jump to a specific address occurs at the time of line increment and vertical synchronization signal input. There is a problem that must be. Further, since a circuit for address control, a wiring area for an address bus, and the like are required, there is also a problem that hardware is increased in size. Furthermore, in the conventional screen division control method, since each divided screen is written one by one, there is a problem that it is difficult to perform processing without lowering the frame rate.

The present invention has been made in view of the above problems, and has as its object to provide a screen division control system which does not require complicated address control and can be configured in a small and inexpensive hardware. This is the purpose of 1. A second object of the present invention is to provide a screen division control method capable of performing processing without lowering the frame rate.

[0009]

A first screen division control method according to the present invention is a display division control method for dividing a display screen into a plurality of parts and displaying different image data in each divided area. Storage means for storing image data to be stored in the image storage means, and the pixel data displayed in each divided area in the image storage means is shifted in spatial phase from the pixel data displayed in the other divided areas, and the pixel data is arranged according to the arrangement period of the pixel data. And read the stored pixel data from the image storage means at a longer cycle than the arrangement cycle such that the image data of the area is continuously read at the display timing of each divided area. Light control means.

According to a second screen division control method of the present invention, in addition to the above-described structure, a plurality of synchronized image data displayed in the plurality of divided areas are input in parallel, and one of the plurality of image data is input from the plurality of image data. A data selection unit for selecting image data, wherein the read / write control unit switches the image data to be selected each time one pixel data is selected by controlling the data selection unit;
Image data of different divided areas is supplied to the image storage means in a time-division manner, and image data of all divided areas displayed in one field is written to the image storage means within one field period. .

In a third screen division control method according to the present invention, the read / write control means stores the image data of the pixel data constituting the image data displayed in each of the divided areas supplied one by one in order. By permitting writing to the means at regular intervals, the pixel data of each of the divided areas is written to the image storage means at a cycle larger than the arrangement cycle of the pixel data.

In a fourth screen division control method according to the present invention, the image storage means has a capacity capable of storing image data for at least two fields, and the read / write control means includes an image for one field. During writing of data, the image storage means is controlled so as to execute reading of image data of the other field.

According to the first screen division control method of the present invention, the read / write control means shifts the spatial phase of the pixel data displayed in each divided area from the pixel data displayed in the other areas. In addition, since the data is written into the image storage means at a cycle longer than the arrangement cycle of all pixel data, the write address increases at a constant interval, and the address does not jump in the middle of the screen. Also, at the time of reading image data, by reading pixel data at a cycle larger than the arrangement cycle, the image data of each divided area can be read continuously at the display timing of each divided area. The address does not jump during access to the image storage means. As described above, according to the present invention, an address jump does not occur, so that an inexpensive serial access memory can be used, and a circuit for address control and an address bus are not required, and hardware can be miniaturized. it can.

According to the second screen division control method of the present invention, a plurality of image data to be displayed in a plurality of division areas are input in parallel, and these image data are switched for each pixel data, and the image data is time-divided. By writing a plurality of image data in the storage means, all the image data displayed in one field is written in one field period, so that the writing time of the plurality of image data is shortened and the number of screens displayed There is an advantage that the frame rate does not decrease even if it does.

According to the third screen division control method of the present invention, even when image data displayed in each divided area is sequentially supplied one field at a time, no address jump occurs and an inexpensive serial access memory is used. Can be used, and the hardware can be downsized.

According to the fourth screen division control method of the present invention, since the image storage means has a double buffer configuration, while the image data is being written into one buffer, the image data from the other buffer is not stored. Reading can be performed, and time margin for the writing process can be secured.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a video processing apparatus to which a screen division control method according to an embodiment of the present invention is applied. Four NTSC image input signals A, B, C, D supplied in parallel
Are decoded by the NTSC decoder 1 and synchronized by the synchronization adjustment circuit 2. The four sets of image data synchronized by the synchronization adjustment circuit 2 are sequentially selected by the data selector 3 and written alternately one field at a time in each buffer of the serial access memory 4 having a double buffer configuration. The memory write controller 5 includes the synchronization adjustment circuit 2
Data selector 3 based on a vertical synchronizing signal, a horizontal synchronizing signal, and a pixel clock (PCLK) supplied from
And a write enable (/ WE) signal, a write address increment (/ W-ADDINC) signal, and a write address reset (/ W-RES) signal, respectively.
Control the data write operation. The memory read controller 6 outputs an output enable (/ OE) signal and a read address increment (/ R) based on the above-described vertical synchronization signal, horizontal synchronization signal, and PCLK.
-ADDINC) signal and read address reset (/
R-RES) signal is generated to control the operation of reading data from the memory 4. Image data sequentially read from the memory 4 under the control of the memory read controller 6 is converted into an NTSC signal by an NTSC encoder 7 and output as an image output signal.

Next, with reference to FIG. 2, a method of controlling the screen division by this video processing apparatus will be described. Here, for convenience of explanation, one field is described as 16 × 8 pixels, but actually more pixels are targeted. A, B, C, and D are pixel data constituting image data displayed in each divided area. FIG. 2 (a)
Indicates a writing position of each pixel data controlled by the memory write controller 5 in the memory 4.
That is, the memory write controller 5 controls the data selector 3 to alternately select the pixel data A and the pixel data B in a time-division manner in the odd lines and write them in the memory 4, and in the even lines, the pixel data C and the pixel data C in the odd lines. The pixel data D and the pixel data D are alternately selected in a time division manner and written into the memory 4. The write address is incremented according to PCLK. As a result, the pixel data A, B, C, D
Are written with a large period in which the spatial phases are shifted from each other and each pixel is thinned out by one pixel.

FIG. 2B shows a reading order when the pixel data A, B, C, and D written in the memory 4 are read out under the control of the memory read control 6. The pixel data is read every other pixel. When the 64th pixel data is read, the read address is reset and the read position is set to 1
To shift by one pixel, the address is incremented by one from the previous case, and pixel data is read out every other pixel again. Since the memory 4 is scanned for two fields, the read address is incremented by twice the pixel clock 2PCLK at the time of reading. As a result, all pixel data is read in one field period.

As a result, as shown in FIG. 2C, image data A, B, and
A four-split screen display in which C and D are arranged is realized. In this device, both the write address and the read address are incremented by 1 in the write and read operations,
Since an address jump does not occur on the way, address control is not required, and the use of an inexpensive serial access memory 4 becomes possible.

FIG. 3 is a diagram showing a configuration example of the memory write controller 5 and the memory read controller 6 for realizing such a read / write operation, FIG. 4 is a timing chart at the time of memory write control, and FIG. It is a timing chart of time. First, the memory write controller 5 will be described. Since the write address only needs to make one round of writing for one field, the vertical synchronization signal is used as it is as the / W-RES signal. In order to inhibit the writing of pixel data to the memory 4 and the write address increment operation during the blanking period of the vertical synchronization and the horizontal synchronization, a NAND output of the vertical synchronization signal and the horizontal synchronization signal is obtained by the NAND gate 11. , This is the / WE signal, / W-ADDIN
Let it be a C signal. Further, the horizontal synchronizing signal is frequency-divided by the frequency divider 12 to generate the select signal SEL1. PCLK is frequency-divided by the frequency divider 13 to generate the select signal SEL0.
As shown in FIG. 4, the select signal SEL1 becomes "H" on odd lines and "L" on even lines, and the select signal SEL0 switches to "H" or "L" for each pixel. By these SEL0 and SEL1, the pixel data A,
Select B, C, D.

Next, the memory read controller 6 will be described. At the time of memory reading, since the read address makes two rounds during scanning for one field, as shown in FIG. 5A, a / R-RES signal having a half cycle of the vertical synchronizing signal is generated. This means that the horizontal synchronizing signal is counted by the counter 14, the output of the counter 14 changes at the time when scanning for half a field is completed, and a pulse of a predetermined width is output from the flip-flop 15 at the change point of the output. An AND output of the output of the flip-flop 14 and the vertical synchronizing signal is obtained by the AND gate 16, and this is / R-R
An ES signal may be used. Further, in order to inhibit the data output operation and the read address increment operation during the blanking period of the vertical synchronization and the horizontal synchronization and the reset pulse output period of the / R-RES signal, the NAND output of the vertical synchronization signal and the horizontal synchronization signal is NAND gated. Got at 17,
The AND output of this and the output of the flip-flop 15 is A
By obtaining with the ND gate 18, / OE, / R-AD
Generate a DINC signal. The memory address is 2P
CLK, and the data output is PCLK
, Data is read every other pixel. In addition, since the pixel data to be read needs to be shifted by one pixel when the scanning for the half field is completed, as shown in FIG. 5B, / OE, / R-ADDI
The NC signal is configured so that the active timing at the start of field scanning and the active timing after reset after a lapse of a half field are shifted by a half cycle of PCLK. .. Are read at the start of scanning of the field, and after half a field has elapsed, the reading is started after the address is incremented by one, so that the addresses 1, 3, 5,. Will be read. Specifically, the pulse output from the flip-flop 15 to the AND gate 18 may be delayed from the pulse output from the flip-flop 15 to the AND gate 16 by a half cycle of PCLK.

FIG. 6 is a block diagram of an image recording / reproducing apparatus to which a screen division control system according to another embodiment of the present invention is applied. This device uses a Motion Photo JPEG (Joint Photographic Coding Exsp.
erts Group) and compressed and recorded by multi-screen display, and played back on a multi-screen display. For example, when analyzing sports forms, images of several seconds can be captured from different angles and compared on the same screen, Useful for applications such as comparing a form with your own form. In this embodiment, at the time of image recording, the image input signals A, B, C, and D of the NTSC system, which are input at different times, are transmitted to the NTSC system.
After decoding by the CS decoder 1 and compression by the compression / decompression unit 31, a DRAM (Dynamic Random Access Memory)
The image data A, B, C, and D stored in the DRAM 32 are sequentially read out one field at a time during image reproduction, and serially accessed under the control of the memory write controller 33 and the memory read controller 6. By writing in the memory 4, a four-split screen display is realized.

In this case, since each image data is read from the DRAM 32 one field at a time, FIG.
As shown in FIG.
Pixels are thinned out one by one in the vertical direction and written into the memory 4 at a cycle twice as long as the pixel arrangement cycle, and as shown in FIG.
In the second field, the pixel data B is written into the memory 4 at a period twice as long as the pixel arrangement period by making the spatial phase of the pixel data A different from that of the pixel data A in the horizontal direction, and as shown in FIG.
In the field, the pixel data C is written into the memory 4 at a period twice as long as the pixel arrangement period with a different spatial phase in the vertical direction from the pixel data A, and as shown in FIG. D is written into the memory 4 at a cycle twice as long as the pixel arrangement cycle, with a different horizontal spatial phase from the pixel data C. Thus, one field is completed in four fields. In the meantime, the same image data is continuously read from the other buffer four times. The reading sequence of each field is exactly the same as in the previous embodiment.

FIG. 8 shows a configuration example of the memory write controller 33 for realizing the above-described write operation, and FIG. 9 shows a timing chart of the write operation. In the above embodiment, the pixel data is selected by the select signals SEL0 and SEL1 to control the order of writing.
In this embodiment, the write position in each field is controlled by the / WE signal. That is, as shown in FIG.
Select signals S1 whose output is inverted for each field, 2
A select signal S2 whose output is inverted for each field is generated, and a write position is controlled by a combination of these select signals S1 and S2. In this example, the relationship between the select signals S1 and S2 and the write position is as follows.

[0026]

[Table 1] Select signal write position S1 S2 HH Odd-numbered pixel on odd-numbered line LH Even-numbered pixel on odd-numbered line H L Odd-numbered pixel on even-numbered line L L Even-numbered pixel on even-numbered line

The select signal S1 is, as shown in FIG.
The vertical synchronizing signal is obtained by dividing the frequency by the frequency divider 41, and the select signal S2 is obtained by further dividing the output of the frequency divider 41 by the frequency divider. A signal indicating that the horizontal synchronization signal is an even line obtained by dividing the frequency of the horizontal synchronization signal by the frequency divider 43 and a signal indicating that the line is an odd line obtained by inverting the signal by the inverter 44 are supplied to the selector 45. And the selection signal S
The selection output SO2 is obtained by selecting at step 2. Then, the OR gate 46 masks the / W-ADDINC signal with the selection output SO2. On the other hand, a signal indicating an even-numbered pixel obtained by frequency-dividing the PCLK signal by a frequency divider 47 and a signal indicating an odd-numbered pixel obtained by inverting the signal by an inverter 48 are supplied to a selector 49 and selected. The selection output SO1 is obtained by selecting with the signal S1. When the selected output SO1 and the output of the OR gate 46 are input to the OR gate 50, the OR gate 50
Can be used as the / WE signal.

FIG. 10 is a diagram showing still another embodiment of the present invention. This embodiment is an example in which pixel data of YC (4: 2: 2) format, which is often used as a color image, is divided and displayed. In FIG.
Un represents the luminance Y and color U of the pixel data n, and YVn represents the luminance Y and color V data of the pixel data n. By continuously storing YUn data and YVn data of the same pixel and reading out two pixels continuously, as shown in FIG. 3B, skipping two pixels and reading the pixel data, As shown in (c), a multi-screen display in which color image data is arranged in each divided area can be obtained.

In the above embodiment, an example of a 4-split screen display has been described. However, the present invention can be applied to other division numbers such as 2-split and 16-split. It goes without saying that the screen size can be applied to other sizes such as 640 × 240.

[0030]

As described above, according to the present invention,
Since the read / write control means writes the pixel data of each divided area into the image storage means at a different period from the pixel data of the other divided areas at a period longer than the pixel arrangement period, the write address is constant. When the image data is read out, the pixel data is read out at a period larger than the arrangement period so that the image data of the region is continuously read at the display timing of each divided region. Address jump does not occur,
An inexpensive serial access memory can be used, and an address control circuit and an address bus are not required, and the hardware can be reduced in size.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video processing device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a screen division control method in the same device.

FIG. 3 is a block diagram showing a configuration of a memory write controller and a memory read controller in the same device. FIG. 2 is a diagram showing a storage area of a DRAM and a display screen.

FIG. 4 is a timing chart during the memory write.

FIG. 5 is a timing chart at the time of the memory read.

FIG. 6 is a block diagram showing a configuration of an image recording / reproducing apparatus according to another embodiment of the present invention.

FIG. 7 is a diagram for explaining a screen division control method in the same device.

FIG. 8 is a block diagram showing a configuration of a memory write controller and a memory read controller in the same device.

FIG. 9 is a timing chart during the memory write.

FIG. 10 is a diagram for explaining a screen division control method according to still another embodiment of the present invention.

FIG. 11 is a diagram for explaining a conventional screen division control method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... NTSC decoder, 2 ... Synchronization adjustment circuit, 3 ... Data selector, 4 ... Serial access memory, 5, 33 ... Memory write controller, 6 ... Memory read controller, 7 ... NTSC encoder, 31 ... Compression / expansion part, 3
2. DRAM.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/265 H04N 5/265

Claims (4)

[Claims] An image storage means for storing image data to be displayed in a screen division control method for dividing a display screen into a plurality of parts and displaying different image data in each divided area; The pixel data displayed in each divided area is written with a spatial phase shifted from that of the pixel data displayed in the other divided areas and at a cycle larger than the arrangement cycle of the pixel data. Read / write control means for reading out the stored pixel data from the image storage means at a cycle longer than its arrangement cycle so that the image data is continuously read out. . 2. The image processing apparatus according to claim 1, further comprising a data selection unit configured to input a plurality of image data displayed in the plurality of divided areas and synchronized with each other in parallel, and to select one image data from the plurality of image data. The light control unit controls the data selection unit to switch image data to be selected each time one pixel data is selected, thereby supplying image data of different divided regions to the image storage unit in a time-division manner, 2. The screen division control method according to claim 1, wherein image data of all divided areas displayed in one field is written into said image storage means within one field period. 3. The read / write control means permits, at regular intervals, writing of pixel data constituting image data displayed in each of the divided areas supplied one by one in order to the image storage means. 2. The screen division control method according to claim 1, wherein the pixel data of each of the divided areas is written into the image storage unit at a period longer than an arrangement period of the pixel data. 4. The image storage means has a capacity capable of storing image data of at least two fields, and the read / write control means operates while the image data of one field is written. 4. The screen division control method according to claim 1, wherein the image storage unit is controlled so as to execute reading of the image data.