JPS63242069A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a smooth moving picture with high vertical resolution as to a moving pattern and to obtain a picture with fluctuation as to a still picture by switching a write address depending on the result of discrimination of a field discrimination circuit of a video input signal so as to control the read address by the result of comparison of the position of write/read patterns. CONSTITUTION:A write address is switched from the result of discrimination of a field of a video input signal to write video signals of both 1st and 2nd fields into separate areas of the memory. In case of readout, a write pattern position and a read pattern position are compared to discriminate the moving/ stilling pattern and the read address is switched for each field as to the moving pattern to output alternately the signals of both the fields and only the signal of the 1st field is outputted always to the still pattern. Thus, a picture is obtained for the moving pattern by using the signal of both the fields through interlacing and a field still picture is obtained as to the still pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a device that realizes a multi-screen function, and particularly to a video signal processing device suitable for obtaining a moving image screen with high resolution and smooth motion.

[Conventional technology]

The "Year VTRr NV-D21 J (Hideo Salon) equipped with Digital Memo" was released by Matsushita Electric on December 1, 1986 as a device that realizes the so-called multi-screen function that displays multiple reduced images at the same time. ,
(December 1986 issue, p. 139).

(D rNV -D21J +7) v le f screen function!
Nine screens reduced to 11/3 are displayed in 3 horizontal screens x 3 vertical rows, and it has a multi-strobe function that sequentially displays strobe images on 9 screens, and images from each channel of TV broadcasting. It has a multi-channel function that displays images sequentially.

The display method is based on the first . Record only one of the second fields in memory,
This signal is read out and displayed in two consecutive fields, and from this K it is possible to obtain a field still image without blurring.

[Problem that the invention seeks to solve]

In the conventional example described above, since a video signal is recorded only every other field, the moving image screen is played back in field skip mode, and the motion is discontinuous compared to a normal interlaced playback image, and the resolution in the vertical direction is lower.

An object of the present invention is to obtain, in a multi-screen function, an image with high vertical resolution and smooth movement on a moving image screen, and an image without blur on a still screen with light.

[Means for solving problems]

In order to achieve the above object, the present invention provides a memory for storing video signals and a read and write address generation circuit, as well as a field determination circuit for video input signals, and switches the write address value based on the determination result. . Also,
A circuit is provided to compare the writing and reading screen positions, and the read address is controlled based on this result.

[Effect]

Based on the results of field discrimination of the video input signal.

Switch the write address to the first. The video signals of both second fields are respectively written to different areas of the memory. When reading, the write screen position and read screen position are compared to determine whether the screen is a moving image or a still screen, and for the moving screen, the read address is switched for each field and signals for both fields are output alternately. , only the first field signal is always output for a still screen. From this K, an image interlaced using the signals of both fields is obtained for the moving image, and a field still image is obtained for the still screen.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, 1 is a memory section, 2 is a latch circuit, 3 is a timing generation circuit, 4 is a write column address generation circuit, 5 is a write row address generation circuit, 6 is a field discrimination circuit, and 7 is a writing screen position. Control circuit, 8 is a multiplexer.

9 is a synchronization and work signal addition circuit, 10 is a read column address generation circuit, 11 is a read row address generation circuit, 12 is a frequency divider circuit, 13 is a read screen position detection circuit, 14 is a comparator, and 15 is a 16 is an AND circuit, and 17 is an OR circuit. Further, 18 is a video signal input terminal, 19 is a write clock signal input terminal, 20 is a horizontal synchronization signal terminal, 21 is a vertical synchronization signal input terminal, 22 and 23 are control signal terminals, and 24 is a video signal output terminal. , 25 are read clock signal input terminals.

Next, the circuit operation of the embodiment shown in FIG. 1 will be explained.

In the embodiment shown in FIG. 1, it is assumed that the memory unit 1 is of a dual port type in which data can be written and read simultaneously. The video signal terminal 181C outputs the video signal 1a and leads this signal 1a to the latch circuit 2.

On the other hand, it was synchronized with the video signal 1a. The write clock signal 1b, horizontal synchronization signal IC, and vertical synchronization signal 1d are applied to the long terminals 19, 20, and 21, respectively. The video signal 1a is sampled from the latch clock signal 1eK generated in the timing generation circuit 3 according to these signals. This sampling is to thin out the video data in the horizontal and vertical directions according to the reduction ratio of one screen. For example, if the reduction ratio of the screen is 173, there are 3 pixels in the horizontal direction and 1 pixel in the button. The latch clock signal 1e is controlled so that the sampling is performed at a rate of , and at a rate of one every three scanning lines in the vertical direction. The thus sampled video signal is processed according to the write address value generated by the write address generation circuit 4.5.

Write to memory section 1. Reading is performed according to the read address value generated by the read address generation circuit 10.11, and after a synchronization signal and a wake signal are added by the synchronization/wake signal addition circuit 9.

Output to the output terminal 24.

Next, address control will be explained using FIGS. 2 and 3. FIG. 2 shows the memory section 1 of the embodiment shown in FIG.
This is a diagram showing the storage area of , with rows arranged vertically and columns arranged horizontally. FIG. 3 is a diagram showing sampling points for the video input signal 1a. The solid lines in FIG. 1 indicate the scanning lines of the first field, and the remaining lines indicate the scanning lines of the second field. Further, the points indicated by O in the figure are sampling points, and the points indicated by × are points at which sampling is not performed. Here, the number of screens of the multi-screen is 3 vertically and 4 horizontally, totaling 12 screens (each screen is hereinafter referred to as 1st to 12th screen).
, the reduction ratio is assumed to be 1/3, but the present invention is not limited to this.

In the present invention, data is written and read by associating the row address of the memory with the vertical position of the screen and the column address with the horizontal position of the screen. As a result, each address generation circuit can be configured with a relatively simple circuit configuration.

The video signals of the first field of the first to twelfth screens are respectively written in the storage areas indicated by A1-A12 in FIG. Also, Bf, B2. 1 each in the storage area of B3
The video signals of the second fields of the 5th stage (1st to 4th screens), the 2nd stage (5th to 8th screens), and the 5th stage (9th to 12th screens) are written. The position of the writing screen is determined by the writing screen position control circuit 7, and the screen position is controlled by a control signal input from the input terminal 23. Switching of the fixed position on the screen is performed by switching the initial values of write addresses 1h and 11 using the 5-position control signal 1g1C.

Below, a case in which writing is performed on, for example, the first screen will be described. Write write column address 1h in write column address generation circuit 4 and horizontal synchronization signal 1C
It is initialized by the clock signal 1b and updated at the same cycle as the write frequency. At this time, by switching the initial value of the address by the discrimination signal 1fVc from the field discrimination circuit 6, the video signal of the first field is transferred to the storage area A1 of the memory section 1, and the video signal of the second field is transferred to the storage area B1. , alternately write each field. Also,
In the write row address generation circuit 5, the write
The row address 11 is initialized by the write vertical synchronization signal 1d and updated every five pulses of the write horizontal synchronization signal 1C. Therefore, as shown in FIG.
For the fields, a1, B2, etc. in the figure are shown.
. . to the storage area A of the memory unit 1, and for the second field, bt, b2 .・Sequentially write the old scanning lines to area B-\.

Next, the read operation will be explained. In the read column address generation circuit 10, using the signal 1m inputted from the input terminal 25 as a clock, read column address 1 is generated at a frequency three times the writing frequency to the memory.
generate j. moreover.

The read column address generation circuit 1p generates a read horizontal synchronization signal 1n indicating that addresses for one horizontal scanning period have been generated. The read row address generation circuit 11 uses this signal 1m as a clock to generate a read row address 1k. Furthermore, the read row address generation circuit 11 generates a read vertical synchronization signal 1p indicating that an address for one field has been generated. This signal 1p is sent to a frequency divider circuit 12, and the output signal 1r whose frequency is divided by 2 is sent to a read/row address circuit 11, and the number of horizontal scans for one field is set to 1, for example, in the case of an NTSC signal.

Switch to K 262 and 263 per field. In other words, signal 1r indicates whether the read signal is the first field or not.
This is a signal indicating whether it is the second field.

In the present invention, in the multi-screen mode, interlacing is performed using the signals of the first and second fields on the moving image screen to obtain an image with smooth motion and high resolution in the vertical direction. On the other hand, for a still screen, field stilling is performed using only the first field signal to obtain a still image without blur.

For example, in the case where the second screen is a moving image screen and the other screens are still screens, video signals are written into the storage areas A2 and B1 of the memory section 1 alternately for each field. Writing and reading are performed asynchronously, and when writing and reading are performed by emitting light from the same storage area in order to further reduce one screen, the read address may overtake the write address, resulting in the data being written on one screen. A discontinuous boundary line appears. Therefore, reading is always performed from the area to which no writing has been performed to prevent address overtaking from occurring. For example, when writing is performed in area A2, the readout operation for the first stage screen is performed in the order of areas AI, B1, A3, A4 (one line from each area successively).

Also, if writing is performed in area B1, area AI
, A2, AM, and A4 are read in this order.

Also, for the second and third screens, A5, A6, A7, A8, and A9. A10
, A11, and A12 are read in this order. in particular.

The writing screen position and the reading screen position are compared in the comparator 14, and if they do not match, the storage area A of the memory unit 1 is always used, and if they match, the area A or B is not written. The read column address 1j is controlled so that the other area is read.

Basically, the value of the read row address may be updated every horizontal scanning period. 4 to 8 show portions of the readout screen, and their relative positions in the vertical direction are shown together with each other. In the embodiment shown in FIG. 1, writing and reading are performed asynchronously when the moving picture screen is being played back, so there is no difference between the first and second fields of the reading indicated by the signal 1V, and the actual reading. The first field of the signal.

The second field does not necessarily match. When the two match, that is, when the first field is read, the signal of the first field written in area A is read, and when the read is the second field, the signal of the second field of area B is read. In this case, a correct reduced screen can be obtained as shown in FIG. On the other hand, if the two do not match, that is, when the readout is in the first field, the signal of the second field of area B is sent, and when the readout is in the second field, the signal of the area A is sent.
When the signal of the first field is read out, the vertical relationship of the scanning lines is reversed between the 1st and 2nd fields, as shown in FIG. 5, and the image is distorted. In order to prevent this, the present invention
For a moving picture screen, when reading is the second field and the signal of the first field of area A is read, that is, 1
When the output signal 1r of the division circuit 12 and the output signal 1f of the write field discrimination circuit 6 are both the second field, the adder 15 adds the read row address K "1". As a result, an image without reversal of scanning lines is obtained as shown in FIG. This image is shifted up by one scanning line with respect to the image in FIG.

On the other hand, for still screen light, the video signal of the first field of area A is always read out regardless of the field to be read out.

In this case, the image obtained is as shown in FIG. Here, if you pay attention to the image with a boundary line between scanning lines a4 and h4 (the lower end of the L-shaped figure with diagonal lines in the figure), you will notice that in Figures 6 and 7, the maximum scanning There is a difference of two lines, and the vertical movement of the image is noticeable when switching from a moving image to a still screen, or from a still screen to a moving image. Therefore, in the present invention, for a still screen, "1" is added to the read row address when reading is in the second field. The image thus obtained is shown in FIG. Figures 4 and 6
Compared to the moving picture screen in the figure, the vertical deviation of one image can be suppressed to one scanning line at most.

In the embodiment shown in FIG. 1, the output signal 1f of the field discrimination circuit 6 and the output signal 1r of the frequency dividing circuit 12 are both
It shall be at a high level during the field. Also,
It is assumed that the output signal 1t of the comparator 14 becomes a low level when the write screen position and the read screen position match, and the control signal 1u becomes a high level when the entire screen is a still image. The output signal 1t of the comparator 14, the control signal 1u, and the output signal 1f of the field discrimination circuit 6 are
It is led to the R circuit 17, and then the OR circuit 1
7's output signal 1v and the output signal 1r of the frequency dividing circuit 12 are A
It is led to an ND circuit 16 and a logical product is taken. This AND circuit 16
When the output signal 1W of is at high level, the adder 15 adds "1" to the read row address. The writing and reading screen positions do not match.

Alternatively, since the readout screen is a still image when the control signal 1u is at a high level, the desired adder control' is performed by one or more circuit configurations.

In this embodiment, the reduction ratio is 1151 and the number of screens is 12, but the present invention is not limited to this. Also, although I did not specifically mention the processing of one color signal, one color difference and
There is no problem even if the present invention is applied to a signal after separating the luminance signal.

[Effects of the Invention] According to the present invention, in a multi-screen function that displays a plurality of reduced screens at the same time, it is possible to obtain a smooth image with high vertical resolution for a moving image screen, and to obtain an image without blurring for a still screen. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG.
1 is a memory map diagram showing the area of the memory section 1 of the embodiment of FIG. 1, FIG. 3 is an explanatory diagram for explaining the write operation of the embodiment of FIG. 1, and FIGS. FIG. 3 is an explanatory diagram for explaining the read operation of the illustrated embodiment. 1...Memory part. 3... Timing generation circuit. 4...Write column address generation circuit. 5...Write row address generation circuit. 6...Write field discrimination circuit 10...Read column address generation circuit. 11...Read row address generation circuit. 15... Adder.

Claims (1)

[Claims] 1. m screens in the horizontal direction (m is a natural number) and l screens in the vertical direction (l is a natural number) reduced to 1/n (n is a natural number)
, a memory capable of storing at least (m×l+1) fields of reduced screens, and a column and row address generation circuit for writing to the memory, in a device that simultaneously displays a total of (m×l) screens. a read column and row address generation circuit, a video signal input terminal, and a write means for thinning out the video input signal from the video signal input terminal in the horizontal and vertical directions and writing to the memory according to the write address; a video signal output terminal, a reading means for reading a signal from the memory according to the read address and guiding it to the video signal output terminal, a field discrimination circuit for discriminating fields of the video input signal, and detecting the positions of the write screen and the read screen. a detection circuit for controlling the write address generation circuit to write the first and second field signals to different areas of the memory according to the results of the field discrimination circuit, and further for controlling the read and write screen. The outputs of the detection circuits are compared, and if they match, the signals of the first and second fields are read out alternately for each field, and if they do not match, only the signal of the first field is read out. A video signal processing circuit that controls a read address generation circuit. 2. In claim 1, if the result of the field determination is the second field or the writing and reading screen positions do not match, and furthermore, the reading is the second field, the readout row A video signal processing circuit characterized by adding "1" to an address value.