JPH01114272A - Frame memory access method - Google Patents

Abstract

PURPOSE:To simplify a program or constitution by setting a prescribed number of bits subsequent to an address area corresponding to one scanning line length to a field selection signal and plural bits subsequent to the field selection signal to a scanning line designation address area. CONSTITUTION:The prescribed number-bits subsequent to the address area 61 corresponding to one scanning line length is set to the field selection signal 62, and the plural bits subsequent to the field selection signal 62 is designated to the scanning line designation address area 63. For making access in terms of frames, one field is selected based on the field selection signal 62, a scanning line is designated based on the content of the scanning line designation address area 63 and a frame memory is made access based on the content of the address area 61 corresponding to one scanning line length in such a state, whereby merely increment is needed. Thus, software and constitution can be simplified.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a frame memory access method, and more specifically, the present invention relates to a frame memory access method.
The present invention relates to a method for accessing a frame memory partitioned into a field and a second field.

<Prior art> Interlaced scanning and non-interlaced scanning have been provided as scanning methods for television cameras, CRT displays, etc., but compared to the non-interlaced scanning method where one field constitutes one frame, interlace In the scanning method, two fields constitute one frame, which has the advantage of being able to reduce flicker and have good reproducibility of motion.

To explain in more detail, for example, a video signal captured by a television camera is converted into digital data by an A/D converter and sequentially stored in a frame memory. In this case, the frame memory is divided into an even numbered memory area corresponding to an even numbered scanning line and an odd numbered memory area corresponding to an odd numbered scanning line (see Figure 6), and the first field scanning The digital data obtained by performing the second field scan (see the solid line in Figure 5) is transferred to the even memory area, and the digital data obtained by performing the second field scan (see the broken line in Figure 5) is transferred to the odd memory area. I am trying to store each one.

Therefore, although the scanning line interval in one field scan becomes wider, the time required for one field scan is halved, which is useful when inputting images with a television camera or displaying images etc. with a CRT display. etc., it is possible to reduce flicker and improve motion reproducibility.

<Problems to be Solved by the Invention> When the above-mentioned interlaced scanning method is applied only to simple video input and display of images, etc., it has only the advantages described above, and in particular there is no interlace. For example, when performing processing such as masking, trimming, enlargement, reduction, rotation, etc. on a video signal input from a television camera, it is necessary for the processor to access the frame memory. There is a problem in that access to the frame memory becomes complicated and overall processing efficiency cannot be improved.

To explain in more detail, frame memory access by the processor is not performed field by field but frame by frame, so when accessing the frame memory shown in FIG. , and scan lines at the same address in the odd memory area are sequentially accessed, and then the scan line address to be accessed is incremented to sequentially access the scan line at the incremented address in the even memory area and the odd memory area. By repeating access, frame-by-frame access can be performed sequentially. Therefore, simply incrementing the address data to obtain the scanning line address to be accessed results in access in units of fields, and cannot be accessed in units of bottom frames.

As a result, after accessing one scan line, the address data must be changed to correspond to the next scan line (a scan line in a different memory area). The problem arises that it becomes complicated,
Further, if a counter is provided to change the address data, a problem arises in that the configuration becomes complicated.

On the other hand, if the frame memory is configured to be suitable for frame access as shown in Figure 7, the above-mentioned problem will not occur when access is performed by the processor. When inputting video from the 1st field to the 2nd field, it is necessary to skip only 1 scanning line each time one scanning line is accessed. There is a problem in that the configuration becomes complicated by providing a circuit for skipping one scanning line and a circuit for initializing the start address.

<Object of the invention> This invention was made in view of the above problems,
For a frame memory partitioned into a first field and a second field for interlaced scanning,
It is an object of the present invention to provide a frame memory access method that can perform frame access without complicating programs or configurations.

<Means for Solving the Problems> In order to achieve the above object, the frame memory access method of the present invention accesses a frame memory partitioned into a plurality of fields in units of frames to perform interlaced scanning. In this method, a predetermined number of bits following an address area corresponding to one scanning line length are used as a field selection signal, and a plurality of bits following the field selection signal are used as a scanning line designated address area.

However, it is preferable to generate address data for frame memory access by replacing the field selection signal and the scanning line designation address area.

Furthermore, the frame memory may be divided into two fields, and the field selection signal may be set as a 1-bit signal.

With the frame memory access method described above, since the frame memory is divided into multiple fields for interlace scanning, it is not necessary to input video from a television camera or display images on a CRT. In this case, interlaced scanning can be achieved simply by sequentially scanning each field.

In addition, when performing frame-by-frame access, select one of the fields based on the field selection signal,
In this state, the scan line is specified based on the contents of the scan line specification address area, and the frame memory is accessed based on the contents of the address area corresponding to the length of one scan line, so it is sufficient to simply increment. After scanning one scanning line in the - field, the field selection signal changes automatically, so that scanning lines at the same address in other fields can be scanned. After the scanning lines in all other fields have been scanned, the field selection signal automatically changes to restore the original state, and the contents of the scanning line designated address area are incremented. The next scan line in the field can be scanned. Thereafter, by repeating the above operations, the contents of the frame memory partitioned into a plurality of fields can be accessed not in units of fields but in units of frames.

When generating address data for frame memory access by replacing the field selection signal and the scan line designation address area, simply incrementing the field or scan line designation or changing the data arrangement The most significant bit can select a field, and the frame memory can be accessed as it is.

Furthermore, the same effect as described above can be achieved even when the frame memory is divided into two fields and the field selection signal is set as a 1-bit signal.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 4 is a schematic diagram showing an example of a device implementing the present invention, in which an interlaced television camera (1) is shown.
The scanning address data in the processor (4) is converted by an A/D converter (2) and supplied to the frame memo (January 3), and the address data generated in the processor (4) is converted to an address converter (5). ), the data is converted into address data for frame memory access, and the address data is supplied to the frame memory (3).

More specifically, as shown in FIG. 2, the frame memory (3) has a first field (31) corresponding to an odd numbered scanning line and a second field (31) corresponding to an even numbered scanning line. 32) It is divided into
Both fields have memory areas corresponding to N scan lines. The scanning address data in the interlaced television camera (1) is
Odd-numbered scanning lines and even-numbered scanning lines are the first field (31,) and the second field (32), respectively.
The field is set in advance to correspond to the above fields, and video input from a television camera is automatically assigned to each of the above fields.

In addition, the address data generated in the processor (4) has 1 on the lower bit side, as shown in FIG. 1A.
n-bit address area (61) corresponding to the scanning line
It also has a 1-bit field selection signal area (62) on the upper bit side of the address area (61), and further has a field selection signal area (62).
62), there is a scanning line designation address area (63) of (m-n-1) bits on the more significant bit side.

Therefore, the address data is sequentially incremented from the lower bit, and by scanning one scanning line, the contents of the address area (61) are restored to the original state, and the contents of the field selection signal area (62
) contents. Then, by scanning two scanning lines, the contents of the address area (61) and field selection signal area (62) are restored to their original states, and the contents of the scanning line specified address area (63) are incremented. be done.

The address conversion unit (5) converts the address data in the format shown in FIG. 1A, and the address data in the format shown in FIG. 1B.
As shown in FIG. 3, by moving the field selection signal area (62) to the most significant bit position and shifting down the scanning line designation address area (63) by one bit, the signal to be supplied to the frame memory (3) is moved. I am trying to generate address data.

The frame access operation of the device with the above configuration is as follows.

When storing video input from the television camera (1) in the frame memory (3),
Since 1) is an interlaced method, scanning corresponding to odd-numbered scanning lines and scanning corresponding to even-numbered scanning lines are performed alternately, and address data is also generated in accordance with the above scanning. Therefore, the first field (31) and the second field (32) are automatically selected, and video data is stored for each field.

When the frame memory (3) is accessed by the processor (4), the processor (4)
In order to perform frame-by-frame access, address data shown in FIG. 1A is generated. This address data is converted into address data in the format shown in FIG. 1B in the address conversion section (5), and is supplied to the frame memory (3). Therefore, in the address data shown in FIG. 1B, while the scanning line of the same scanning line specified address is scanned twice, the contents of the bits excluding the most significant bit or the same state appear, and only the contents of the most significant bit appear. are in different states and the processor (
The first field (31) and the second field (32), which are partitioned from each other, can be accessed in the same way as frame-by-frame access without changing the generation of address data in step 4). can.

FIG. 3 is a diagram showing a configuration for selecting a field based on the content of the most significant bit, and control data indicating that a state in which the frame memory (3) is accessed by the processor (4) is selected is shown. Paired AND gate (3
3) (34) and one AN
The contents of the third most significant bit are inverted and supplied to the D game (33), and the other AND gate (33)
For 4), the contents of the most significant bit in item 2 are supplied as is. The output signal from the AND gate (33) is supplied to the first field (31) as an access control signal, and the output signal from the AND gate (34) is supplied to the second field (32). is supplied as an access control signal.

Therefore, the content of the most significant bit is inverted every time one scanning line is accessed, and as the content of the most significant bit is inverted, control data is selectively output from one of the AND gates. Therefore, only the corresponding field becomes accessible, and even though address data corresponding to the frame-by-frame access state is generated, it is possible to perform access corresponding to the state partitioned by field. .

Note that the present invention is not limited to the above-described embodiments, and can be applied, for example, to displaying the contents of a frame memory on an interlaced CRT display. It is possible to separate the area and separate data, and furthermore, it is possible to partition the frame memory into more than two fields, and to set the number of bits of the field selection signal to correspond to the number of fields, and other fields. However, various design changes can be made without departing from the gist of the invention.

<Effects of the Invention> As described above, the present invention provides a frame memory 1 divided into a plurality of fields for interlaced scanning.
This has the unique effect of incrementing the single address data and making it possible to access the frame memory in frame units without complicating the software or configuration. .

[Brief explanation of the drawing]

Figure 1 is a diagram showing the format of address data generated in the processor and address data supplied to the frame memory, Figure 2 is a schematic diagram showing the configuration of the frame memory, and Figure 3 is a diagram showing the contents of the most significant bit. 4 is a schematic diagram illustrating an example of an apparatus for implementing the present invention; FIG. 5 is a diagram illustrating interlaced scanning; FIGS. 6 and 7 are diagrams illustrating a configuration for selecting a field based on 1 is a schematic diagram showing a conventional example of a frame memory. (3)...Frame memory, (4)...Processor, (5)...Address converter, (31)...Second field, (32)...Second field, (61)・
...Address area, (62)...Field selection signal area, (63)...Scanning line specification address area.Gq Group 1-゛Figure 7

Claims (1)

[Claims] 1. A method for accessing a frame memory partitioned into a plurality of fields in units of frames to perform interlaced scanning, the method comprising: accessing a predetermined number of fields following an address area corresponding to the length of one scanning line; A frame memory access method characterized in that a bit is used as a field selection signal, and a plurality of bits following the field selection signal are used as a scanning line designation address area. 2. The frame memory access method according to claim 1, wherein address data for frame memory access is generated by replacing the field selection signal and the scanning line designated address area. 3. The frame memory access method according to claim 1 or 2, wherein the frame memory is divided into two fields and the field selection signal is set as a 1-bit signal.