JPH07203297A - Video moving picture magnification interpolation device - Google Patents

Abstract

PURPOSE:To facilitate the use of a gate, an array, a programmable logic device and a field programmable gate array efficiently by using logic circuits and gates so as to form an interpolation arithmetic section so as to attain high speed interpolation. CONSTITUTION:A received NTSC signal is subject to Y/C separation by a Y/C separator section 1, decoded by a chroma decoder 2 and the result enters an A/D converter 3, and its outputs being R, G, B signals are stored in a frame memory 8 of R/G/B double magnification circuits 41, 42, 43. Then the signals are read by a horizontal interpolation section 9, in which horizontal linear interpolation data are calculated and stored in line memories LM0-2. Then the data are selected by a line memory select section 10 and vertical linear interpolation data are calculated by a vertical interpolation section 11 and outputted to a D/A converter 5. Thus, a CPU and a ROM are not used for the linear interpolation and high speed arithmetic operation is attained with a simple logic circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video moving picture enlarging / interpolating apparatus used for interpolating pixel data of an image, for example, when enlarging and displaying a part of a video moving picture.

[0002]

2. Description of the Related Art Conventionally, for example, when an abnormality occurs in a crime prevention device for monitoring a required place by a television camera, an abnormal portion of a monitor screen is enlarged and displayed,
BACKGROUND ART While playing a recorded video tape, a part to be particularly viewed is enlarged and viewed. Figure 1
0 indicates a situation in which such a video moving image image is enlarged and displayed, A is a television screen such as a CRT, and an arbitrary partial image B indicated by a broken line in the television screen A is doubled, for example. The image C is enlarged and displayed.

As described above, when a partial image on the television screen is enlarged and displayed, in order to obtain a good image, it is necessary to interpolate new pixel data into the pixel data isolated by the enlargement. Conventionally, the interpolation of this pixel data has
The method of performing calculations using
A method is adopted in which the data is stored in M and the two interpolated data are used as addresses in the ROM to read out the stored data and perform interpolation.

[Problems to be Solved by the Invention]

However, the method of calculating and interpolating by using the CPU employs a method of thinning out the frames instead of using all the frames because the calculation speed of the CPU is slow. Therefore, there is a drawback that the motion of the moving image becomes awkward.

The interpolation method using ROM is
When using a PLD (programmable, logic, device) or FPGA (field, programmable, gate, array) whose operation speed is limited by the lead time of the ROM, and which has become popular in recent years, use the ROM for these PLDs.
Since it is difficult to form it inside the or FPGA, the efficiency is low.

In view of the above problems of the prior art, the present invention makes it possible to perform high-speed interpolation by constructing the interpolation operation section using logic and gates without using a CPU or ROM, thereby improving efficiency. It is an object of the present invention to provide a video motion picture interpolation device that facilitates the use of good gates, arrays, PLDs and FPGAs.

[0007]

In order to achieve the above-mentioned object, a video moving picture enlarging / interpolating device of the present invention comprises an image signal enlarging circuit for enlarging and outputting an inputted image signal. Further, it is provided with a horizontal interpolating means for horizontally interpolating the pixel data and a vertical interpolating means for vertically interpolating the pixel data. In a typical embodiment of the present invention, the interpolation is performed by a linear interpolation method and the interpolation operation is performed by a logic circuit.

[0008]

In the video moving picture enlarging / interpolating apparatus of the present invention having the above-described structure, for example, the NTSC image signal inputted to the image signal input circuit is enlarged, and at the same time, the pixel data is interpolated to perform the horizontal linear interpolation. Interpolation and vertical linear interpolation are performed, and the interpolated image signal is output.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In order to simplify the explanation and make it easier to understand,
In the description of this embodiment, the number of data bits is set to 4 bits, but in the implementation, a bit number exceeding 4 bits can be similarly realized.

FIG. 1 is an overall block diagram of an embodiment of a video moving picture enlarging / interpolating device of the present invention for enlarging a video moving picture by a factor of 2 and shows a block diagram using an NTSC signal as an example. As can be seen in the figure, this device has a Y / C separation unit 1
, A chroma decoder 2, an A / D comparator 3, a 2 × enlargement section 4 including enlargement circuits 41, 42 and 43, and D /
It is composed of an A comparator 5 and an NTSC encoder 6. Reference numeral 7 is a sync separation unit. The main part of the device of the present invention is an enlargement section 4 comprising enlargement circuits 41, 42 and 43 for doubling each of the R, G and B image signals, and these three circuits are all circuits of the same contents. It is composed of.

The input NTSC signal is Y / C separated by the Y / C separation unit 1, is decoded by the chroma decoder 2 and enters the A / D converter 3, and is converted from an analog to a digital signal to obtain R, G and R2 for each B signal
The signal is enlarged by the double enlargement circuit 41, the G2 double enlargement circuit 42, and the B2 double enlargement circuit, converted into analog signals by the D / A converter 5, encoded by the encoder 6, and NT.
The SC signal is output to a display device (not shown).

FIG. 2 is a double magnification circuit 4 of the double magnification section 4.
1, 42 and 43 are respectively shown in a block diagram. The digital signal from the A / D converter 3 is stored in the frame memory 8 and read out by the horizontal interpolation section 9 to calculate horizontal linear interpolation data. , The calculated data is stored in the line memories LMO, LMI and LM2,
The line memory is selected by the selection unit 10, the vertical linear interpolation data is calculated by the vertical interpolation unit 11, and the vertical linear interpolation data is output to the D / A converter 5. Reference numeral 12 denotes an expansion control circuit that receives the synchronization, sampling, and clock (SCLK) signals from the synchronization separation unit 7 and controls each unit of this expansion circuit. FIG. 3 is a block diagram of the frame memory 8. The frame memory 8 is an odd (ODD) field memory 81.
And an even field memory 82.

Under the control of the control circuit 12, the frame memory 8 is written with ISCLK and read with 1/2 SCLK. EVEN when writing the ODD field
The field is read, and the ODD field is read when the EVEN field is written.

FIG. 4 is a block diagram showing an example of the horizontal interpolation unit 9. As described above, in this figure, the number of bits is set to 4 in order to simplify the description. 1/2 SC
The data read from the frame memory 8 in synchronization with LK is latched by the latches LHI and LH2, and the adder 1
After being added by 3, it is shifted to the decimal point side by 1 bit,
It is latched by the latch LH3. The data selector 14 outputs LH2 to the line memory when 1 / 2SCLK is "H", and the saved data LH3 when "L".
Is output to the line memory.

As shown in FIG. 2, the line memory is L
There are three lines MO to LM2, one of the three lines is selected for each horizontal period, and the data subjected to the horizontal linear interpolation is written. The order of selection is LMO → LM1 → LM
It becomes like 2 → LMO. Further, the two unwritten lines are read and output to the line memory / select unit 10.

FIG. 5 shows a block diagram of the line memory / select unit 10. Also in this figure, the number of bits is 4 in order to simplify the description. Also, Table 1
Is a control data list of the line memory and select unit. The line memory / select unit selects any two of the line memories LMO to LM2, rearranges the order, and outputs the data to the vertical interpolation unit 11.

[0017]

[Table 1]

FIG. 6 is a block diagram showing an example of the vertical interpolation unit 11. Also in this figure, the number of bits is set to 4 in order to simplify the description. The vertical interpolation unit includes latches LV1 and LV2, an adder 15, latches LV3 and LV4, and a data selector 16. By, linear interpolation data is created. When the interpolated data and the select signal LINE COMPN are "H", the interpolated data is not output to the D / A converter 5, and YODO to YO
D3 data is output as it is, and LINE COMP
When N is “L”, the interpolation data is output to the D / A converter 5.

FIG. 7 is a diagram showing an algorithm of a linear interpolation operation carried out in the video moving image enlargement / interpolation apparatus of the present invention having the above-mentioned structure. In the figure, X
The axis represents the interpolated position and the Y axis represents each data value. y
_o and y _i are the actual data values that have been A / D converted, and y
_M is the interpolated data value created by _yo , _yi .
In the case of the 2-fold enlargement shown in the above embodiment, _yo and _yi
If the interval is set to 1, the interpolation position of the interpolation data y _M becomes 0 and 5 of the middle points. The data value of y _M is represented by the formula (Equation 1). That is, it can be seen from the equation (Equation 1) that y _M can be obtained by adding _yo and y _i and shifting by 1 bit to the decimal point side. Therefore, linear interpolation can be performed by digital circuits such as the latch circuit and the adder circuit shown above.

[0020]

[Equation 1]

FIGS. 8 and 9 are diagrams showing the location of the interpolated data, and in order to simplify the explanation, they are shown as 4 pixels in both the horizontal and vertical directions. Figure 8
FIG. 9 shows a pixel location before double magnification, and FIG. 9 shows a pixel location after double magnification. In the figure, P _ij is A / D
Converted data, H _ij is horizontal interpolation data, V _ij
ij is vertical direction interpolation data. H _ij in FIG.
Is expressed by the equation (2), and V _ij is expressed by the equations (3) and (4).

[0022]

[Equation 2]

[0023]

[Equation 3]

[0024]

[Equation 4]

As is apparent from the above description, the video moving image enlargement / interpolation device of the present invention enlarges and displays a part of a video moving image by interpolating pixel data, and its enlargement portion in the screen is arbitrary. Can be set in the place of. Although the above embodiment has been described with respect to the case of magnifying twice, the magnifying power is not limited to 2 and can be set to any magnifying power, and fixing the magnifying power is also a zoom. It is also possible. further,
It can be applied to both black and white and color video movies. Furthermore, it can be applied to a high-definition system.

As described above, the video moving image enlargement / interpolation device of the present invention uses CP for performing linear interpolation calculation.
Since it is composed of a simple logic circuit without using U or ROM, high-speed operation is possible. Moreover, since the arithmetic circuit can be configured in the gate, array, FPGA and PLD,
There is an advantage that the hardware can be configured inexpensively.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a video moving image expansion / interpolation device.

FIG. 2 is a block diagram of an enlargement unit.

FIG. 3 is a block diagram of a frame memory unit.

FIG. 4 is a block diagram of a horizontal interpolation unit.

FIG. 5 is a block diagram of a line memory and a selection unit.

FIG. 6 is a block diagram of a vertical interpolation unit.

FIG. 7 is an explanatory diagram of an interpolation calculation algorithm.

FIG. 8 is a pixel location diagram before enlargement.

FIG. 9 is a pixel location diagram after enlargement.

FIG. 10 is an explanatory diagram of a magnified display state of a video moving image.

[Explanation of symbols]

 4 Enlargement Units 41, 42, 43, Enlargement Circuit 9 Horizontal Interpolation Unit 11 Vertical Interpolation Unit

Claims (3)

[Claims] 1. An image signal enlarging circuit for enlarging and outputting an input image signal, wherein the image signal enlarging circuit horizontally interpolates pixel data and vertical interpolation for vertically interpolating pixel data. And a video moving image enlargement / interpolation device. 2. The video motion picture enlarging interpolation device according to claim 1, wherein the data interpolation method by the horizontal and vertical interpolation means is a linear interpolation method. 3. A video moving image enlarging / interpolating device according to claim 1, wherein the data interpolating operation in said horizontal and vertical interpolating means is performed by a logic circuit.