JPH0421188A - Method for processing image information - Google Patents

Abstract

PURPOSE:To improve the speed of image recognizing processing without expanding memory capacity by reading out the former half part of a picture of in a frame memory synchronously with a step for inputting even lines in the frame memory and reading out the latter half part at the time of inputting odd lines. CONSTITUTION:A synchronizing signal generating circuit 9 separates and outputs a synchronizing signal in accordance with an interlace analog video signal including a synchronizing signal from a TV camera 1 and a frame memory control circuit 10 outputs a required frame address control signal by using the synchronizing signal as reference timing to control the writing/reading of the frame memory 3 by a prescribed method. At the time of writing even fields, the former half part of an image written in the memory 3 is read out. At the time of reading out odd fields, the latter half part is read out and an interlace digital signal is supplied to an image processor 4. In the above procedure, the conversion of image information can be attained within a half of the one-frame time and the speed of image recognizing processing can be improved without extending memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image information processing method for converting an analog video signal into a digital signal in order to perform digital image processing.

"Prior Art" FIG. 5 is a diagram showing the configuration of a conventional image information processing apparatus to which a conventional image information processing method is applied. In FIG. Image input means 2 For example, a television camera; (2) is an A/D conversion circuit that converts an analog video signal imaged by the television camera (1) into a digital signal; (3) has color or shading information for each pixel. The frame memory (4) stores image information for one screen, and is an image processing device that sequentially extracts and processes pixel data after all pixel data for one screen is stored in the frame memory (3). Note that the image processing device (4) is generally constructed using a microcomputer or a dedicated complex circuit element.

Next, a method of processing image information using a conventional device will be described. Before entering into a description of the conventional method, an outline of the two-screen scanning method will be described. Screen scanning methods include interlaced scanning and non-interlaced scanning1.
A normal television camera captures images using an interlaced scanning method. In the interlaced scanning method, in the first scan, odd-numbered scanning lines are scanned to create first image information, and in the second scan, even-numbered scanning lines are scanned to create second image information. 1st. This is a method in which scanning for one screen is completed by combining nine pieces of second image information.

On the other hand, the non-interlaced scanning method simply scans the scanning lines sequentially, but images produced by this method have the disadvantage of flickering, and are only used when the total number of scanning lines is small. It is a method.

Now, in FIG. 5, when an analog video signal based on interlaced scanning method captured by a television camera (1) is A/D converted by an A/D converter circuit (2) and outputted directly to an image processing device (4). , the image processing device (4 2 image processing devices (4
) cannot handle this directly. Therefore, the fifth
As shown in the figure, the first image information and the second image information are stored in a frame memory (3
) is stored in a superimposed manner so as to become non-interlaced image information, thereby restoring it to non-interlaced image information, which is then read out again and sent to the second image processing device (4).

According to this method, two images are captured by the AI from the TV camera (1).
One frame time (1730 seconds) per screen is written to the frame memory (3) via the D conversion circuit (2), and the information is sent to the image processing device (4) only after that, so two images are generated. Processing device (4) and frame memory (3)
Even if the speed is high, the time required to write image information to the frame memory (3) becomes a bottleneck.

There is a problem that the speed of image recognition processing cannot be improved.

Furthermore, in the method shown in Fig. 1, the frame memory (3
) is the time when information is being read from the TV camera (1).
Since the image information sent from the A/D converter circuit (2) cannot be written to the frame memory (3), real-time processing that continuously processes the image information that is continuously sent cannot be performed. .

To solve this real-time processing problem, there is a method shown in FIG. 6 of Japanese Patent Laid-Open No. 63-205778. In this method, a frame memory (30) with a storage capacity of information for two screens is prepared, an area of the frame memory (30) that stores information for one screen is designated as frame memory A, and the remaining area for storing information for one screen is The area in which this is stored is called frame memory B. Then, the interlaced analog video signal sent from the television camera (1) passes through the A/D conversion circuit (2) to the frame memory A.
While the image information is being input to the TV side, the contents of the frame memory B side where the image information immediately before (one frame time ago) is stored are read out, and after the reading of the contents of the frame memory B side is completed, the TV The interlaced analog video signal sent from the camera ( ) is processed by the A/D conversion circuit (
At the same time that the image information that has passed through 2) is written to the frame memory B side, the image information that has been written to the frame memory A side that has completed writing first
Real-time processing is realized by reading out the contents of the side. With this method, it still takes one frame time (1/30 second) to convert interlaced image information to non-interlaced image information, and the image sent from the frame memory (30) is always sent to the television camera (1). There is a delay of one frame time (1/30 second) with respect to the image information sent out.

Further, the synchronization signal separation circuit (6) in FIG. 6 separates the synchronization signal part included in the interlace analog video signal sent from the television camera (1), and based on this, the clock generation circuit 5), the A/D conversion circuit (
2), write control circuit (7), and read control circuit (
8).

Further, the write control circuit (7) and read control circuit (8) also control which frame memory A or frame memory B is accessed.

Note that in FIG. 5, the clock generation circuit (5) and synchronization signal separation circuit (6) in FIG. 6 are omitted for convenience of explanation.

[Problems to be Solved by the Invention] Conventional image information processing methods have been performed as described above, so it takes at least 1 time to convert analog image information based on interlaced scanning to non-interlaced image information as digital information. Frame time is required, and in order to perform real-time processing of continuous image information, the frame memory (30
).

This invention was made to solve the above-mentioned problems, and it is possible to convert analog image information using an interlace scanning method into non-interlaced image information as digital information in 172 times of one frame time. The object of the present invention is to provide a method for processing image information that enables real-time processing of continuous image information and requires only a frame memory capacity that can store image information for one screen.

[Means for Solving the Problems] A method for processing image information according to the present invention includes a step of A/D converting image information scanned by an image input means in odd-numbered rows and inputting the image information into odd-numbered rows of a frame memory. After inputting the image information of 7 to the frame memory, the image information scanned by the even numbered rows by the image input means is A/D converted and inputted to the even numbered rows of the frame memory.

A step that repeats the step of entering data in odd-numbered rows and the step of entering data in even-numbered rows.

When sequentially reading one screen of digital image information input to the frame memory, the first half of one screen is read out in synchronization with the step of inputting even numbered rows, and the second half of one screen is read out in synchronization with the step of inputting odd numbered rows. Step of reading out part.

The first half of one screen is read out from the frame memory in synchronization with the step of inputting the odd-numbered rows into the frame memory, and the second half of one screen is read out from the frame memory in synchronization with the step of inputting the odd-numbered rows into the frame memory.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. 1st
The figure shows a configuration for implementing the method of this invention.
(1) is a television camera that scans and captures images using the interlaced scanning method, (2) is an A/D conversion circuit, (3) is a frame memory that stores information for one image, and (4) is a frame memory (3). An image processing device (9) that processes the non-interlaced image information read out from the television camera (1) separates a synchronization signal part from the analog video information output from the television camera (1), and processes it based on this separated synchronization signal part. This is a synchronization signal generation circuit that generates a synchronization signal. In addition, A/D
The conversion circuit (2) receives a synchronization signal as a reference operation timing signal from this synchronization signal generation circuit.

(10) is a frame memory control circuit which uses the synchronization signal outputted from the synchronization signal generation circuit (9) as a reference timing and provides frame memory (3) head address information and control information.

FIGS. 2 to 4 are memory maps with the situations in which interlaced image information is read from the frame memory (30). In FIGS. 2 to 4, there is a total of one line, and ji (1≦j≦n) represents information on the j-th line of the i-th screen. For example, 1i, 3i,...(n
-1) i is the information of the odd-numbered row of the i-th screen,
This is first screen information having a total of n/2 lines of information.

Further, 2i, 4i, .

Figure 2 shows that the first screen information of the i-th screen is sequentially written to the frame memory (30), and the information in the n/2 rows in the lower half of the previous 11th screen is read as non-interlaced information. It shows how it is being taken.

What is the operating timing?

At the same time as writing 1i, (TI/2+ 1)l-1 is read and 3i 〃(n/2+ 2)+-+
”in/2+(n/2-1)l+ 〃(n/2
+n/2), -1〃The whole operation takes 17 seconds per frame time.
2 (this time is referred to as one field time). The reason why it is possible to operate as shown in Fig. 2 will be described later.5Similarly, Fig. 3 shows that the second screen information of the first screen is sequentially written to the frame memory (30) and It shows how information in half of n/2 lines is read as non-interlaced information.

What is the operating timing?

At the same time as writing 21, 11 is read and 4
1 no/21〃 t'n/2+(n/2-2] I ノ'
in/2-1) i ”(n/2+n
/21 r ” (n/2), “The entire operation is performed in 172 of one frame time.

Figure 4 shows j=i+1 in Figure 2, and 2
This is the same as FIG. 2 except that the following screen is handled.

Next, in FIG. 3, the reason why the information in the n/2 rows in the upper half of the i-th screen can be normally read out as non-interlaced information will be explained. First, information 21 is written at the same time as 11 pieces of information written when the first screen information of the i-th screen shown in FIG.

2], which is read next, has been updated from 21-1 to 21 immediately before, so it can be read correctly. At this time, 41 is written at the same time as 121 is read. Since all of the information read in this way has been updated from i-1 to i↓, the upper half of the information on the i-th screen is read out as non-interlaced information.

Next, in Figure 4, the first screen information of the i+1th screen is written to zero, but the reason why the lower half of the information on the i-th screen can be read as non-interlaced image information is explained below. explain. The first post is li
+1, so the information that is read simultaneously at this time is the information on the i-th screen (n/2+l>i), but the reason why the information on the i-th screen can be read until the last information is read is as follows. It is proven that

The information written simultaneously when reading (n/2+R)i is (2R() I-1. (However, I≦R≦n/2
) Therefore, if 2R-J< n/2+R holds, then before reading the information on the i-th screen, write
It can be seen that the image information on the +1st screen is not rewritten.

Now, under two conditions 1≦R≦n/2, from R≦n/2, R
-1<n/2 holds, so 2R-1< n/2+
R holds true.

Therefore, the lower half of the information on the i-th screen will not be updated by writing the i+1-th screen information before the i-th screen information is read out, and will be read out normally as non-interlaced image information. I understand.

In the above embodiment, the frame memory (3) is a memory that can be read and written at the same time, but even if it is a memory that cannot be read and written at the same time, the next information is input to the frame memory (3). It is sufficient if it can be read and written to. For example, frame memory (3)
If the frame memory (3) can be read and written at twice the transfer speed of image information input to the frame memory (3), the same result can be obtained by reading and writing alternately.

[Effects of the Invention] As described above, according to the present invention, the first half of one screen is read out from the frame memory in synchronization with the step of inputting the even numbered rows into the frame memory, and the odd numbered rows are input into the frame memory. Since the second half of one screen is read out from the frame memory in synchronization with the step of inputting it into the memory, the conversion of two image information can be accomplished in 172 hours, which is one frame time.

This has the effect of improving the speed of image recognition processing without increasing memory capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an image information processing apparatus for implementing an image information processing method according to an embodiment of the present invention, and FIGS. 2 to 4 show conversion of interlaced image information to non-interlaced image information. FIG. 5 is a block diagram showing the configuration of an image information processing device for carrying out the conventional image information processing method, and FIG. FIG. 2 is a block diagram for explaining the method. (1) is an image input means, and (3) is a frame memory. In Figure 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] Image information scanned by odd-numbered lines by the image input means is
D-converting and inputting the image information to the odd-numbered rows of the frame memory, after inputting the image information of the odd-numbered rows to the frame memory, A/D converting the image information scanned by the even-numbered rows by the image input means, a step of inputting data into the even-numbered rows of the frame memory; a step of repeating the step of inputting the data into the odd-numbered rows and the step of inputting the data into the even-numbered rows; A method for processing image information, comprising: reading out the first half of the one screen in synchronization with the step of inputting the odd-numbered lines, and reading out the second half of the one screen in synchronization with the step of inputting the odd-numbered lines. .