JPH08237611A - Image storage device and scanning converter - Google Patents

Abstract

PURPOSE: To reproduce a synchronizing signal in response to a read speed together with image data with simple-configuration by storing the image data comprising video signals and its synchronizing signal in pairs simultaneously to a memory. CONSTITUTION: Sensor data (image data) and a scanning signal outputted from a scanner 1 comprising a scanning microscope are written simultaneously to a scanning data storage device 2 and the sensor data in the scanning data storage device 2 or display data stored in a display memory 3 are selected by a switch 4. Thus, a window pattern based on the sensor data is displayed on a display screen of a display device 2. Then a read address of the display data from the display memory 3 is given to a window start trigger generator 6 and when the address reaches a preset read start address, a read start trigger is given to the scanning data storage device 2. Thus, the configuration is simplified without the need for a synchronizing signal generating circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device in which data output from various scanning type sensor devices is written / read out, and scan conversion, image display conversion and speed conversion of an input video signal and an output video signal. The present invention relates to a scan conversion device capable of

[0002]

2. Description of the Related Art Conventionally, a scan conversion device (Japanese Patent Laid-Open No. 61-43885) for converting a television signal transmitted by an interlaced scanning system into a progressive scanning system, or a writing speed and a reading speed are made different. There is a recording / reproducing apparatus (Japanese Patent Laid-Open No. 61-84980) for recording / reproducing a television signal.

FIG. 27 shows the configuration of the scan conversion device described in the above-mentioned Japanese Patent Laid-Open No. 61-43885. This scanning conversion device converts an input video signal into image data digitized by an A / D converter 71, converts the converted image data into parallel data by a serial-to-parallel converter 72, and then stores it in a memory 73. Remember. At this time, the sync separation circuit 74
The sync signal extracted from the input video signal is given to the write address counter 75 for designating the address of the image data to generate the write address, and only the image data is stored in the memory 7.
Write in 3 for each field. Further, the sync signal extracted by the sync separation circuit 74 is input to the PLL unit 76 to generate a reference clock that is in external synchronization.

On the other hand, when the image data is read from the memory 73, the reference clock generated in the PLL unit 76 is divided by the frequency divider 7
The speed is converted via 7 and input to the synchronizing signal generating circuit 78. The sync signal generation circuit 78 newly generates sync signals such as a vertical sync signal, a horizontal sync signal and a data valid signal necessary for reproducing the image data. Sync signal generation circuit 7
The read address counter 79 is operated based on the synchronization signal generated in 8 to generate a read address. Image data read from the memory 73 by alternating fields for each line is returned serially by the parallel-to-parallel converter 81.
The image data is converted into an analog signal by the D / A converter 82.

[0005]

However, when the image data stored in the memory 73 is read out, the scan conversion is realized by reading out at a reading speed different from the writing speed. It was necessary to newly generate a sync signal for reading using a clock corresponding to a pixel. Therefore, it is necessary to separately provide a sync signal generation circuit 78 that generates a sync signal for reading.

Further, after the image data given from the scanning type sensor device is stored in the storage device and then the data is transferred from the storage device to another device, the data transfer rate is set to the transfer destination by using the line buffer or the frame buffer. There is a conversion device that matches the device, but it was necessary to separately provide a line buffer or a frame buffer.

Further, since only the image data is stored in the memory, it is necessary to determine the number of pixels in one line by some means. For example, the number of pixels in one line is determined by associating the pixel size of the image with another file. In the field where the number of pixels on one screen is fixed, there is no need to perform an operation for matching the pixel size, but this is not a problem, but when recording and reproducing image data captured by a scanning sensor device such as a scanning microscope, Since the number of pixels in the line is frequently changed depending on the condition of the sample, it is necessary to make the pixel size correspond to another file each time, and the operation is complicated.

It is an object of the present invention to set a set of image data forming a video signal and a synchronizing signal thereof and store them in a memory at the same time. An object of the present invention is to provide an image storage device and a scan conversion device capable of reproducing a corresponding synchronization signal together with image data.

An object of the present invention is to enable speed conversion to an arbitrary speed without using a line buffer or the like, and
An object of the present invention is to provide an image storage device and a scan conversion device that can always match image data and its synchronization signal and can very easily create a high-quality reproduced image without pixel shift.

[0010]

The present invention has taken the following means in order to achieve the above object. According to a first aspect of the present invention, in an image storage device that stores image data whose horizontal and vertical sizes are defined by a sync signal, a write address determined based on a count value of the sync signal is used. The image data and the synchronization signal are stored at the same time.

According to a second aspect of the present invention, an A / D converter for A / D-converting an image signal acquired by a scanning device to convert it into image data represented by a predetermined number of bits, and an A / D converter
A write address generator that counts the sync signal of the image signal input to the D converter to generate a write address of the image data, and the image data and the sync signal at the write address generated by the write address generator. A read address of the data storage unit is generated based on a data storage unit to be stored as a set, a synchronization signal read out together with image data from the data storage unit, and a read clock corresponding to a transfer speed of a data transfer destination. And a read address generator.

According to a third aspect of the present invention, an A / D converter for A / D converting an image signal acquired by a scanning device to convert it into image data represented by a predetermined number of bits, and an A / D converter for the image signal. A write address generation unit that counts a synchronization signal to generate a write address of the image data, and a data storage unit that stores the image data and the synchronization signal as a set at the write address generated by the write address generation unit. A read pixel counter that counts a read clock according to a clock speed of a data transfer destination to generate a pixel address of the data storage unit; and a horizontal signal included in a synchronization signal output from the data storage unit together with image data. A read line counter that counts a synchronization signal to generate a line address of the data storage unit; A read frame counter for generating a frame address by counting a vertical sync signal and a horizontal sync signal included in a sync signal output together with the image data, and a sync signal converted into a sync signal output together with the image data from the data storage unit. Means for inserting supplementary data according to the display form, frame data latch unit for storing the contents related to the frame address from the supplementary data inserted in the synchronization signal output from the data storage unit, and the frame data latch unit For setting the contents of the supplementary data stored in the read frame counter
The switch means, the line data latch unit for storing the content related to the line address from the supplementary data inserted in the synchronization signal output from the data storage unit, and the content of the supplementary data stored in the line data latch unit. Second switch means for setting the read line counter, a pixel data latch section for storing the content related to the pixel address from the supplementary data inserted in the synchronization signal output from the data storage section, and the pixel Third switch means for setting the content of the supplementary data stored in the data latch unit in the read pixel counter, and switching of input of a synchronization signal to the read pixel counter, the read line counter, and the read frame counter. A fourth switch means.

[0013]

The present invention has the following effects by taking the above measures. According to the present invention corresponding to claim 1, the image data and the sync signal are stored as a set at an address determined according to the count value of the sync signal such as the horizontal sync, the vertical sync, and the valid signal. . Therefore, by reading the image data, the synchronizing signal is also reproduced in synchronization with this.

According to the second aspect of the present invention, the synchronizing signal of the image data is counted by the write address generating unit to generate the write address of the image data. The image data and the sync signal are stored as a set at this address. On the other hand, the read address of the data storage unit is determined based on the synchronization signal read by the read address generation unit together with the image data from the data storage unit and the read clock corresponding to the transfer speed of the data transfer destination. Therefore, it is possible to easily read at different reading speeds without separately preparing a device that generates a synchronization signal that matches the transfer speed of the reading-side device.

According to the present invention corresponding to claim 3, the supplementary data is inserted into the synchronization signal stored together with the image data in the data storage unit, and the content of the supplementary data is read when the synchronization signal is read from the data storage unit. Is stored in each data latch unit, and is set in the corresponding address counter from each data latch unit by the first to third switch means. Therefore, a free tomographic image can be easily created by manipulating the supplementary data.

[0016]

Embodiments of the present invention will be described below. (First Embodiment) FIG. 1 shows a schematic configuration of the first embodiment. In this embodiment, the sensor data (image data) output from the scanning device 1 including a scanning microscope and the scan signal are simultaneously written in the scan data memory 2, and the sensor data in the scan data memory 2 and the display memory 3 are written.
It is possible to display the window screen based on the sensor data in the display screen displayed on the display device 5 based on the display data by switching the display data stored in the display device 5 with the switch 4. The read start address of the display data is supplied from the display memory 3 to the window start trigger generator 6 and the read start trigger is input to the scan data memory 2 when the preset read start address is reached.

FIG. 2 shows the configuration of the scan data memory 2. The output terminal of the scanning device 1 that outputs sensor data is connected to the storage device 12 via the A / D conversion unit 11, and the output terminal of the scanning device 1 that outputs a scan signal is connected to the storage device 12. The write address of the sensor data and the scan signal is designated by the write counter 13. The write counter 13 is the A of the A / D converter 11.
The write address is determined and generated based on the first clock synchronized with the / D conversion timing and the scan signal output from the scanning device 1.

On the other hand, the read address of the memory device 12 is instructed by the read address generating section including the pixel counter 14, the line counter 15, the frame counter 16 and the like. The pixel counter 14 specifies a pixel address by performing a counting operation with a second clock having a speed corresponding to the device of the data transfer destination, and is reset by a horizontal synchronization signal output from the storage device 12 together with the image data.
The line counter 15 counts the horizontal synchronizing signal output from the storage device 12 together with the image data, and is reset by the vertical synchronizing signal. The frame counter 16 counts the vertical synchronization signal output from the storage device 12. The operation of each of the counters 14 to 16 of the read address generator is controlled by the X gate signal and the Y gate signal output from the gate generator 17. That is, the pixel counter 14 counts the second clock when the X gate signal and the Y gate signal are simultaneously active, the line counter 15 counts the horizontal synchronizing signal when the Y gate signal is active, and the frame counter 16 is vertical synchronizing. Count the signals.

The gate generator 17 actively changes the X gate signal and the Y gate signal in response to the input of the X trigger signal and the Y trigger signal, and outputs a synchronizing signal (horizontal synchronizing signal, vertical synchronizing signal) output from the storage device 12. Signal), the generation of the X gate signal and the Y gate signal is stopped. The switch 4 is switched to the storage device side only while the pixel counter 14 is enabled.

Next, the operation of this embodiment configured as described above will be described. First, the write operation will be described with reference to the time chart of FIG. Sensor data obtained by two-dimensional scanning of the sample by the scanning device 1 and a scan signal used for the two-dimensional scanning are input to the scan data storage device 2.

In the scan data memory 2, the first image data (sensor data) corresponding to the pixel clock shown in FIG.
A / D conversion is performed in synchronization with the clock signal of. At this time,
The write counter 13 uses the line count signal corresponding to the horizontal synchronizing signal of the same image data, the frame count signal corresponding to the vertical synchronizing signal, and the write address based on the first clock corresponding to the pixel clock as the first clock. It occurs to the storage device 12 at a speed according to the above. As a result, the line count signal, the frame count signal, the pixel data valid signal, and the pixel data (one pixel of the image data) shown in FIG. 3 are sequentially written in the storage device 12 at the same address in synchronization with the first clock. It will be. That is, the image data and the scan signal thereof can be written to a predetermined address at the same timing.

Next, the operation when the image data stored in the storage device 12 together with the scan signal is output to the window (hatched portion) as shown in FIG. 4 will be described. First, the display start position (X1, Y1) of the window screen is set in the window start trigger generator 6.

The display position of the display memory 3 is the designated position (X
1, Y1), the switch 4 is connected to the display memory side, and the display data of the display memory 3 is displayed and output to the display device 5 in synchronization with the second clock. The read address corresponding to the display position of the display memory 3 is counted by the counter provided in the display memory 3.

As shown in FIG. 5, the window start trigger generator 6 generates an X trigger each time the display position on the display memory 3 reaches X1 on each line, and the display position is changed to the Y1 line. When it arrives, the Y trigger is generated only once.

The gate generator 17, as shown in FIG.
When the X trigger is generated, the X gate signal is activated, and when the Y trigger is generated, the Y gate signal is activated. The display position on the display device 5 is the designated position (X1, Y
When 1) is reached, both the X gate signal and the Y gate signal become active. When such a condition is satisfied, the frame counter 16 designates a read frame, the line counter 15 designates a read line (first designates the first line), and the pixel counter 14 sets the same transfer speed as that of the display memory 3. The pixel address is designated in synchronization with the second clock. As a result, the image data of the first line is read from the storage device 12 at a speed synchronized with the second clock, and the scan signal stored together with the image data is read as shown in FIG.
The image data read from the storage device 12 is displayed and output to the display device 5 via the switch 4 already switched to the storage device side.

When the reading of the image data for one line from the storage device 12 is completed, the horizontal synchronizing signal of the scan signal output from the storage device 12 is input to the pixel counter 14 and the line counter 15. The pixel counter 14 is reset by the input of the horizontal synchronizing signal, and the line counter 15 counts up the line count value. As a result, the second line of the storage device 12 is designated. At the same time, the horizontal synchronizing signal is input to the gate generator 17 to deactivate the X gate signal. Therefore, the storage device 1
This means that the image data of 2 to 1 line is read at the transfer rate synchronized with the second clock.

The display position on the display device 5 is (X
1, Y2), an X trigger is generated and the X gate signal is activated, and both the X gate signal and the Y gate signal are activated again. As a result, the storage device 1
The image data of the second line from 2 is read, and when the reading of the image data of the second line is completed, the horizontal synchronizing signal is input to the gate generator 17, the pixel counter 14 is deactivated, and the switch 4 is turned on. Switch to the display memory side. Similarly, the image data of each line is read from the storage device 12 at a speed synchronized with the second clock, and the line counter 15 is output by the vertical synchronization signal output when the reading of the image data of the last line is completed. When reset, the gate generator 17 deactivates the Y gate signal. This completes the reading of one screen stored in the storage device 12. Alternatively, the pixel data valid signal output from the storage device 12 is input to the gate generator 17 to deactivate the Y gate signal.

Thus, according to this embodiment, the scanning device 1
The sensor data output from the storage device 1 is stored in the storage device 12 together with the scan signal used in the scanning device 1.
Scan signal is read out from 2 at the same time as sensor data,
Since the read address of the memory device 12 is generated using the scan signal, the scanning device has a simple configuration and a simple operation of inputting the second clock having an arbitrary transfer rate to the pixel counter. The sensor data from 1 can be speed converted. Further, since the image synchronization signal and the image data always match, it is possible to prevent the occurrence of image shift when the image data is displayed and output, and to reproduce a high quality image.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. In this embodiment, there are three A / D converters for A / D converting the sensor data input from the scanning device.
The D converters 11-1 to 11-3 are provided side by side, and a storage device 12 'including four memories 1 to 4 is provided. Further, a FIFO 21 that performs speed conversion between a clock synchronized with the storage device 12 'and a clock required by a device of a data transfer destination, a selector 22 that performs parallel / serial conversion of data read from the storage device 12', and a selector 22. A D / A converter 23 for converting the serial data output from the device into analog data is provided. The memory device 12 'uses a synchronous DRAM and the clock used is C
It depends on the PU 24 or the memory controller.

The memory device 12 'is configured to output the sensor data and the scan signal stored at the address generated by the read address generating unit configured as shown in FIG. The read address generating unit stores the storage device 12 'based on the pixel clock output from the transfer destination device.
A pixel counter 26 for counting the pixel addresses of the pixels, a line counter 27 for counting the horizontal synchronizing signals output simultaneously from the storage device 12 'with the image data, and a vertical synchronizing signal output simultaneously with the image data from the storage device 12'. And a frame counter 28 for counting.

When the operation of the storage device 12 'is sufficiently fast as compared with the sensor data output from the scanning device, the memories 12-1 to 12-4 to be written / read out are switched by the switch 29 shown in FIG. It is possible to switch in frame units or pixel units. Switch 2
The write counter 13 and the read address generating unit address the memory designated by 9.

Next, the operation of this embodiment configured as described above will be described. Scanning device to A / D converter 11
The digital image data input to the memory and converted from the analog sensor data and the scan signal of the same image data captured from the scanning device together with the sensor data are stored in the memory 1.
Entered in 2. On the other hand, the write counter 13 executes the counting operation based on the scan signal from the scanning device.
The count value is instructed to the storage device 12 'as a write address, and the digital image data and the scan signal (clock signal, line count signal, frame count signal, valid signal) are simultaneously stored in the instructed write address. Therefore, the write address continues to be incremented regardless of the state of the valid signal.

A memory switching operation for converting an interlaced signal input from the scanning device into a non-interlaced signal will be described. Note that memory switching is performed in line units.

When the image data of the odd field is input, the switches 29 are used to switch the memories 12-1 and 12-3 line by line, and the image data of the odd field is switched to the corresponding image data.
When the image data of the even field stored in one of the memories 12-1 and 12-3 is input, the memory 12-2, 12-4 is switched by the switch 29 for each line, and the image data of the even field is changed to that of the corresponding image data. One memory 12-2, 12
Store in -4.

When outputting the image data stored in the storage device 12 'to the display system, the four memories are switched by the switch 29 in the order of 12-1, 12-2, 12-3, 12-4 for each line. Read. As a result, the storage device 12 '
The interlaced signal stored in is converted into a non-interlaced signal and output to the display system.

Further, writing of sensor data from the scanning device to the memory, reading of memory contents from the CPU 24, reading of memory contents from the display system, I / I
It is possible to read the stored contents of the memory to F in parallel while switching in pixel units, line units, and the like.

Further, as shown in FIG. 9, when the range of effective pixels in the display system is changed, the scan signal of the sensor data from the scanning device is changed or the address of the counter is changed. For example, when the effective signal output together with the image data from the storage device 12 'indicates that the effective pixel has ended, if a value of a predetermined number of pixels (for example, 128 pixels) is added to the count value of the pixel counter, the screen An area with no data is formed on the right side. Further, when the valid line ends, if a value of a predetermined line (for example, 64 lines) is added to the count value of the line counter, an area having no data is formed on the lower side of the screen. That is, the size has been converted.

(Third Embodiment) FIG. 10 shows the functional arrangement of a scan conversion apparatus according to the third embodiment. In this embodiment, the horizontal synchronizing signal output together with the image data from the storage device 12 'can be input to the frame counter 28 via the switch S1. The other configuration is the above-mentioned second.
It is similar to the embodiment.

The present embodiment is an example in which three-dimensional image data formed by stacking two-dimensional slice images on the XY plane as shown in FIG. 11 is scan-converted in the Z-axis direction. A plurality of frame image data 1 obtained by slicing the object shown in FIG.
N is input from the sequential scanning device to the storage device 12 'and stored together with the scan signal of each frame image. The stored contents of the memory in which the frame image and its scan signal are stored can be represented by an image as shown in FIG. Also,
FIG. 13 is a time chart in which only the sync signal is extracted.
As shown in (a). There is one vertical sync signal at the beginning of one frame and a horizontal sync signal at the beginning of each line in the frame.

The switch S1 is set to the state shown in FIG. 10, and the image data is stored in the memory device 12 'as shown in FIG.
Counter 2 with the synchronization signal output at the timing shown in
By operating 7 and 28 to generate an address, the frame image data 1 to 1 are synchronized with the read clock.
N is sequentially read.

On the other hand, when reading the two-dimensional image data in the Z-axis direction from the three-dimensional image data stored in the storage device 12 ', the switch S1 is switched so that the horizontal synchronizing signal is input to the frame counter 28. As a result, the horizontal synchronizing signal is input to the frame counter 28, so that FIG.
The line counter 2 is synchronized with the timing synchronization signal shown in (b).
7. The frame counter 28 is counted up. By stopping the count of the line counter 27 and operating the frame counter 28 with the horizontal synchronizing signal, a tomographic image in the Z-axis direction can be obtained. If both the frame counter 28 and the line counter 27 are operated by the horizontal synchronization signal, XY
An oblique tomographic image having a predetermined angle with respect to the plane can be obtained.

As described above, according to this embodiment, the scan signal is simultaneously stored together with the image data from the scanning device.
Since the horizontal synchronizing signal stored in 2'and read out together with the image data from the storage device 12 'can be input to the frame counter 28, a predetermined amount can be obtained from the three-dimensional image data to the tomographic image in the Z-axis direction or the XY plane. An oblique tomographic image with an angle can be easily created.

(Fourth Embodiment) There is a gap between frames in the frame images stored in the storage devices 12 and 12 'provided in the above-described embodiments. For example, the effective image size is 128 x 1
28 pixels, the image size including the sync signal is 256
Assuming x144 pixels, the number of pixels assigned to the synchronization signal is 128 pixels in the horizontal direction and 25 pixels in the vertical direction.
This means 6 × 16 pixels. That is, a gap of 16 lines is generated between the frames. Further, each line forming one frame also has an invalid pixel including a horizontal synchronizing signal.

Therefore, in this embodiment, the storage devices 12, 1 are
As shown in FIG. 14, various supplementary data are put in the gap corresponding to the synchronizing signal portion of the image data to be stored in 2 ', and when the image data is read out from the storage devices 12 and 12' later, based on the synchronizing signal. To retrieve supplementary data. Image data such as image name and size are provided as supplementary data to be inserted in the gap between frames. The supplemental data to be put in the invalid pixel portion of each line includes the line number of each image, a signal indicating the scanning direction, a correction signal for the effective image (shading correction, etc.), and other data.

As described above, according to the present embodiment, various supplementary data are put in the synchronizing signal portion of the image data, and the synchronizing signal read out at the same time when the image data is read from the storage devices 12 and 12 'later is used. Since the supplementary data is extracted from the image data, the supplementary data can be freely taken in and out of the image data using all the synchronization signals, and can be used for the subsequent processing.

Further, by inserting supplementary data in the synchronizing signal portion, the image signal output from the scanning device can be transferred to the NTS.
It can be directly converted into a C signal. FIG. 15 shows a time chart when the image signal from the scanning device is directly converted into the NTSC signal. As shown in the figure, a signal corresponding to a blanking signal and a signal corresponding to a burst signal are written as supplementary data during a low level period (synchronization signal portion) of the scan signal. Also, the pulse width of the scan signal itself is adjusted according to the width of the supplementary data to reconstruct the horizontal synchronizing signal. As a result, the reconstructed horizontal synchronizing signal shown in FIG. 15 and the digital image data in which the supplementary data is written in the synchronizing signal portion are stored in the storage devices 12, 1.
2'is simultaneously written and simultaneously read.
Therefore, the signal from the scanning device can be easily converted directly into the NTSC signal.

(Fifth Embodiment) FIG. 16 shows the arrangement of a scan conversion apparatus according to the present embodiment. The scan conversion apparatus of this embodiment is configured to convert an interlaced scan video signal into a non-interlaced scan video signal.
The input video signal is input to the A / D conversion circuit 31 to be converted into digitized image data, and the input video signal is input to the sync separation circuit 32 to extract the sync signal to form the video signal. The image data and the synchronization signal are stored in the same address of the memory 33 at the same time in synchronization with the first clock. The write address on the memory for storing the image data and the synchronizing signal is generated by the write address counter 34 which counts the first clock.

The first clock is a clock having a cycle corresponding to one pixel of the input video signal. The sync signal of the input video signal includes a vertical sync signal (V), a horizontal sync signal (H), and an effective pixel signal (BLN) indicating a display effective pixel.
K), a field discrimination signal (O / E) for discriminating between an even field and an odd field. The vertical synchronizing signal (V) and the field discrimination signal (O / E) are input to the write address counter 34 and used for clearing the write address.

A V-cycle detection circuit 35 for detecting the cycle of the vertical synchronizing signal (V ') by counting the vertical synchronizing signal (V') read from the memory 33 together with the image data with the second clock is provided. The cycle count value detected by the V cycle detection circuit 35 is given to the selection circuits 36 and 37. The cycle count value is doubled and given to the selection circuit 36. The selection circuit 36 has two input lines, an input line to which a doubled cycle count value is input and an input line to which a zero value is given, and the two input lines use a vertical synchronization signal (V '). And switch. The selection circuit 37 has two input lines, an input line for inputting the cycle count value and an input line for giving a 0 value, and these two input lines are read out from the memory 33 at the same time as the horizontal synchronizing signal (H Use ′) to switch. The values of the input lines selected by the selection circuits 36 and 37 are input to the corresponding adders 38 and 39, respectively.

The output of the read address counter 40 which counts the second clock and whose count value is cleared by the vertical synchronizing signal (V ') is used as the read pixel address.

The vertical synchronizing signal (V ') read out from the memory 33 together with the image data is masked by the mask circuit 41. The mask circuit 41 outputs the field discrimination signal (O / E ′) read out from the memory 33 together with the image data.
The vertical synchronizing signal (V ') is masked based on Specifically, when the field discrimination signal (O / E ') is at H level (representing an odd field), the vertical synchronizing signal (V') is fixed at H level and the field discrimination signal (O / E ') is At the L level (representing an even field), the vertical synchronizing signal (V ') is passed as it is. The image data read from the memory 33 is converted into an analog signal by the D / A conversion circuit 42 and output as an output video signal.

The operation for each line will be described with reference to FIG. Actually, the image data and the synchronizing signal are sequentially and continuously stored in the memory 33, but the memory is two-dimensionally represented for the sake of expression.

When the interlaced scanning video signal is input, first the image data of the even field and the synchronizing signal are sequentially stored in the memory 33 in synchronization with the first clock (F1). At this time, the write address of the memory 33 is counted up by the write address counter 34 in synchronization with the first clock. Since interlaced scanning is performed, even lines are stored in the order of 0, 2, 4, ... When the writing of the even field is completed, the write address counter 34 is cleared by the vertical synchronizing signal (V), and the field discrimination signal (O / E ') becomes H level. After that, the image data of the odd field and the synchronizing signal are written in the memory 33 in synchronization with the first clock.
The write address counter 34 is reset to 0 after writing data for four fields by the vertical synchronizing signal (V) and the field discrimination signal (O / E). In order to convert an interlaced scanning video signal into a non-interlaced scanning video signal, the read speed becomes twice as fast as the interlaced scanning, so at least four fields (F1 to F)
This is because the video signal of 4) is required.

On the other hand, in the non-interlaced scanning, the memory 3
When reading the image data and the sync signal from 3, the read address counter 40 is counted up in advance by the second clock, and the cycle of the read vertical sync signal (V ′) is checked by the V cycle detection circuit 35.

Next, two fields (F
After confirming that the video signal of (1), (F2) has been stored, the read address counter 40 is reset, and thereafter counting is started at the second clock.

First, the first and second fields (F1, F2) are read from the memory 33 by using the adder 39 and the selection circuit 37. In order to read out as an image of non-interlaced scanning, the image data and the sync signal stored in the memory 33 must be read out in the order of even fields and odd fields (circled numbers 1, 2, 3, ...).
At the start of reading the first frame, the selection circuits 36 and 37
Select 0-value input lines with. By operating the read address counter 40 from this state with the second clock, the pixel addresses of the line (0) of the first field (F1) are sequentially generated.

After the final pixel address in line (0), which is an even field, is specified, but before the start pixel address in line (1), which is an odd field, is generated, the horizontal synchronization signal (H) of line (1) is generated. The address of ′) is designated. The selection circuit 37 selects the output of the V cycle detection circuit 35 by the input of the horizontal synchronizing signal (H ').

In synchronization with the output of the horizontal sync signal (H ') from the memory 33, the read address counter 40 generates the head pixel address of the line (1). As a result, the adder 39 adds the head pixel address of the line (1) to the output of the V cycle detection circuit 35. here,
The output of the V cycle detection circuit 35 is the count value of the second clock number corresponding to one field. Further, the storage address of line (1) in the memory 33 is stored at an address deviated by one field from the original storage address of line (1) of the first frame. Therefore, the output of the adder 39 represents the leading pixel address of the line (1) of the first frame on the memory 33.

Line (2) after the last pixel address in line (1) is specified and before the start pixel address of line (2), which is an even field, is generated.
The address of the horizontal synchronizing signal (H ') is designated. The selection circuit 37 selects the input of 0 value by the input of the horizontal synchronizing signal (H ') of the line (2). As a result, the start pixel address of the line (2) on the memory 33 output from the read address counter 40 is directly added to the adder 39.
And is given to the memory 33.

Similarly, every time the horizontal synchronizing signal (H ') is input to the selection circuit 37, the V cycle count value and the 0 value are switched, and the even field and the odd field are alternately addressed in the memory 33. The image data of the first field and the sync signal are read from the memory 33 in the order of 0, 1, 2, ... Lines designated.

As described above, the speeds of the interlaced scanning and the non-interlaced scanning are twice different.
As shown in FIG. 18, in order to match the relative times of both, the same frame must be read and displayed twice consecutively by interlaced scanning. In this embodiment, the difference in speed is absorbed by resetting the read address counter 40 with the vertical synchronizing signal (V ') every frame (one frame in two fields of odd number and even number).

Next, add the third and fourth fields (F3, F4) from the memory 33 to the adders 38 and 39 and the selection circuit 3.
Read using 6,37. The selection circuit 36 switches the input line every time the same frame is read twice by the vertical synchronizing signal (V '). As shown in FIG. 18, when the first and second fields are read twice, the input is switched to a value obtained by doubling the V cycle count value and output to the adder 38.

At this time, since the start pixel address of the line (0) of the first field (F1) in the memory 33 is input from the adder 39 to the adder 38, the V cycle count value is doubled to this address. By adding the values,
The address on the memory 33 is shifted by two fields and converted into the leading pixel address of the line (0) of the third field (F3). Thereafter, until the second frame is read twice, the value obtained by doubling the V cycle count value is added by the adder 38. Therefore, the selection circuit 37 and the adder 39 operate as described above, Lines of 3,4 fields will be addressed in the order 0,1,2 ...

As described above, the image recorded by the interlaced scanning is read by the non-interlaced scanning and the scan conversion is performed. Thus, according to this embodiment,
Since the sync signal and the image data are simultaneously stored at the same address in the memory 33, the image data and the sync signal at the speed required at the time of reading can be easily obtained. Further, by using the input synchronizing signal and the synchronizing signal read from the memory 33, scanning conversion and speed conversion can be easily performed without newly generating a signal.

(Sixth Embodiment) FIG. 19 shows the functional arrangement of a scanning conversion apparatus according to this embodiment. The present embodiment includes a memory 50 having a bit width capable of storing image data and a sync signal at the same address and having a capacity capable of storing 512 sheets of data for 1024 × 1024 words.

Here, the information amount of the video for one screen is 102
It is set to 4 × 1024 words. As shown in FIG.
The information for one screen includes all the parts for synchronizing, in addition to the part where the actual image exists. 1 word is
It is the storage capacity of the memory per one memory address. For example, each color of RGB of a color image has a resolution of 8 bits to make a total of 24 bits, and sync signals (vertical sync signal V, effective vertical sync signal HEN, horizontal sync signal H,
If 4 bits are used to record the effective pixel signal DEN), the total is 28 bits. Furthermore, if a margin is added to the above 24 bits to increase 6 bits to 30 bits, 1
The word will be 34 bits.

The write address counter 51 controls writing to the memory 50. The write address counter 51 generates a memory address for writing the image data and its synchronizing signal based on the write clock WRCLK.

The reading control of the memory 50 is performed by the frame address counter 52, the line address counter 53, and the pixel address counter 54. These address counters 5
2 to 54, the read clock RD is a memory address for the memory 50 to read both the image data and the synchronization signal.
It is generated for each frame, line, and pixel in synchronization with CLK. The data latch circuits 55 to 5 provided corresponding to the initial values given to the address counters 52 to 54, respectively.
Holds at 7.

The pixel address counter 54 has a switch S.
The read clock RDCLK is input to the clock terminal via W1, and the horizontal synchronizing signal H'via the switch SW2.
Is input to the set terminal.

The line address counter 53 receives the horizontal synchronizing signal H'via a switch SW3 having three terminals A to C. The horizontal synchronizing signal H'is input to the clock terminal of the line address counter 53 through the terminal A of the switch SW3, and the set terminal is connected to the terminal B of the switch SW3.
The horizontal synchronizing signal H'is input through.

In the frame address counter 52, the horizontal synchronizing signal H'and the vertical synchronizing signal V'are input to the clock terminal via the switch SW4, and the horizontal synchronizing signal H'to the set terminal via the switch SW5.

The CPU resets the address counters 52 to 54 and controls the switching of the switches SW1 to SW5.
58 executes. An operation of storing a non-interlaced scanning video signal (including a synchronization signal) obtained by slicing a three-dimensional object into 512 images in the memory 50 and controlling reading of the image from the memory 50 to display a tomographic image explain.

The non-interlaced scanning video signal separated into the image data and the synchronizing signal is stored in the address generated by counting the write clock WRCLK by the write address counter 51. It is assumed that the image data of 512 slice images is stored in the memory 50 together with the synchronization signal.

When the video signal is read from the memory 50, the output addresses of the address counters 52 to 54 are combined to determine the read address. Since the combined read address has a size of 1024 × 1024 words in one screen, it can be expressed as a binary number with 10 × 10 bits, and since 512 sheets can be stored, a total of 29 bits of addresses are obtained. As shown in FIG. 26, a 29-bit composite address (frame address, line address, pixel address) is assigned. The frame address counter 52, the line address counter 53, and the pixel address counter 54 are 9 bits, 10 bits, and 1 bit, respectively.
It is 0 bit and becomes 0 when the maximum count is incremented by 1.

21, 22, and 24 show the initial values of the respective address counters 52 to 54 when the read address is controlled to display only a specific image from the memory 50.

With reference to FIG. 21, the operation for displaying only one screen of the 0th sheet will be described. First, set the switches SW1 to SW5 to ON, OFF, A side, A
Side, set to OFF. With such a connection, the pixel address counter 54 is set to 0 by the read clock RDCLK.
The line address counter 53 counts up from 0 to 1023 according to the horizontal synchronizing signal H ′ read from the memory 50 and sequentially shifts the read line.

At this time, the frame address counter 52
Since there is no signal input to the clock terminal of the switch SW4 by setting the switch SW4, the frame address of the same screen continues to be specified. Therefore, as shown in FIG.
Only the 0th to 0th images are read and displayed. By giving an initial value from the data latch circuit 55 to the frame address counter 52, only the nth image is stored in the memory 50.
Can be read from.

With reference to FIG. 22, an operation for reading a tomographic image having an angle of 26.5 degrees in the Z direction from 512 captured images will be described. First, switch S
W1 to SW5 are set to be ON, OFF, B side, B side, and OFF. With such a setting, the pixel address counter 54 sets 0 to 0 by the read clock RDCLK.
The horizontal synchronizing signal H ′ is counted up to 1023 and the line address counter 53 reads it from the memory 50.
Sets the line address data latch value by
The frame address counter 52 is counted up from 0 to 511 by the horizontal synchronizing signal.

The value to be written in the line address data latch circuit 55 at this time will be described with reference to FIGS. As shown in FIG. 7A, among the data written in the memory 50 in synchronization with the write clock signal WRCLK, the data to be displayed as a video (valid data).
And there is data without video (invalid data).

In this embodiment, the period of invalid data is effectively utilized, and each address counter 51 to 51 is used during the period of invalid data.
A value given as an initial value from the data latch circuits 55 to 57 is previously written in 54 by the CPU 58. Data latch circuits 55-5 are provided to the address counters 51-54, respectively.
If the timing for setting the initial value from 7 is the falling edge of the horizontal synchronizing signal H ', it may be set in each of the data latch circuits 55-57 one clock before.
As shown in FIG. 20B, the value to be set in each of the data latch circuits 55 to 57 is written in the data before the falling of the horizontal synchronizing signal H '(the hatched portion of the valid data).

In this embodiment, the data width of the image data is 30.
Since it is a bit, the lower 10 bits, 10 bits, and 9 bits are assigned to the pixel address, line address, and frame address, respectively, as shown in FIG. 26, and the value is written to the corresponding bit. As shown in FIG. 22, if the value written as the line address in the invalid data area before the fall of the horizontal synchronizing signal H ′ is increased by “2”, the number of the line address increases by 2 each time the frame address increases by 1. 26. in the Z direction from the XY plane.
It is possible to obtain a tomographic image having an angle of 5 degrees.

The operation in the case of displaying a tomographic image in the Z direction of the 50th line from the 512 slice images captured in the memory 50 will be described with reference to FIGS.
First, set the switches SW1 to SW5 to ON and OF, respectively.
Set to F, B side, A side, ON. By applying the read clock RDCLK while maintaining this set state, the pixel address counter 54 is read by the read clock RDC.
The line address counter 53 and the frame address counter 52 count up from 0 to 1023 by LK.
Are data latch circuits 56, 5 according to the horizontal synchronizing signal H '.
A value of 5 is set. At this time, the horizontal synchronizing signal H'is adjusted so that the data size for one screen is 1 as shown in FIG.
In order to make 024 × 1024 words, the value shown in FIG. 24 is written in advance from the CPU in the shaded position in FIG.

As described above, according to this embodiment, the synchronizing signal is written in the memory 50 together with the image data, and the reading address is generated by using the synchronizing signal read out together with the image data from the memory 50. A tomographic image at an arbitrary angle can be extracted very easily from the stored three-dimensional image data.

The above description is based on the embodiment.
The invention of the present application includes the following inventions. (1) A / D the image data acquired by the scanning device
An A / D converter for converting, a write address generator for counting a sync signal of the image data to generate a write address of the image data, and a pair of the image data and the sync signal for the writing. The read address of the memory is determined based on a plurality of memories to be stored at the address designated by the embedded address generation unit, a synchronization signal read together with the image data from the memory, and a read clock corresponding to the transfer speed of the data transfer destination. And a memory switching means for switching the memory for writing / reading the image data and the synchronizing signal based on the scanning method of the image data and the synchronizing signal.

According to the present invention, the image data and the sync signal are stored in the memory as a set, and the read address of the memory is designated based on the sync signal and the read clock. At this time, the memory for writing / reading the image data and the synchronizing signal is switched by the memory switching means based on the scanning method of the image data and the synchronizing signal. Therefore, scan conversion can be realized only by switching the memory. (2) In the invention of claims 1, 2, or (1), when the effective pixel in each line of the image data input from the scanning device is completed, or the effective line in one frame of the image data is completed. At this time, the count value of the write address generator is added with the count value of a predetermined pixel or a predetermined line.

According to the present invention, when the effective pixel in each line of the image data is completed, or when 1 of the image data is
When the valid line in the frame is completed, the count value of the write address generation unit is added with the count value of a predetermined pixel or a predetermined line. As a result, conversion of the frame rate is easily realized. (3) In the invention of claim 2 or (2), supplementary data having predetermined information is inserted in the synchronization signal portion of the image data stored in the data storage section.

According to the present invention, since the supplementary data having the predetermined information is inserted in the synchronizing signal portion of the image data, the supplementary data can be taken out based on the synchronizing signal at the time of reproducing the image data, and the subsequent processing Can be used for. (4) A / D the image signal acquired by the scanning device
Converted and converted to image data represented by a predetermined number of bits A
/ D converter, a write address generator for counting the sync signal of the image signal to generate a write address of the image data, and the image data and the sync signal for the write address generated by the write address generator A pair of data storage units, a read pixel counter that generates a pixel address by counting a read clock according to the transfer speed of a data transfer destination, and a synchronization signal that is output from the data storage unit together with image data. And a read line counter for generating a line address by counting the horizontal sync signal included in the vertical sync signal and the horizontal sync signal included in the sync signal read together with the image data from the data storage unit. A read frame counter for generating a frame address, the read pixel counter, and the read Read address designating means for designating a read address of the data storage unit by synthesizing respective addresses generated by the line counter and the read frame counter, and converting a vertical synchronizing signal and a horizontal synchronizing signal input to the reading frame counter. A scan conversion device comprising: a switch unit that switches based on an image display mode.

According to the present invention, the horizontal synchronizing signal is input to the read frame counter which generates the frame address of the read addresses of the data storage section depending on the display form of the converted image. Therefore, since the frame address of the read image can be changed by the horizontal synchronizing signal, a tomographic image having an arbitrary angle can be obtained by combining with the count value of the read line counter. (5) A / D the image signal acquired by the scanning device
Converted and converted to image data represented by a predetermined number of bits A
/ D converter, a write address generator for counting the sync signal of the image signal to generate a write address of the image data, and the image data and the sync signal for the write address generated by the write address generator And a data storage unit that stores the data as a set, and a cycle of a vertical synchronization signal included in a synchronization signal read from the data storage unit is detected by a clock count operation based on a clock speed of a data transfer destination, and the data storage unit stores the data storage unit. 1 in the department
Vertical sync cycle detecting means for detecting the cycle of the vertical sync signal corresponding to the field width, and a vertical sync signal read from the data storage section for counting operation based on a read clock corresponding to the clock speed of the data transfer destination. And a horizontal synchronizing signal read from the data storage section are input, and the count value of the cycle detected by the vertical synchronizing cycle detecting means is added to the count value output from the read address counter. A scanning conversion device comprising: a read address designating unit for designating a read address of the data storage unit by adding every other line based on a horizontal synchronizing signal.

According to the present invention, the read address is output from the read address counter that has counted based on the read clock corresponding to the clock speed of the data transfer destination, and the read address is detected by the vertical synchronization cycle detecting means. The count value of the cycle is added every other line or every other line based on the horizontal synchronizing signal. Therefore, the read address is shifted by one field every other line or every other line in synchronization with the horizontal synchronizing signal. Therefore, if the image data acquired by the interlaced scanning is stored in the data storage unit, it is regarded as a non-interlaced scanned image. Can be read. The present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention.

[0090]

As described above in detail, according to the present invention, the image data forming the video signal and the synchronizing signal thereof are set and stored in the memory at the same time, so that the synchronizing signal generating circuit is not provided. It is possible to provide an image storage device and a scan conversion device capable of reproducing a synchronization signal according to a read speed together with image data with a simple configuration.

According to the present invention, speed conversion to an arbitrary speed is possible without using a line buffer or the like, and
(EN) It is possible to provide an image storage device and a scan conversion device that can always match image data and its synchronization signal and can very easily create a high-quality reproduced image without pixel shift.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a scan data storage device provided in the first embodiment.

FIG. 3 is a time chart of a write operation in the first embodiment.

FIG. 4 is a diagram showing a window start position.

FIG. 5 is a time chart of a read operation in the first embodiment.

FIG. 6 is a functional block diagram of a second embodiment of the present invention.

FIG. 7 is a diagram for explaining a memory switching operation in the second embodiment.

FIG. 8 is a diagram showing a writing mechanism provided in the second embodiment.

FIG. 9 is a diagram for explaining a frame speed conversion operation.

FIG. 10 is a functional block diagram of a third embodiment of the present invention.

FIG. 11 is a diagram showing an example of data of a three-dimensional image.

FIG. 12 is a diagram showing a relationship between each frame image and a timing signal.

FIG. 13 is a diagram showing synchronization signals before and after Z-axis conversion.

FIG. 14 is a diagram showing a relationship between a synchronization signal and image data.

FIG. 15 is a time chart for explaining a conversion operation for converting image data into an NTSC signal.

FIG. 16 is a functional block diagram of a fifth embodiment of the present invention.

FIG. 17 is a diagram showing a relationship between a sync signal and a write line on the memory of the fifth embodiment, and a conversion operation from an interlaced image to a non-interlaced image.

FIG. 18 is a diagram for explaining a reading method for speed absorption in a conversion operation from an interlaced image to a non-interlaced image.

FIG. 19 is a functional block diagram of a sixth embodiment of the present invention.

FIG. 20 is a diagram showing a relationship between a sync signal, valid / invalid data in image data, and supplementary data.

FIG. 21 is a diagram showing a specific example of supplementary data for displaying the Oth image in the sixth embodiment.

FIG. 22 is a diagram showing a specific example of supplementary data for displaying a tomographic image at an arbitrary angle in the sixth embodiment.

FIG. 23 is a plan view of a specific example showing an image area and a non-video area in one screen.

FIG. 24 is a diagram showing a specific example of supplementary data for displaying a tomographic image in the Z direction on the 50th line in the sixth embodiment.

FIG. 25 is a plan view showing an image area and a non-video area in one screen.

FIG. 26 is a diagram showing bit allocation of supplementary data to each address counter.

FIG. 27 is a configuration diagram of a conventional scan conversion device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Scanning device, 2 ... Scan data storage device, 3 ... Display memory, 4 ... Switch, 5 ... Display device, 6 ... Window start trigger generator, 11 ... A / D conversion part, 12, 12 '
... storage device, 13 ... write counter, 14 ... pixel counter, 15 ... line counter, 16 ... frame counter,
17 ... Gate generator, 33, 50 ... Memory, 35 ... V cycle detection circuit, 36, 37 ... Selection circuit, 38, 39 ... Adder, 40 ... Read address counter, 55-57 ... Data latch circuit, 58 ... CPU .

Claims (3)

[Claims] 1. An image storage device for storing image data of which horizontal and vertical sizes are defined by a synchronization signal, wherein the image data and the synchronization are set at a write address determined based on a count value of the synchronization signal. An image storage device characterized by storing signals and signals at the same time. 2. An A / D converter for A / D converting an image signal acquired by a scanning device to convert it into image data represented by a predetermined number of bits, and an image signal of the image signal input to the A / D converter. A write address generation unit that counts a synchronization signal to generate a write address of the image data, and a data storage unit that stores the image data and the synchronization signal as a set at the write address generated by the write address generation unit. A read address generation unit for generating a read address of the data storage unit based on a synchronization signal read out together with the image data from the data storage unit and a read clock corresponding to a transfer speed of a data transfer destination. Characteristic scan conversion device. 3. An A / D converter for A / D converting an image signal acquired by a scanning device and converting the image signal into image data represented by a predetermined number of bits; and a synchronizing signal of the image signal for counting the image. A write address generation unit that generates a write address of data, a data storage unit that stores the image data and the synchronization signal as a set at the write address generated by the write address generation unit, and a clock speed of a data transfer destination A read pixel counter that counts a read clock according to the above to generate a pixel address of the data storage unit, and a horizontal sync signal included in a sync signal that is output together with image data from the data storage unit to count the data. A read line counter for generating a line address of the storage unit, and the image data output from the data storage unit. A read frame counter that generates a frame address by counting a vertical synchronization signal and a horizontal synchronization signal included in the synchronization signal, and a synchronization signal output together with the image data from the data storage unit, depending on the display form of the converted image. A unit for inserting data, a frame data latch unit for storing the contents related to the frame address from the supplementary data inserted in the synchronization signal output from the data storage unit, and the supplementary data stored in the frame data latch unit. First switch means for setting the contents in the read frame counter; a line data latch part for storing contents related to a line address from supplementary data inserted in the synchronization signal output from the data storage part; The contents of the supplementary data stored in the line data latch unit are Second switch means for setting the read line counter; a pixel data latch section for storing the content related to the pixel address from the supplementary data inserted in the synchronization signal output from the data storage section; Third switch means for setting the content of the supplementary data stored in the latch section in the read pixel counter, and whether or not a synchronization signal is input to the read pixel counter, the read line counter, and the read frame counter. A scanning conversion device comprising a fourth switching means for switching.