JP2561597B2 - Video signal acquisition method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, when an image is displayed on a liquid crystal display panel based on a video signal output from a CCD camera or a video signal in a television signal, the video signal is temporarily stored in a random access memory for video. The present invention relates to a method of taking in a case.

[0002]

2. Description of the Related Art Today, a video signal of Japan is composed of an image of one screen made up of 525 scanning lines, and is divided into a field by odd-numbered scanning lines and a field by even-numbered scanning lines by interlaced scanning, and one field. Are used as 262.5 scanning lines, and a video signal for one frame (one screen) in two fields is used.

By the way, in recent years, an image formed by a video signal is often reproduced on a small liquid crystal display plate, and when a liquid crystal display plate is used, it is limited by the number of pixels formed on the display plate. The sampling period during the horizontal scanning period is adjusted according to the number of pixels of, and the video data of one scanning line is formed into a digital signal of 4 bits or the like by the number of video data equal to the number of dots of one line on the liquid crystal display panel. However, scanning lines in one frame are appropriately thinned according to the number of pixels in the vertical direction.

As described above, the video signal included in the video signal is used as digitized image data, and when the image is displayed on the liquid crystal display panel by the image data, the digitized image data is temporarily stored in the video random access memory. The image data for one frame stored in the random access memory for video is sequentially read and displayed on the liquid crystal display panel.

Conventionally, when the image data for one screen is stored in the video random access memory with the video signal of two fields, the thinning rate of the odd field and the even field is set to the same rate, and formed by 525 scanning lines. When the image data for liquid crystal display is formed from the image of one screen, the image data is taken in from the entire screen as evenly as possible.

[0006]

As described above, when image data for one screen is formed by a video signal of one frame, the video signal has a time of about 1/60 second in an even field and an odd field. When image data for one screen is formed from a video signal of one frame by a video signal that captures a moving subject, an image is misaligned between even lines and odd lines in one frame. Occurrence of a portion may cause a defect of degrading image quality.

[0007]

SUMMARY OF THE INVENTION The present invention distinguishes between odd and even fields based on a vertical sync signal,
When writing the image data digitized from the video signal to the video random access memory while outputting the address signal whose count value is sequentially increased based on the horizontal synchronization signal, every time the horizontal synchronization signal is required. A value obtained by adding 1 is additionally output as the count value of the line addressing circuit. In one field, the image data based on the video signal in each scanning period is taken in, and in the other field, the required number is added. It is assumed that only the image data in one scanning line for each required number of horizontal synchronizing signals is fetched while sequentially outputting the numerical value to which 1 is added from the line addressing circuit.

[0008]

[Operation] According to the present invention, when the image data of each scanning period is captured in one of the even field and the odd field, and the count value of the line addressing circuit is increased based on the horizontal synchronizing signal. Since the count value is increased by one extra for each required number, only one line having no image data is formed for each required number, and in the other field, an image based on the video signal in the required number of scanning lines is formed. Since the data is captured in the line area having no image data, the image data of a part of the scan lines forming the other field is added to the line having no image data by the scan line of one field to obtain one screen. It is possible to obtain image data that forms

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit example for writing image data in a random access memory for video (hereinafter simply referred to as V-RAM) embodying the present invention is input to a video signal input terminal 11 as shown in FIG. The vertical separation signal is extracted from the video signal by the sync separation circuit 13, the video signal is digitized into a 4-bit signal which is image data of 16 gradations by the analog-digital converter 15, and an image of 2 pixels is obtained through the data adjustment circuit 17. The data is collectively written in the V-RAM 25 as 1-byte information. When writing this image data, the vertical sync signal extracted from the video signal and the horizontal sync output from the horizontal sync oscillator 19 in synchronization with the video signal are output. Image data for forming a screen with 320 lines by one line of 480 dots by a signal and a horizontal scanning period signal. The write timing and the write address and controls with a write control circuit 30.

As shown in FIG. 2, the write control circuit 30 has a field determination circuit 31 for outputting a field signal for identifying the odd field or the even field to the B signal by the horizontal sync signal H and the vertical sync signal V. A field signal for identifying whether the image data output from the data adjusting circuit 17 to the data bus is a digitized video signal in an odd field or a digitized video signal in an even field. Is output to the B signal.

Further, there is a fetch section determining circuit 33 to which the field signal and the horizontal scanning period signal h excluding the blanking period in the horizontal scanning line period are inputted, and the fetch section determining circuit 33 is an odd field. And a horizontal scanning period signal for a predetermined number of scanning lines among the 262.5 horizontal scanning lines in the even field is output to the C signal as a capture period signal.

In the present embodiment, the horizontal scanning period signals for the first few scanning lines in each field are cut off, and 240
The horizontal scanning period signal for the scanning line of the book is passed. Then, the fetch period signal is input to the read control circuit 35 and the address reference signal output circuit 41.
The address reference signal output circuit 41 outputs the address reference signal to the D signal each time the fetch period signal is input, and the fetch period signal is set as the required number of 3 times. A 2-bit address reference signal, which is one extra value as the address reference signal value, is output every time it is input. When the signal indicating the odd field is input as the field signal, the acquisition period 1 to 3 each time a signal is input
0 to 2 signal indicating the value of (binary 00 to 10)
Are sequentially output as address reference signals, and when a signal indicating an even field is input as a field signal, a 3 signal (binary 11) that indicates a value of 4 every time a capture period signal is input three times Is output as an address reference signal.

Further, the line address designation circuit 43 to which the address reference signal is input outputs the line address signal based on the address reference signal,
When a signal indicating a value of 1 to 3 is repeatedly output as the address reference signal, the value of the line address signal is sequentially incremented by 1 every time the capture period signal is output based on the address reference signal. When a 3 bit is output three times and a 9-bit line address signal having a value of 0 to 319 is output by incrementing the value by 1 and the signal indicating the value of 4 is repeatedly output as the address reference signal. Outputs a line address signal having a value obtained by subtracting 1 from a multiple of 4 every time the capture period signal is input three times.

Further, the read control circuit 35 receives the address period signal from the address reference signal output circuit 41 and the field signal from the field determination circuit 31 in addition to the capture period signal from the capture period determining circuit 33. Is input and the field signal is a signal indicating an odd field, all the fetch period signals are output to the E signal as the write period signal, and the timing circuit 37
The write enable signal is output to the V-RAM 25 as a write enable signal, but in the even-numbered field, the capture period signal for every three times, which is the required number based on the address reference signal, is output to the E signal as the write period signal.

This write period signal is input to the dot address designating circuit 45 and the timing circuit 37, and the dot address designating circuit 45 outputs a value of 0 to 239 once for each write period signal. The dot address signal is output during output, and the timing circuit outputs V
-A write enable signal is output to the V-RAM 25 when a write period signal is input in synchronization with the timing when image data and address data are established in the RAM 25.

Then, the line addressing circuit 43
The line address signal output by the dot address signal and the dot address signal output by the dot address designating circuit 45 are latched by the latch circuit 47, the dot address value is associated with 0 to 7 bits, and the line address is associated with 8 bits to 16 bits. The value is output as an associated address signal.

Therefore, in the write control circuit 30, the capturing section determining circuit 33 limits 240 scanning lines out of the 252.5 scanning lines in each field in the video signal, and in the odd field, The image data based on the video signal in each of the 240 scanning lines is recorded in the V-RAM 25. At this time, the line address designating circuit 43 scans by the address reference signal output from the address reference signal output circuit 41. Since one extra line address value is added for every three lines, as shown in FIG. 3, every time three lines of video signals of 240 scanning lines in an odd field are recorded, one line is left blank. The image data is recorded by designating the address position of the V-RAM 25.

The image data is sequentially written in the V-RAM 25 by the dot addressing circuit 45 with 2 bytes of 16-bit 4-bit signal as one byte.
Image data for 480 dots per line is V-RAM 25
The value of the line address is incremented by 1 by being written in the 240-byte area. In this way, the video signals of 240 scanning lines in the odd field are stored in the V-RAM 25 as the image data of 320 lines in which the area for one line is blanked every four lines, and are fetched in the even field. After the number of scanning lines is limited to 240 by the section determining circuit 33, when the reading control circuit 35 recognizes an even field by the field signal from the field determination circuit 31, the address reference signal inputs the required number of capture period signals. Since the capturing period signal is output as the writing period signal every time the writing is performed, as shown in FIG.
In the even field, only the video signal of one scanning line is extracted for every three scanning lines and the image data is written in the V-RAM 25. At this time, the line address designating circuit 43 requires the address reference signal. Since a multiple of 4 which is the number plus one is output as the value of the line address, the image data is stored in the area of every 4 lines of the V-RAM 25.

Thus, 240 in the odd field
The video signals of the four scanning lines are stored in the V-RAM 25 as image data at a position of 320 lines in which one line is blank for every four lines which is the required number plus one, and among 240 scanning lines in an even field. The video signals of 80 scanning lines, one scanning line for every three lines, are stored as image data at a position of 80 lines, which is one line for every four lines with three lines left blank. , Fig. 5
As shown in FIG. 5, a video signal of one screen formed by 525 scanning lines in which each scanning line in the even field is arranged between the first scanning line in the odd field and 252.5 scanning lines in sequence. 1 based on the video signal of the 240 central scanning lines of the 252.5 lines in the odd field and the 240 scanning lines adjacent to the scanning lines of the odd field in the even field.
Image data for the screen can be formed.

Therefore, when displaying an image on the liquid crystal display plate, if a read control circuit (not shown) sequentially and sequentially increases the dot address and the line address to read the image data, the liquid crystal display plate reads 1 line per 4 lines.
It is possible to display an image of 320 lines by adding an image based on the scanning lines of the even field line by line. In this embodiment, since only a part of the video signal of the even field is added to the video signal of the odd field as described above, 25
In the configuration of the screen formed by more than zero lines, only a part of the video signal relating to one field is added, and when a moving image is recorded, even if the copy body is displaced due to the field. It is possible to reduce deterioration of image quality when the image is displayed on the liquid crystal display board.

In the above embodiment, the address reference signal output circuit 41 uses a counter circuit that outputs an extra value every time the fetch period signal is input three times.
Although 0 to 320 lines are formed, a counter circuit that outputs one extra value each time an input signal is input twice is used as the address reference signal output circuit 41, and 360 lines from 240 scanning lines are used. It can also be formed.

[0022]

According to the present invention, the odd field and the even field are discriminated on the basis of the vertical synchronization, and the count value of the line addressing circuit is sequentially increased on the basis of the horizontal synchronization signal, while the image data digitized from the video signal is obtained. In the random access memory for video, the image data based on the video signal in each scanning period is taken in by adding 1 to the count value of the line addressing circuit for each required number of horizontal synchronizing signals in one field. ,
In the other field, the method is a method of taking in only the image data of the scanning period for each required number of the horizontal synchronizing signals while using the count value of the required number plus 1 as the address signal, and thus the image data of one field is Since only a part of the image data of the field is added, the image data forming one high-quality frame can be obtained even when the image is slightly shifted between the fields.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit that controls writing of image data according to the present invention.

FIG. 2 is a block diagram showing an example of a write control circuit for implementing the present invention.

FIG. 3 is a schematic diagram of forming a line of image data from video signals of odd fields.

FIG. 4 is a schematic diagram of forming a line of image data from a video signal of an even field.

FIG. 5 is a schematic diagram showing a scanning line arrangement of frames and a line arrangement of image data.

[Explanation of symbols]

11 Video Signal Input Terminal 13 Sync Separation Circuit 15 Analog-to-Digital Converter 17 Data Adjustment Circuit 19 Horizontal Sync Oscillator 25 Video Random Access Memory 30 Write Control Circuit 31 Field Judgment Circuit 33 Capture Section Determining Circuit 35 Read Control Circuit 37 Timing Circuit 41 Address Reference signal output circuit 43 Line address designation circuit 45 Dot address designation circuit 47 Latch circuit

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location G09G 5/36 9377-5H G09G 5/36 H04N 7/01 H04N 7/01 G

Claims (1)

(57) [Claims] 1. When storing image data obtained by digitizing a video signal of one frame in a predetermined area of a random access memory for video based on the value of an address signal output from a line address designating circuit and a dot address designating circuit. An odd field and an even field are discriminated based on the vertical synchronizing signal, and in one field, an address signal whose value is sequentially incremented by 1 based on the horizontal synchronizing signal is output as a count value from the line addressing circuit, and , An address signal having a value obtained by adding 1 as the count value of the line addressing circuit for each required number of horizontal synchronizing signals is output, and in the other field, a value obtained by sequentially adding the required number plus 1 is added to the horizontal synchronizing signal. Output from the line addressing circuit for each required number. When storing the image data based on the video signal in each scanning period, by adding 1 to the count value from the line address designating circuit, the line area for which the image data is not captured is added for each line area of the required number plus 1. It is formed in a random access memory, and in the other field, image data based on a video signal for each required number of scanning lines of each scanning line is stored for each required number of video random access memory plus one line area. And video signal acquisition method.