JP3248877B2 - Video printer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera and a video camera.
Related to a device for hard-copying the output of a TR playback image, etc.
In particular, reduce the input image and store it in many memories, or
Video printer suitable for printing by reducing and dividing the image
About. 2. Description of the Related Art A conventional apparatus is disclosed in Japanese Patent Application Laid-Open No. 56-64884.
As described in Japanese Patent Publication No.
To obtain one print with the same image array
Had become. [0003] The above prior art is a memo.
To reduce the size of the deleted image and print it simultaneously in multiple divisions
Prints small images without regard to points
If you want to obtain many types of
After taking a small image, I have to print multiple sheets.
There was a problem in strike and time. In addition, VTR and TV release
This is not possible if you want to print the image
there were. An object of the present invention is to print a plurality of reduced images.
Image frame at the boundary between reduced images.
And there. [0005] In order to achieve the above object,
According to the present invention, there is provided a memory means for storing input image data.
And the image data read from the memory means as an image.
Output means for outputting the data read from the memory means.
A printer that prints image data and outputs multiple reduced images
In a video printer having a printing means,
An image frame signal generating means for attaching an image frame to the boundary is provided. Further, according to the present invention, input image data is stored.
Memory means for reading, and image data read from the memory means.
Output means for outputting data as an image, and the memory means
Print the image data read from the
Video printer with printing means for output
The memory means stores the input image data reduced to 1 / N.
Buffer memory to hold data and a buffer to control this
Memory control means, and the data stored in the buffer memory.
Field that holds reduced image data at specified position
Memory and field memory control means for controlling the memory
And the reduced image held in the buffer memory.
A frame area detecting means for detecting an image frame area between images;
Signal generating means, which is detected by the frame area detecting means.
Switch the output of the picture frame signal generating means into the
It was to so. Further, the present invention relates to the above-mentioned video printer.
Switch means for interrupting the output of the picture frame signal generating means
It was made to have. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video which is a premise of the present invention will be described.
The configuration of the printer will be described with reference to FIGS. In FIG.
Here, 1 is a magnetic recording / reproducing device, a video camera, or
Signal source such as TV broadcast receiver, 2 for analog signal processing
Decoding processing means for applying 3
Memory means 4, encoding processing means 5, monitor 5, 6
Is a print for hard copy of the memory information in the memory unit 3.
Means 7 is a system controller (hereinafter abbreviated as syscon).
Do). Next, the operation will be described. This system is
In mode 1, the video signal from signal source 1 is sequentially reduced
And stored in the memory means 3 in the form of a multi.
After confirming, the printing is performed by the printing means 6 (see FIG.
2). Also, the present system can be used as a second mode, for example.
If the signal source 1 is a magnetic recording player such as a video floppy or VTR
In the case of a raw device, the signal source 1 and the system
The contents of the video floppy (for example, a 50-field image
Area) is sequentially reduced, and 25 screens / field are stored in the memory means 3.
Print after storing as multi-screen memory
(FIG. 3). In addition, the present system provides a third mode.
Standard that does not reduce the video signal from signal source 1
After holding in the memory means 3 with the size of
In the means 6, the multi-segmented multi-image shown in FIG.
Compress and place the same image on one print on N screens)
It is to lint. [0010] The configuration of a video printer as a premise of the present invention
An example is shown in FIG. This figure realizes the print image of FIG.
It is. In FIG. 5, reference numeral 301 denotes a buffer memory;
02 is field memory control, 303 is buffer memory control
Means 304 is a field memory control means. Ma
In addition, the buffer memory control means 303 includes a W / R control means.
331, vertical address means 332, horizontal address means 3
33, 2N frequency divider 334, 2N frequency divider 335, clock
Field memory consisting of switches 336 and 337
The control means 304 includes a W / R control means 341 and a W gate
Step 342, coincidence detecting means 343, 344, area address
Means 345, vertical address means 346, horizontal address
Means 347. In the above, the area address means 345
Are the reduced areas in FIGS. 2 and 3 (A, B,
C, D...) Are supplied. Ma
The buffer memory 301 is used for simplifying the description.
It is assumed that there are four buffer memories. Next, the operation will be described. First, the decoding process
As shown in FIG.
The tall images are sequentially input to the memory means 3. This human power
The digital image is decimated vertically / horizontally, and
Only the data constituting the reduced image is stored in the buffer memory 30.
Written to 1. That is, the image “A” in FIG.
Is reduced to buffer memory A1 / B1 during one field period.
Written small. In the next field period (image "B" in FIG. 2)
During the period, the contents of the buffer memories A1 / B1 are continuous.
To the other buffer memo
The image “B” is reduced and written in the area A2 / B2.
You. Thereafter, the images "C", "D" ... are also sequentially reduced and buffered.
Written to and read from memories A1 / B1 and A2 / B2
It is. Now, here, the input image "A" is
When writing to the memory A1 / B1, horizontal scanning (some
Buffer memory A1 and B
Write to 1 alternately. At the time of subsequent reading, two buffer memos
A1 and B1 are simultaneously read out, and the next field memo is read.
In the writing area of the A / B 302 (reduced section in FIG. 2)
Write simultaneously at the same timing. Hereinafter, A, B, C, D,...
... written as 1, 2, 3, ..., continuous with P or 25
Completed writing of reduced image to field memory 302
I do. Thereafter, the field memory 302 is continuously stored.
And displays the image of FIG. 2 on a monitor (not shown).
And the same as the monitor image by the printing means 6
Print the print. Next, the buffer memory control means 303 and the
The detailed operation of the field memory control means 304 will be described.
First, the buffer memory control means 303
Only the necessary data is stored in the buffer memory 301 as shown in FIG.
Take in. First, in the horizontal direction, the input data transfer cycle
(Same as the input clock CLK and T _CLK To)
The address change of the horizontal address means 333 is 2N ·
T _CLK It is. In other words, horizontal addition is performed by the 2N frequency divider 335.
The clock cycle of the addressing means 333 is 2N times. FIG. 6 shows a state of 16 divisions where N = 2.
You. Therefore, the same address is, for example, as shown in FIG.
Four consecutive data 1-1, 1-2, 1-3, 1-4 shown in
Data is written, but finally written last
4 is held. Then go to the next address
Represents 1-8 of the following four data (1-5 to 1-8)
Is held, and as a result, in one horizontal scan, 5
Of the 12 data, 1/4 of the 128 data
Is written to the buffer memory A1 (the first water
During the horizontal scanning period, data is written to the A1 memory of the buffer memory 301.
Be included. ). After that, the next
In the horizontal scanning period to be inserted, 128 data
The data is written to the field memory B1. afterwards,
Data is written alternately in field memories A1 / B1
It is. Next, the operation of the vertical address means 332 will be described.
However, at the time of writing, 2N
The rotated horizontal synchronizing signal HD is input (the explanation of this embodiment).
In the description, N = 2 as described above). Therefore,
The vertical address of the memory 301 is one in four horizontal cycles.
Will be moved to each buffer memory shown in FIG.
The data of the assigned row is written. Therefore,
The horizontal period data of the first second row is stored in the buffer memory A1.
The horizontal period data two rows later is held in the buffer memory.
It is held by the memory B1 and thereafter, this operation is repeated to
128 rows of data from the last period (256 rows of data)
Each time it is held in the buffer memory A1 / B1. This result
As a result, the buffer memory 301 finally stores the horizontal data.
Only the 4nth (n = 1 to 128) data
And in the vertical direction, in the buffer memory A1
(4m-2) line, 4m line in buffer memory B1
Only data (m = 1 to 64) is held. As a result,
The data shown in FIG. 6B is stored in the buffer memories A1 / B1.
Is held. When writing to the buffer memory 301
A / B switching is performed by the W / R control unit 331.
Is done. Next, reading of the buffer memory 301 will be described.
In some cases, the vertical address means 332 and the horizontal address
As the clock of the means 333, HD and CLK are directly input.
It is. Therefore, in the vertical direction, the same
One address appears four times periodically, and one in the horizontal direction.
The same address appears periodically four times in the horizontal period. Toes
Output from the buffer memory 301 via a monitor.
If you look at it, it is exactly reproduced in 16 divided state on the right side of FIG.
I have. In other words, each of the reduced 16 areas has
In response, the same image appears 16 times. Such an image is
It is supplied to the column field memory 302. Next, the field memory control means 30
Operation 4 will be described. The vertical /
The horizontal address is provided by vertical address means 346 and
And the horizontal address means 347. These ads
Reset means 346 and 347 reset VD and HD signals
R, HD, CLK signals as clock CK,
Vertical address means 33 in buffer memory control means 303
2 and the read state of the horizontal address means 333
Generate addresses as well. Therefore, the buffer memo
The reduced area read from the memory 301 and the field menu
The reduction area in the memory 302 is completely timing
Matches. Therefore, the area address means 345
As an output, the compression to be written to the field memory 302
W / R control means by specifying the position of the small area
341 is written only in that area (for example, area A in FIG. 2).
Outputs a write command. At this time,
(M-th line, n-th line) in the area 2
Then, (m, n) is supplied to the area address means 345.
You. At this time, the output of the area address means 345 is
Both in the vertical and horizontal directions (in this embodiment)
Are output, and the match detecting means 343 and 344 output each address.
It is compared with the upper 2 bits (MSB side) of the dress. Therefore, one area data (m,
n), only for one reduced area period,
The stages 343 and 344 output the coincidence signal and the W gate means 3
At 42, the W / R controller 3 controls only the common period of both coincidence signals.
A match signal is output to 41. At this time, the reduced area (Fig.
2A to P) writing order or random area finger
Can be set arbitrarily according to the design of the system controller 7.
Can be. Also, from the system controller 7 to the W gate means 342
By sending a signal directly, the same reduced image can be
Data can be written to the six-screen field memory 302. Further, the area number is cut for each field.
In other words, the continuous field image shown in FIG.
16-segment continuous memory is possible, every few fields
Or switch the area number by manual input
Allows intermittent or intermittent field memory
Noh. In the above, four buffer memories A1
/ B1, A2 / B2 W / R operation and field memory 3
The W / R operation of No. 02 is shown in FIG. Fieldme
By writing data to memory A / B 302 at the same time,
The next field write is enabled and the field memory 3
02, read the field memo for each field.
By switching between A / B and outputting, normal monitor
Reproduce the interlaced signal that can be projected
I have. FIGS. 7 (5) and (6) show field memories.
It looks like the reduced area number written to 302 changes sequentially
This is schematically shown by the phase change of the write pulse. In FIG. 5, the buffer memory A1
The relationship between / B1 and the buffer memory A2 / B2 is as follows:
In the writing state, W / R is always opposite. I
Therefore, the buffer memories A1 / B1, A2 / B2, etc.
A dedicated vertical address means 332 and a horizontal address
333 is necessary, but it is easy to understand.
Each wiring is omitted. In the description of FIGS. 5 to 7, N = 2.
Has been described, but N may be another integer.
Good. For example, N = 1 is divided into four, N = 3 into 36, N
= 4 and 64 divisions. In the video printer described above,
The screens of adjacent reduced images are in contact with each other. like this
When cutting multiple images, the
If you do not cut correctly, the background of the next image will enter
There is a risk. This embodiment eliminates such inconveniences.
It relates to a video printer that can be eliminated. An example of an odd division print as shown in FIG.
An example is shown in FIG. In the same figure, it has the same function as FIG.
Those having the same numbers are described. In FIG. 8, 305 is
Buffer memory control means, 306 is frame data generation means,
307 is a data switch. Buffer memory control hand
Step 305 is included in the buffer memory control means 304 of FIG.
Vertical shifting means 35 in addition to
1, horizontal shift means 352, final address detection means 35
3, 354, frame area detecting means 355, OR gate 35
6,357, and address switches 358, 359.
Is done. Next, the operation will be described. In the description, FIG.
Take 25 screens as an example. First, the buffer memory 30
Image writing to 1 is 1/4 as described in FIG.
Data is reduced and one field of data is captured.
You. Also, as shown in FIGS. 7 (3) and (4), the buffer memory A
During the write field period to 1 / B1, the buffer memory
The memory A2 / B2 is in the readout period and the next field period
Now we are in the opposite situation. Add buffer memory 301
Address via address switches 358 and 359.
Controlled by the direct addressing means 332 and the horizontal addressing means 333
Is controlled. Here, the vertical address means 332 performs a write operation.
(Write: W) The vertical address means 332a and the read (R
ead: R) is composed of vertical address means 332b,
The address switches 358a and 358b conflict with each other.
Output of the vertical address means 332 to be selected
Are supplied to the memory A1 / B1 and A2 / B2. As well
The horizontal addressing means 333 is also used for the W horizontal addressing means 3.
33a and R horizontal address means 333b.
Buffer memory means 3 as well as vertical address means 332
01 to the address. First, the operation of the W horizontal address means 333a
Will be described with reference to FIG. H from decode processing means 2
2N frequency divider 335 and horizontal shift means 3
52 is reset R. At this time, the horizontal shift means 3
The output of 52 becomes, for example, "H" and the W horizontal address
The stage 333a is reset R. After that, the 2N frequency divider 33
5 is a clock signal CLK (in this description, N = 2
), Divides the frequency by 4 and shifts to the next horizontal shift means 352 and W horizontal
The clock input terminal CK of the address means 333a is divided by 4 into C
Supply LK. Thereafter, the horizontal shift means 352 is
When a constant (eg, 14 shots) CLK divided by 4 is counted,
The output is inverted to “L”, and the output of the W horizontal address
Release reset. As a result, the W horizontal addressing means 3
33a can be counted, and is activated every time the divide-by-4 CLK arrives.
Update the dress value. This address value is 12
8 and the subsequent counting operation becomes meaningless. did
Therefore, the buffer memories A / B are shown in FIG.
In the horizontal direction, only the data after the 15th line is
Be held. 50 × 100 held in buffer memory
Pieces of data are stored in the R horizontal address
At the same time as being repeatedly read by the stage 333b, the next stage
To the data switch 307. here,
R horizontal address means 333 is reset by HD signal
The clock CLK is started counting immediately after that.
When the count reaches the final count value (for example, 100), the final
The dress detection means 354 outputs the last address as the last address.
The count value is detected, and a reset pulse is supplied to the OR gate 357.
Output. This resets the R horizontal address means again.
Counting starts from address 0.
It is repeated until HD arrives. There are over 500 CLKs in one horizontal period.
Therefore, for example, the data (8-
15) to (8-114) are repeatedly read 5 times or more
Will be extruded. Therefore, for each vertical address
On the other hand, the same data group in the horizontal direction (for example, 8-15
To 8-114) are read five or more times. Where the final
Address 100 is one of the integers of 512/5 or less
Selected and not necessarily limited to this
No. Next, the operation of the vertical address means 332 will be described.
I will tell. The horizontal operation of the horizontal address means 333 is
What is replaced in the vertical direction is vertical address means 332.
You. First, the operation of the W vertical address means 332a will be described.
You. 2N frequency division by VD signal from decode processing means 2
The reset unit 334 and the vertical shift unit 351 are reset.
At this time, the output of the vertical shift means 351 is, for example,
Becomes "H" and resets the W vertical address means 332a to R
I do. After that, the 2N frequency divider 334 converts the HD signal into the (actual
(N = 2 in the embodiment)
Next stage vertical shift means 351 and W vertical address means 33
2a to the clock terminal CK. Vertical shift means 3
Reference numeral 51 counts a predetermined number (for example, 7) of divided-by-4 HD signals.
Then, the output is inverted to "L" and the W address means 33
Release the reset of 2a. Then, the W vertical address
Stage 332a begins counting the divide-by-4 HD signal, and
Buffer via the address switch 358
The data is supplied to the memory 301. Therefore, the buffer memory
A1 and B1 contain data from the eighth line onward, as shown in FIG.
Data is retained. At this time, write data from the 58th line onwards.
The inclusion is optional. Next, the R vertical address means 332b
The operation will be described. Via OR gate 356 by VD signal
Then, the R vertical address means 332b is reset,
Immediately after that, the HD signals are counted. The count value is the final count value
(For example, 50), the final address detecting means 3
53 detects the final count value as the final address,
A reset pulse is output to OR gate 356. to this
Therefore, the R vertical address means 332b is reset again.
Then, counting starts from address 0 again. This behavior is
This is repeated until the next VD signal arrives. VD circumference
During the period, there are approximately 260 HD signals, and
(B) For example, data for 50 lines from the 8th line to the 57th line
Data is repeatedly read out five times in the vertical direction. As described above, the vertical addressing means 332 and the water
FIG. 9B shows the read control of the flat address means 333.
Screen is vertical / horizontal (vertical / horizontal when viewed on a monitor)
A total of 25 screens are read for each of the five screens. Accordingly
The field memory 302 and the field memo of FIG.
If the remote control means 304 is used, the reduced image
Screen memory is possible, and the same image can be simultaneously stored in 25 screens
You can also. As described above, the buffer memory 301
The reduced image read out is sent to the data switch 307.
Is framed. That is, the frame area detecting means 3
55, the data switch 307 switches the frame data.
Frame data from the data generator 306, and
To the memory 302. Here, as frame data
Is defined as white, black, or any other hue. Now, the operation of the frame area detecting means 355 will be described.
I will tell. The frame area detecting means 355 has an R vertical address
R vertical address and R horizontal address from means 322b.
The R horizontal address from the means 333b is input.
You. In the frame area detecting means 355, a frame is calculated from each R address.
Detects the address to be set as the area and uses it as a frame area signal
The data is supplied to the data switch. As the frame area,
For example, two lines at the left and right ends shown in FIG.
15 and 16 and 113 and 114 lines)
For example, two rows at the end (horizontal data 8, 9, and 56, 5
7)) addresses are detected. This frame detection signal is reduced
It occurs in the upper, lower, left and right areas for one image, and these are
It is output for all 25 screens. Next, the buffer memory control procedure in FIG.
Another embodiment of the stage 305 is shown in FIG. Smell
8 having the same functions as those in FIG.
is there. In FIG. 10, the R vertical address means 322b and the R horizontal
The address means 333b is a preset PS type.
Vertical shift means 351 and horizontal shift means in FIG.
352 is deleted. Vertical address means 332
The operation other than the horizontal addressing means 333 and FIG.
You. First, the operation of the horizontal address means 333 will be described.
I will tell. The W horizontal addressing means 333a uses the HD signal
Immediately after the reset, counting of the frequency-divided CLK is started. I
Therefore, the buffer memory 301 stores the water shown in FIG.
All square data is written. On the other hand, when reading
Means that the R horizontal address means 333b is controlled by the HD signal.
Preset PS to a fixed value (for example, 15), and then C
The address value is updated by LK. Final count value (example
For example, when the address value advances to 114), as in FIG.
Preset pulse is output from end address detection means 354
And the R horizontal address means 3 through the OR gate 357.
33b is reset again. Thereafter, the horizontal address is repeated in the same manner.
Output. Therefore, from the buffer memory 301
Indicates that the reduced image data of FIG. 9B is repeated as in FIG.
Output. On the other hand, in the vertical address means 332,
The horizontal direction of the horizontal address means 333 is set in the vertical direction.
It is equal to the changed state. That is, the W vertical address means 33
2a is reset by the VD signal, and the divided-by-4 HD signal is
Count. Therefore, the buffer memory 301 has
All data is written from the first row in the horizontal direction shown in FIG. At the time of reading, R vertical address means 332
b is preset to a predetermined value (for example, 8) by the VD signal.
S is performed, and then the frequency-divided HD signal is counted. Final address
The data detecting means 353 is provided at the end of the R vertical addressing means 332b.
When the end address (for example, 57) is detected, the preset
Is output, and the R vertical signal is output again through the OR gate 356.
The dress means 332b is preset. Hereafter this behavior
repeat. Therefore, the reduced image in FIG.
Read continuously. In the above description of FIGS. 8 to 10,
Assuming that N = 2, the size is reduced to 1/4 in the vertical and horizontal directions, and 5 ×
5 = 25 reduced screen writing has been described.
It is not limited to. For example, in the case of 3 × 3 = 9 screens
Is reduced to 1/2 in the vertical and horizontal directions assuming N = 1 (25
6 × 256), and store it in the two buffer memories 301.
Write (256 × 128). When reading, the reduced image
(170 × 85) part of the image (256 × 128)
Read repeatedly. In the case of 7 × 7 = 49 screens,
Assuming N = 3, compression (84 × 84)
The image (84 × 42) is written into the buffer memory 301.
The (72 × 36) portion is repeatedly read. As described above, an odd number (2N +
When storing the reduced image of 1), reduce it to 1 / 2N
After that, the data is written into the buffer memory 301, and 5
12 / (2N + 1) or less
The image is repeatedly read and stored in the field memory 302.
Just write it. According to the present invention, an image frame is provided around a reduced image.
Strict alignment when cutting the reduced image
Even if it is not done densely, the background of the adjacent screen in the reduced screen
I can't get in.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a video printer which is a premise of the present invention. FIG. 2 is a conceptual diagram for explaining the operation of the video printer. FIG. 3 is a conceptual diagram for explaining the operation of the video printer. FIG. 4 is a conceptual diagram for explaining the operation of the video printer. FIG. 5 is a block diagram showing the configuration of a video printer on which the present invention is based in more detail. FIG. 6 is a conceptual diagram for explaining the operation of the video printer of the present invention. FIG. 7 is a main part waveform diagram for explaining the operation of the video printer of the present invention. FIG. 8 is a block diagram illustrating a configuration of a video printer according to the present invention. FIG. 9 is a conceptual diagram for explaining the operation of the video printer of the present invention. FIG. 10 is a block diagram showing the configuration of still another embodiment of the video printer of the present invention. [Description of Signs] 1 Signal source 2 Decoding processing means 3 Memory means 4 Encoding processing means 5 Monitor 6 Printing means 7 System controller 301 Buffer memory 302 Field memory 303 Buffer memory control means 304 Field memory control means 305 Buffer memory control means 306 Data generation means 355 Frame area detection means

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tetsu Yoshida 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) References JP-A-62-147883 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/76-5/956 B41J 2/00

Claims (1)

(57) [Claims] Memory means for storing input image data, output means for outputting the image data read from the memory means as an image, and printing means for printing the image data read from the memory means and outputting a plurality of reduced images In the video printer, the memory unit includes an image reduction unit that thins out input image data and stores the image data in a memory unit, and an image frame signal generation unit that adds an image frame to a boundary between reduced images stored in the memory unit. A video printer. 2. Memory means for storing input image data, output means for outputting the image data read from the memory means as an image, and printing means for printing the image data read from the memory means and outputting a plurality of reduced images In the video printer, the memory means includes an image reducing means for reducing image data to 1 / N, a memory unit for sequentially holding reduced image data from the image reducing means at a predetermined position, and a memory for controlling the memory unit. Control means, a frame area detecting means for selecting or detecting an image frame area between the reduced images, and an image frame signal generating means, wherein the image frame signal is generated in the area of the reduced image designated by the frame area detecting means. A video printer, wherein the output of the means is switched and inserted. 3. 3. The video printer according to claim 1, further comprising switch means for interrupting the output of said image frame signal generating means.