JPH11284931A - Driving device for display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the disturbance of a display picture on a screen in selecting a channel by reading picture element data written in synchronizing with a self-running clock signal and supplying it to a display driving means. SOLUTION: A memory control circuit 9 alternately sets the write mode and the reading mode of respective memories 51 and 52 at every two periods of a self-running clock 2. The memory 51 becomes the write mode when it is connected to a data processing circuit 4 through the contact point '1' of a switch SW1. The memory 52 becomes the read mode when it is connected to a column electrode driver 6 through the contact point '0' of a switch SW2. The memory 51 becomes the read mode when it is connected to the column electrode driver 6 through the contact point '1' of the switch SW2, and the memory 52 becomes the write mode when it is connected to the data processing circuit 4 through the contact point '0', of the switch SW1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving apparatus for a display panel such as a plasma display panel (PDP).

[0002]

2. Description of the Related Art In a display device of a matrix display system such as a PDP, halftone display is performed by using a subfield method. Therefore, two field memories are used as a display memory, and pixel data for one field is stored in one of the display memories. While reading from one memory and performing display driving, further pixel data is written to the other memory, and after reading of pixel data from one memory is completed, pixel data is read from the other memory and display driving is performed. The operation of writing further next pixel data to the memory of (i) is repeated. That is, the read-side memory and the write-side memory are switched for each field.

[0003]

Problems to be Solved by the Invention
As disclosed in Japanese Patent No. 48834, a channel guide function for automatically changing channels and displaying images of a plurality of broadcasting stations on one screen to facilitate channel selection has been introduced into TV receivers and the like. I have. By the way, in a plasma display device of a matrix display system, various pulses necessary for light emission display are generated based on a synchronization signal of a video signal, and image display driving is performed. Therefore, when a plurality of images are displayed on one screen by switching a plurality of channels one after another in a short time to select a channel such as a channel guide function, if the generation timing of the synchronization signal varies for each channel, It is necessary to match the generation timing of various pulses for image display with the synchronization signal of the video signal within a short time. Therefore, if the generation timing of such various pulses is slightly deviated from the synchronization signal,
There has been a problem that the image quality of the image displayed on the screen is impaired.

[0004] It is an object of the present invention to provide a display panel driving apparatus in which a displayed image on a screen is not disturbed even when a channel is selected in order to solve the above-mentioned problem.

[0005]

According to the present invention, there is provided a display panel driving apparatus for receiving a television broadcast wave, generating a video signal, and changing a receiving station in accordance with a command. A synchronizing signal separating circuit for detecting a synchronizing signal from a video signal, and an A / A for sampling the video signal and obtaining pixel data corresponding to each pixel
A D converter, first and second memories each having a capacity for storing at least one field of pixel data, a free running clock signal generating means for generating a free running clock signal, and one field of pixel data. Control means for alternately writing the first and second memories and controlling the first and second so as to alternately read the written pixel data for one field from the first and second memories;
Display driving means for driving a display panel based on pixel data read from the first and second memories, wherein the control means controls the writing and reading of each of the memories by generating the free-running clock signal. Switching is performed in synchronism with the self-running clock signal at intervals of time equal to or longer than twice the period, and pixel data for one field is changed according to the synchronization signal detected immediately after the memory is switched from reading to writing. Writing to a memory, the control means comprising:
The pixel data written in synchronization with the free-running clock signal is read and supplied to the display driving means.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a driving apparatus for a plasma display panel according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of a driving device of a plasma display panel according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an antenna for receiving a radio signal of a television broadcast, and a television signal receiving circuit 2 demodulates a signal of a designated broadcasting station from the radio signal received by the antenna 1 to generate a video signal. Output as A /
The D converter 3 obtains pixel data D for each pixel by sampling a video signal input from the receiving circuit 2 and performing analog-to-digital conversion to a digital video signal. The image data processing circuit 4 performs image processing on pixel data input from the A / D converter. For example, the pseudo intermediate display is realized by reducing the number of bits of the pixel data, and a false contour is compensated. And a false contour processing circuit for generating pixel data. A switch SW1 is connected to the image data processing circuit 4, and the switch SW1 selectively connects the image data processing circuit 4 to the memories 51 and 52.

The memories 51 and 52 have a storage capacity capable of storing pixel data for at least one field. The column electrode driver 6 is connected to the memory 5 via the switch SW2.
1 and 52, and separates pixel data for one field read from the memories 51 and 52 into bits, and outputs voltage values corresponding to the logical values “1” and “0” of the bits, respectively. The generated pixel data pulse is applied to a column electrode of a plasma display panel (PDP) 7.

The synchronizing signal separating circuit 8 detects a synchronizing signal from the video signal output from the television signal receiving circuit 2. The memory control circuit 9 includes the memories 51 and 5
2 to control writing and reading of pixel data. The operation means 10 is for setting / releasing a multi-screen mode divided into a plurality of sections. The free-running clock generation circuit 11 generates a free-running clock signal having the same frequency as the video signal synchronization signal and having no correlation with the generation timing of the video signal synchronization signal.

The control circuit 12 includes a memory control circuit 9, and includes a receiving circuit 2, an A / D converter 3, an image data processing circuit 4, switches SW1 and SW2, a synchronizing signal separating circuit 8, an operating means. 10 and a free-running clock generation circuit 11, and the reception circuit 2, the A / D converter 3, and the image data processing circuit 4 synchronize the video signal detected by the synchronization signal separation circuit 8. A clock signal for executing data processing based on the signal is supplied. The control circuit 12
Controls the switches SW1 and SW2 and the memory control circuit 9 with the free-running clock signal input from the free-running clock signal generation circuit 11, and also sends an image to the row electrode driver 13 based on the input free-running clock signal. A reset timing signal, a scan timing signal, a sustain timing signal, and an erase timing signal required for display are generated and supplied.

The row electrode driver 13 responds to these various timing signals by a reset pulse for initializing the residual charge amount, a scan pulse for writing pixel data, and a sustain pulse for maintaining a discharge light emitting state. Then, an erase pulse for stopping discharge light emission is generated, and these pulses are applied to the row electrode pair of the PDP 7. At this time, the scanning pulse is applied to the row electrode pairs by sequential scanning.

In the PDP 7, when a scanning pulse is applied from the row electrode driver 13 while a pixel data pulse is applied from the column electrode driver 6, charges corresponding to the applied pixel data pulse are accumulated in the PDP 7. You. At this time, for example, light emission occurs at the intersection of the column electrode to which the pixel data pulse corresponding to the logic “1” is applied and the row electrode pair to which the scanning pulse is applied. The intersection is PD
It corresponds to each pixel on the screen of P7. Thereafter, when the sustain pulse is applied from the row electrode driver 13, the above-described light emitting state is maintained for a time corresponding to the number of pulses to which the sustain pulse is applied.

Next, an embodiment of the operation of the driving device will be described with reference to FIG. FIG. 2 shows the memories 51 and 52.
FIG. 4 is a diagram showing writing and reading to and data of pixels displayed on a PDP 7; The control circuit 12 supplies the free-running clock signal C input from the free-running clock signal generation circuit 11 to the switches SW1 and SW2 and the memory control circuit 9, and each of the switches SW1 and SW2 outputs, for example, The contact “0” and the contact “1” are alternately switched every two cycles. That is, when the data processing circuit 4 is connected to the memory 51 via the contact "1" of the switch SW1, the memory 52 is connected to the column electrode driver 6 via the contact "0" of the switch SW2. When the circuit 4 is connected to the memory 52 via the contact "0" of the switch SW1, the memory 51 is connected to the column electrode driver 6 via the contact "1" of the switch SW2.

As described above, the memory control circuit 9 alternately sets the write mode and the read mode of each of the memories 51 and 52 every two cycles of the free-running clock, and the memory 51 sets the contact "1" of the switch SW1. ”Is connected to the data processing circuit 4, the writing mode is set. On the other hand, when the memory 52 is connected to the column electrode driver 6 via the contact“ 0 ”of the switch SW2, the reading mode is set. Conversely, when the memory 51 is connected to the column electrode driver 6 via the contact “1” of the switch SW2, the memory 51 enters the read mode, and the memory 52 stores the data processing circuit 4 via the contact “0” of the switch SW1. Is connected to the write mode. FIG. 2 shows the connection state of the switches SW1 and SW2 and the write and read modes of the memories 51 and 52.

The operation of writing data to each of the memories 51 and 52 when the mode is set as described above will be described with reference to FIG. The video signal sampled by the A / D converter 3 becomes pixel data (a) for each pixel,
The data is sent to the image data processing circuit 4 and subjected to false contour processing and the like, and is written into the memories 51 and 52. Further, the synchronizing signal separation circuit 8 detects a synchronizing signal (b) for each field from the video signal sampled by the A / D converter 3.

On the other hand, the control circuit 12 supplies the free-running clock signal C (FIG. 2C) to each of the switches SW1 and SW2 and the memory control circuit 9. Therefore, at time t _{0, the} image data processing circuit 4 stores
When connected becomes write mode 1, the memory control circuit 9, a write enable signal in response to the synchronization signals S ₁ of the video signal detected immediately after issuing the free-running clock C1 (f)
The so emitted toward the memory 51, the synchronization signals S ₁ and the corresponding one field of pixel data a ₂ of the video signal detected in the memory 51 is to be written as shown in FIG. 2 (i).

The memory control circuit 9 controls the address of the memory 51 in accordance with the free-running clock C1 and sends a timing for sampling the writing of the input pixel data to the data processing circuit 4 so as to display a television screen, for example. In the case of dividing into a plurality of pixels, pixel data input to a small screen can be written as a reduced image. The memory 51
Is in the pixel data write mode, the memory 52 is in the pixel data read mode.

Next, reading from the memory 51 will be described. When the free-running clock C3 is issued at time t _1,
The image data processing circuit 4 is connected to the memory 52, the memory 51 is connected to the column electrode driver 6, and the memory 51 enters a reading mode. In the read mode of the memory 51,
The memory control circuit 9 outputs the read address to the memory 51. Data read from the memory 51 is the pixel data a ₂ for one field written in the immediately preceding write mode, is supplied to the column electrode driver 6 as sequentially read out the pixel drive data in accordance with the running clock C3 You. In the present embodiment, since there are two occurrences of free-running clock C3, C4 during the read mode, the pixel data a ₂ during the read mode is read out twice successively.

[0018] Incidentally, when the memory 51 is in the read mode of the pixel data, the memory 52 is in a write mode of next pixel data, and writes the pixel data a ₄ in the memory 52 in the same manner as the memory 51. Thus, 2
The two memories alternately enter a write mode and a read mode in response to a free-running clock signal, and alternately write and read pixel data for one field to and from the two memories 51 and 52 until the channel is changed. Done.

Next, when the receiving channel is switched from channel A to channel B, the phase of the synchronizing signal of the video signal with respect to the free-running clock signal changes.
Writing and reading of pixel data to and from the pixels 1 and 52 are continuously performed according to the free-running clock signal C without interruption. That is, even at the moment when the channel is switched, the free-running clock as a reference pulse for writing and reading the pixel data is supplied at regular intervals, and the pixel data is written and read. Disturbance is prevented.

In the above embodiment, the switch SW
The switching between SW1 and SW2 is performed every two cycles of the free-running clock, but may be performed every three cycles of the free-running clock. Alternatively, in two consecutive periods of the free-running clock, the memory 51
Is set to the write mode and the memory 52 is set to the read mode, and the switches SW1 and SW2 can be switched so that the memory 51 is set to the read mode and the memory 52 is set to the write mode in the next three consecutive cycles.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a display panel driving device according to the present invention.

FIG. 2 is a waveform diagram illustrating an operation of the driving device of FIG.

[Explanation of symbols]

 2 Television signal receiving circuit 3 A / D converter 6 Display driving means 7 Display panel 8 Synchronous signal separating circuit 11 Self-running clock signal generating means 12 Control means 51, 52 Memory

Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI G09G 3/28 G09G 3/28 J H04N 5/66 101 H04N 5/66 101B // H04N 5/44 5/44 H

Claims (2)

[Claims] 1. A television signal receiving circuit that receives a television broadcast wave to generate a video signal and that can change a receiving station according to a command, a synchronization signal separation circuit that detects a synchronization signal from the video signal, An A / D converter for sampling the video signal to obtain pixel data corresponding to each pixel; first and second memories each having a capacity to store at least one field of pixel data; Self-running clock signal generating means for generating pixel data for one field in the first and second memories alternately, and writing the pixel data for one field in the first and second memories Control means for controlling the first and second data so as to read them alternately from the memory; and a display based on the pixel data read from the first and second memories. Display driving means for driving a ray panel, wherein the control means controls the writing and reading of each of the memories at every time that is twice or more the generation cycle of the free-running clock signal. In response to the synchronization signal detected immediately after the memory is switched from read to write, and writes pixel data for one field to the memory. The control means synchronizes with the self-running clock signal. A driving device for a display panel, which reads out the pixel data written by writing and supplies the read pixel data to the display driving means. 2. The display panel driving device according to claim 1, wherein the free-running clock signal has the same cycle as a synchronization signal of the video signal.