KR100266326B1 - An error protection apparatus of data process for pdp television - Google Patents

Abstract

PURPOSE: An error protecting apparatus of digital data process for a PDP(Plasma Display Panel) TV is provided to prevent error in data processing by delaying reading time when the reading and writing are initiated at a memory after an initial stabilization time. CONSTITUTION: A memory(3) receives a digital data and realigns it suitable for gradation for the reading and writing to be reiterated by a data selection signal. A data interface(4) outputs the digital data input to the memory(3) in a data stream format for an effective PDP gradation processing. A controller(5) transfers a reading initiation signal and a writing initiation signal to the memory(3). A counter(100) stops the control signal transfer to the controller(5) for a determined initial time and counts the stopping time. When the counting of the stopping time is completed, a high pulse is input to the timing controller(5).

Description

Malfunction prevention device for PDTV data processing

The present invention relates to a system stabilization device for data processing of plasma display panel (PDP) television. When a television having a system initialization processing unit of a PDTV television for stabilizing the initial system by removing the uncertain data generated when the power of the PDTV is switched on, the memory is to be removed and the normal data processing is started. An error protecting apparatus of digital data process for plasma display to delay the read operation from the write operation by one vertical sync interval so that the uncertain data in the memory is not initially displayed on the screen. panel television).

A PDTV system which converts an analog image signal into digital data in a PDTV, and displays the image by performing gray level processing on a plasma panel is generally composed of a composite image signal input unit, a digital data processing unit, and a PDP driving unit. Data processing is performed by the configuration as shown in FIG.

Referring to the data processing in the digital data processing unit shown in FIG. 1, the analog image signal received from the antenna is converted into digital data, and the digital data is received and alternately rearranged into a form suitable for shifting the data. The memory unit 3 to be shifted, the data interface unit 4 for outputting the data applied from the memory unit 3 in the form of a data stream, and the data output from the data interface unit 4 are output to the plasma panel. A timing controller section 5 for providing a control signal necessary for the data processing to the address driver IC 6 to be output and displayed, the memory section 3, the data interface section 4, and the address driver IC 6; It consists of.

The digital image data is rearranged in the memory unit 3 of the digital image data processing unit to convert the digitized image data into a form suitable for PDP gray level processing. The rearranged and selected digital image data is selected by using the main clock of the timing controller 5 to output the data to the data interface unit 4, and the data interface unit 4 has a data stream type suitable for gradation processing. The digital video data is output to the address driver IC 6 of the PDP driver.

In order to output data from the digital data processor to the address driver IC 6 of the PDP driver, the data shift signal is supplied from the data shift signal provided by the timing controller 5 of the digital image data processor. It was common to use a method of controlling data output.

The clock signal clk_480 provided from the timing controller unit 5 to the memory unit 3 is a clock signal used for outputting 480 lines of data necessary for forming one frame of the screen. In addition, the shift signal f_107sft provided from the timing controller unit 5 to the data interface unit 4 is a signal of an input shift register for inputting data into the address driving IC 6 and f_32sft is the signal from the data interface to the address driving IC 6. Output shift register signal for outputting data.

In order to perform PDP gradation processing in a PDTV having the above data processing apparatus, an NTSC interlace signal is input, converted into a noninterlace signal, data is processed, and data processing is performed for each weight.

Therefore, since there are many digital chips for processing digital data in the data processing apparatus of the PDTV, when the power supply of the PDTV is switched on, uncertain data (hereinafter referred to as "garbage value data") is initially input. Therefore, when a synchronization signal for normal gradation processing of the PDTV is input, the system may malfunction. In order to prevent the malfunction of the system due to such waste value data, the power of the PDTV television is switched on and the control signal is provided by the timing controller to operate data input / output from the memory unit 3 to the data interface unit 4. There is a system initialization processing apparatus of PDTV that can perform a normal data processing after maintaining a clear time that can remove garbage value data for a predetermined time without preventing the malfunction.

In the above processing apparatus, the read and write operations and the data interface of the memory unit are performed for a predetermined time to remove the waste value data and to stabilize the initial state of the screen when the power is switched on by the timing controller of the PDTV. Stop negative operation. To do this, the data side control is cleared for a certain period of time, and the control on the PDP driving side is operated normally, using a timing controller with a vertical synchronous counter that can count the synchronization signals to make the screen black. There is a data processing device.

However, since the read processing start signal (clear signal) and the write operation start signal provided from the timing controller unit 5 are simultaneously applied to the data processing apparatus after a predetermined time stabilization time has elapsed, the memory unit 3 operates. There is a problem that the first garbage value data input to the is displayed on the screen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem of the initial stabilization apparatus of a PDTV, and an object of the present invention is to perform a read operation when reading and writing data from the memory section after the initial stabilization time of data processing has elapsed. The present invention provides a malfunction prevention device for PDTV data processing which can be operated by delaying time rather than writing operation to remove garbage value data in a memory unit.

As a technical idea capable of achieving the object of the present invention as described above, it is connected to the timing controller unit 5 to count the stabilization time at the beginning of driving of the system, and when the count is over, a high pulse is applied to the timing controller unit 5 In the data processing apparatus having a counter 100 for releasing the stop state of the memory section 3 and the data interface section 4 so as to perform normal data processing, reading is started when the normal data processing of the memory section and the data interface section starts. In order to delay the operation (read) than the write operation (data), the data processing apparatus is provided with a clock generator to generate and output a read start signal and a write start signal corresponding to the stop release signal, respectively, in the timing controller. Presented.

1 is a block diagram of a digital data processing apparatus of a PDTV.

FIG. 2 is a diagram for describing a control signal output state of the timing controller of FIG. 1.

3 is a schematic block diagram of a PDTV.

4 is a block diagram for explaining an embodiment of the present invention.

FIG. 5 is a view for explaining a control signal output state of a timing controller according to the exemplary embodiment of FIG. 4.

<Description of the code | symbol about the principal part of drawing>

1: AV unit 2: ADC unit

3: memory section 4: data interface section

5: Timing Controller Part 6: Address Driving IC

7: holding / scanning driving IC 8: high voltage driving circuit

9: AC / DC conversion unit 10: analog composite video signal processing unit

20: digital data processing unit 30: PDP drive unit

100: counter 200: read clock generation unit

300: write clock generator

Hereinafter will be described in detail with reference to the accompanying drawings with respect to the configuration and operation of the embodiment for achieving the object of the present invention. First, the digital data processing system for PDP gradation processing of PDTV will be briefly described to help understand the present invention. PD Display (Plasma Display Panel) has been in the spotlight as the next generation display device due to its easy color display and large size. The PDTV, which is a television using a PD, uses a plasma display. Plasma is another state different from a solid, liquid, or gas which is generally a three-phase phase of a substance. It refers to the ionized state by obtaining energy by the power of. Therefore, the plasma display may be a device that displays text, graphics, or images by using a glow discharge region during gas discharge. The plasma display operating in the glow discharge region has an advantage of maintaining the discharge at a voltage lower than the discharge start voltage. PDTV is a device that implements an image by converting an analog image signal received using the plasma display apparatus into digital data and performing gradation processing on the plasma panel.

Fig. 2 shows a schematic configuration of a PDTV using the above plasma display.

The analog composite video signal input from the antenna is digitalized by the analog composite signal processing unit 10 which is analog-processed by the AV (Audio-Video) unit 1 and the analog signal, and is digitalized by the ADC unit 2 with constant data. The digital image data is again converted into a data stream (Data stream) conforming to the characteristics of the PDP grayscale processing through the memory unit 3 and the data interface unit 4, and the data stream. The PDP driver 30 and the timing control unit 5 and the high voltage driving circuit unit 8 which receive the input signal from the address driver IC unit 6 to the plasma panel to display an image are provided. (Sustain Driver IC) The high voltage control pulse required by the unit 6 is output, and the AC / DC unit 9 is configured to generate and supply all DC voltages required by the entire system by inputting AC power. All.

The AV unit 1 receives the NTSC composite signal, separates the analog RGB signal from the horizontal and vertical synchronization signals, obtains an average picture level (APL) corresponding to the average value of the luminance signal (Y), and then converts the ADC unit (2). To feed. This APL is used to improve the brightness of the PDTV system.

NTSC composite video signal is interlaced scan method, and one frame is composed of two fields of odd / excellent, horizontal synchronous signal has a frequency of about 15.73KHZ and vertical synchronous signal about 60Hz. The audio signal separated from the composite video signal is output through the audio amplifier directly to the speaker.

The ADC unit 2 receives an analog RGB signal as an input, converts it into a digital data, and outputs the digital data to the memory unit 3, where the digital data is an image data of a converted shape for improving the brightness of the PDTV system. The ADC section 2 is composed of an amplifier section, a clock generation section, a sampling area setting section, and a data mapping section.

The amplifying section of the ADC section 2 amplifies the analog RGB signal and the APL signal to a signal level suitable for quantization, and converts the horizontal and vertical synchronous signals into a constant phase and outputs them. The clock generator must use a clock that is synchronized with the input synchronization signal. The clock generator generates clocks using phase locked loops (PLLs). PLL is used to compare the phase of the input synchronous signal with the phase of the variable pulse output from the loop. And a PC (Programmable Counter) for dividing the output of the VCXO and the output of the VCXO to output a phase comparison pulse, thereby outputting a clock synchronized with the input synchronous signal. If the clock synchronized to the input synchronization signal is not used, the vertical linearity of the displayed image is not guaranteed. The sampling area is set to the vertical position and the horizontal position. The vertical position section is a pulse for setting only the line with the image information among the input signals, and the horizontal position section is a pulse for setting only the time with the image information among the lines set to the vertical position. The vertical position section and the horizontal position section are the standards for sampling.

A total of 480 lines are selected, 240 lines each for even / odd fields. The horizontal position section should be such that there can be at least 853 sampling clocks per selected line. The data mapping unit maps RGB data output from the ADC unit 2 into data corresponding to brightness characteristics of the PDP and outputs the data. In other words, by arranging several vector tables in the ROM and selecting the optimal vector table according to the digitized APL data, the RGB data output from the ADC unit 1 is mapped by one to one. To provide.

In the memory unit 3, for the PDP gradation processing, it is necessary to reconstruct the video data of one field into a plurality of subfields, and then rearrange from the most significant bit MSB to the least significant bit LSB. In addition, since the image data inputted by the interlaced scanning method is converted into a sequential scanning method and displayed, an area for storing one frame of image data is required. It is required to be arranged in accordance with the RGB pixel arrangement output from the memory section 3 and supplied to the address driver IC 6, which is why the data interface section 4 is required. The display size is 853 × 3 (RGB) × 480, and the data interface part needs to temporarily store 1 line of data (853 × 3 = 2559bits) .Because the data continuity must be guaranteed (input and output are performed simultaneously), 2 A temporary storage area of 2559 x 2 = 5118 bits is required. 24 bits of data, 8 bits each of RGB from the memory unit 3, are input to the temporary storage area A in turn (107 times) (24 bits x 107 = 2568 bits), and at the same time interval, the previous one-line amount of the temporary storage area B is stored. Data is output in the form of a data stream required by the address driver IC. Such input / output operations occur alternately in the temporary storage areas A and B. FIG. That is, after the temporary storage area A operates in the input mode, B operates in the output mode, and then, the operations in which A enters the output mode and B enters the input mode are repeated.

When outputting the temporarily stored digital data to the address driver IC 6, the data interface unit 4 provides 1 bit of data and a total of 48 bits of image data to each address driver IC 6 in the form of a stream. In this way, when data is sequentially input to the address driver IC and shifted in parallel, one line (2559 bits) of image data is loaded into the address driver IC 6. This process should be the same as the input mode operation time of other temporary storage areas, so the input mode should be operated at twice the frequency of the output mode.

The high voltage driving circuit unit 8 combines the DC high voltage supplied from the AC / DC converter 9 according to the control pulses of various logic levels output from the timing controller unit 5, and the address, scan, and sustain driving ICs 7 The control panel needed to generate the control pulse can be driven to drive the plasma panel. In addition, the data stream provided from the data interface unit 4 to the address driver IC 6 is also raised to an appropriate voltage level to enable selective writing on the panel.

In the AC / DC converter 9, AC power (220V, 60Hz) is input, and the high voltage required to combine the electrode driving pulses for driving the PDP and the DC voltage required by each part constituting the other PDTV system. Create and supply.

On the other hand, in the driving method for PDP gradation processing, one field (60 Hz) is first divided into several subfields (64 gradations: 6 subfields, 256 gradations: 8 subfields), and image data corresponding to each subfield is address driven. The IC 6 writes to a PD panel in units of lines. In the subfield to which MSB data is written, the number of discharge sustain pulses is reduced in order from the LSB subfield, and gradation processing is performed for the total discharge sustain period according to the combination thereof. In this case, the same data is displayed twice in the even / odd field to eliminate flickering due to sequential scanning. The driving sequence of all the subfields repeats the operations of writing and erasing all screens, writing data, and maintaining discharge (screen display).

One subfield is an operation mode for discharging the discharge. In the case of AC PDP, in the period of neutralizing the wall charge, a discharge is formed at a low voltage so that the wall charge is not sufficiently formed, or an erase pulse having a short pulse width is applied to the wall. Eliminate wall charges by preventing charges from reaching steady state. In order to erase the wall charge remaining in the selected (discharged) pixel after discharge sustaining of the previous subfield, the wall charge is written to all the pixels for a short period of time which is not visible, and then all the pixels are discharged. In this case, the entire screen erasing operation (Erasing mode) initializes the PDP by erasing all the remaining wall charges, and writes and discharges the data by line through the data write electrodes while shifting the scan pulses sequentially to the line scan electrodes. The data writing and scanning mode necessary for the initial discharge formation to selectively form the wall charges on the pixel to be discharged, and the discharge function are performed by the sustain pulse having a lower voltage than the selection pulse by using the storage function characteristics of gas discharge. This is achieved by repeating the sustain discharge operation.

3 is a block diagram of a data processing apparatus of the present invention. A memory unit 3 which receives digital data applied from the ADC unit 2, rearranges the data in a form suitable for shifting the data, and shifts the data alternately and shifts the data applied from the memory unit 3 in the form of a data stream; The data interface unit 4 for outputting the data interface unit 4, the address driving IC 6 for outputting and displaying the data output from the data interface unit 4 to the plasma panel, the memory unit 3, and the data interface unit ( 4) a timing controller section 5 for providing a control signal for the data processing to the address driver IC 6 and a timing start section 5 connected to the timing controller section 5 to provide a read start signal to the memory section 3; A read clock generation unit 200 to be applied, a write clock generation unit 300 connected to the timing controller unit 5 to apply a write start signal to the data interface unit 4, and Connected to the timing controller unit (4) and consists of a 5 bit counter 100 for counting a vertical synchronizing signal applied from the system.

The operation of the embodiment of the present invention described above will be described. When the power supply of the PDTV is switched on, the counter 100 operates to count the vertical synchronization signal for 0.5 seconds. While the counter 100 is counting the vertical synchronization, the timing controller 5 does not provide control signals to the memory 3 and the data interface 4. Data input / output operation is stopped. The counter 100 for counting the vertical synchronization is the vertical synchronization occurs 60 times in one second, so if you count only up to 30 it is to count the time of 0.5 seconds. When the counter 100 counts the vertical synchronization to 30, the operation stops and maintains the value. On the other hand, when the counter 100 counts the vertical synchronization, the counter counts to an active low state, and counts 30 vertical synchronizations, and then changes to the active high to generate a pulse.

4 is a view for explaining the operation of the counter unit 100 of FIG. 3, which is an embodiment of the present invention. In the 5-bit counter 100, it operates as an active low until it counts the vertical synchronization signal input from the system and counts 30 vertical synchronizations, and then changes to an active high after 30 counts (0.5 seconds) is completed. It acts to output pulse to the output terminal of.

The timing controller 5 receives the output pulses of the counter 100 and operates the clear stages of the memory unit 3 and the data interface unit 4 to release the stop state to perform normal data processing. To provide a control signal.

In the read clock generator 200 operating with the active high pulse of the timing controller 5 as a control signal, the write clock generator 300 starts operation by a vertical synchronization signal and then moves to the next vertical synchronization. It operates according to the input of. As described above, the operation of operating the read clock generator 200 after one vertical synchronization signal without operating simultaneously will be described in more detail.

5 is a view for explaining the operation of the main part of the embodiment of the present invention. The write clock generator 300 receiving the output signal from the counter 100 and operating by the vertical sync signal, and the vertical sync signal one section after the vertical sync signal input to the write clock generator 300. And a read clock generator 200 having a vertical synchronous signal input.

The active high pulse signal is generated at the signal input terminal of the write clock generator 300 and the read clock generator 200 as shown in the left waveform of FIG. 4 after counting up to 30 vertical synchronization signals from the counter 100. Is entered. The write start signal from the write clock generation unit 300 on the memory unit 3 side becomes high in accordance with the next vertical synchronization after 0.5 seconds after the system is switched on, and the read stop state is released. The reason for this is that the garbage data in the previous memory section is not read as described above. Therefore, the read start signal of the memory part becomes high in accordance with the second vertical synchronization 0.5 seconds after the system is powered on, thereby releasing the read stop state.

As described above, the present invention provides a timing controller unit for controlling the system to perform normal PDP gradation processing by clearing the garbage value data input in the initial state when the power of the PDTV is switched on. A 5-bit counter is connected to (5) to stop the supply of the control signal from the timing controller unit 5 while counting the vertical synchronization signal input at the same time as switching on the power supply. In the data processing apparatus to release the control signal supply stop of the timing controller unit 5 so that the data input / output relation between the memory unit 3 and the data interface unit 4 is normally performed. 5) the time difference is placed on the vertical synchronization signal input to the write clock generator 300 and the read clock pulse 200 As a result, the garbage value data in the memory can be removed and the data can be processed.

Claims (2)

In a PD TV that converts an analog image signal into digital data and processes the digital data to perform normal gray level processing after clearing input data that is not normal when the power is switched on in a PD TV displaying the screen. Memory means (3) for receiving the digital data and rearranging the data to be suitable for the gradation processing so as to repeat the data writing and reading operation by the data select signal; Data interface means (4) for outputting the digital data applied from the memory means (3) in the form of a data stream so as to efficiently perform PDP gradation processing; Control means (5) for applying data read start signal and write start signal to said memory means (3) for data processing; And a counting means (100) for stopping the supply of the control signal for an initial predetermined time and counting the stop time to the control means (5), When the count means 100 stops counting the stop time, a high pulse is applied to the timing controller unit 5, so that the stop signal of the data read operation in the memory unit 3 is higher than the stop signal of the data write operation. A malfunction preventing device for PDTV data processing, characterized in that to be released later. The method of claim 1, wherein the control means (5) comprises a write clock generator 300 that receives the output signal from the counter 100 and operates by a vertical synchronization signal, The read clock generator 200 has a vertical synchronous signal input terminal to input a vertical synchronous signal one section after the vertical synchronous signal input to the write clock generator 300. Malfunction prevention device.

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