KR100217275B1 - A generating apparatus of data load clock for pdp-tv - Google Patents

Abstract

The present invention relates to an apparatus for implementing a PDP display size of a plasma display panel television (PDP-TV). In particular, the present invention relates to a data load clock generator for implementing a display value of 853x480 mode, which is a value of a wide screen (16: 9). In general, the display value of the PDP-TV was a 640 × 480 mode that implements a conventional 4: 3 aspect ratio. In order to implement a wide screen 853x480 mode, a control method different from the conventional data clock control method of the 640x480 mode is required. In the present invention, 480 shift clock signals (clk_480) and reference clock signals (clk) are inputted to the AND gate 10, and the shift clock signals (clk_480) of the 8 counters 20 and 107 counters 40 are returned. The input signal is inputted as a set signal, and the output of the AND gate 10 is inputted to the eight counters 20 and simultaneously inputted to each end of the AND gate 30 together with the outputs of the eight counters 20. The output signal of the gate 30 proposes a data load clock generator which realizes a screen value of 853 × 480 mode in the PDP-TV input to the 107 counter 40.

Description

Data Load Clock Generator of PDP-TV

The present invention relates to an apparatus for implementing a screen display of a specific size in a plasma display panel television (PDP-TV) system comprising a composite image signal input unit, a digital image data processor, and a PDP driver. In particular, the present invention relates to a data load clock generator for implementing a screen size of 853x480 mode.

CRT, which is a general TV system, adopts a method in which an electron gun sequentially scans pixel by pixel, and gradation is composed of a simple driving circuit driven by an analog method, and its driving speed is very fast as several tens of nanoseconds (ns). If the number of pixels is increased to millions like HDTV, it is very difficult to implement the driving of millions of pixels by one pixel. However, in the case of the PDP, which is a flat panel display, a matrix driving method using a strong nonlinearity characteristic of gas discharge is used instead of scanning by pixel. Nonlinearity is a characteristic of gas discharge. Since the gas discharge phenomenon is caused by ionization through the ionization process of the gas, the discharge occurs only when a voltage higher than the discharge voltage at which the ionization reaction can occur sufficiently is applied. Is a characteristic of gas discharge in which no discharge occurs. PDPs are generally driven by a series of pulses with a constant voltage, and gradation display is implemented by digital rather than analog. However, since gas discharge usually requires a relatively high voltage of several hundred volts, the video signal is amplified and driven. The reason why the PDP is suitable for the enlargement is that not only the process but also the characteristics useful for the enlargement of the gas discharge can be applied to the driving method. The concept of driving technology of PDP is as follows. PDP is an active light emitting display device in which ultraviolet light generated by gas discharge excites a fluorescent film to implement an image. In other words, since the PDP uses ultraviolet light emitted by gas discharge as a light source corresponding to each pixel, the driving circuit simply functions to form or erase gas discharge for each pixel in order to implement a display image. The driving circuit includes an image signal and signal control unit for each pixel constituting an image, and a high speed high voltage switching control unit that can form or eliminate ultraviolet rays generated from each pixel. The driving operation of the PDP-TV system can be classified into three types: selection operation, holding operation and erasing operation.

The selection operation is a driving operation necessary for initial discharge formation. In the case of Pen + mixture of He + Xe and Ne + Xe commonly used in PDP, potential of 240V ~ 280V is applied. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation.

The holding operation is a driving operation in which discharge is maintained by a holding pulse having a voltage lower than a selection pulse by using the storage function characteristic of gas discharge. In the case of AC type PDP, the memory function effect by wall charge and the self priming effect are used in case of DC type PDP. In the case of the memory type driving method which can separate the selection operation and the holding operation by using the memory function, in the case of high gradation display for realizing a high quality display device, the PDP can operate without deterioration of luminance even for a large display device. It provides a driving method.

In the case of AC-type PDP, the discharge is formed at a low voltage in the period of neutralizing the discharging charge so that the wall charge is not sufficiently formed, or the erasure pulse having a short pulse width is applied to prevent the wall charge from reaching the steady state. Remove it.

PDP using gas discharge has a memory function. The memory function is a phenomenon in which the past state affects the present state. In the case of AC PDP, it has a unique memory function due to the wall charges formed in the dielectric. In the case of DC PDP, the charged particle effect is used. Although the PDP adopts the driving method using the row driving method, it would not be possible to apply the large display without the memory function. The memory function is essential for driving a large display element for displaying a high gradation image, and it can be seen that it has a very useful function in gradation display. AC PDPs have a unique memory function because charged particles such as electrons and ions formed during gas discharge form wall charges in the dielectric covering the electrode. In other words, there is no wall charge in the dielectric when there is no discharge, and wall charge is accumulated in the dielectric when a discharge is formed. When the wall charge is present, the potential applied to the external electrode and the potential caused by the wall charge are added together, so that a discharge is formed at a low voltage. Thus, the operation of discharging at a low potential can be separated by the operation of discharging (addressing) without the help of wall charge and the help of the wall charge. In the case of the AC type PDP having the above characteristics, there is a memory function by wall charge, and various driving methods are used according to the method using such wall charge. The present invention relates to an apparatus for generating a clock for loading data in a data interface unit for outputting digital data to the PDP unit in the PDP-TV driven as described above.

The screen size at 4: 3 aspect ratio of the PDP-TV described above was 640 × 480 mode. That is, the R, G, and B data output from the memory unit of the PDP-TV must be rearranged and supplied to the address driver IC according to the RGB pixel arrangement of the panel, which is why a data interface unit is required. In the 640 × 480 mode system, the data interface unit must temporarily store one line of data (640 × 3 = 1920bits) .Because data continuity must be guaranteed (input and output are performed simultaneously), two lines (1920 × 2) are used. = 3840bits) is needed. That is, a total of 24 bits of data of 8 bits each of R, G, and B are sequentially inputted from the memory unit (80 times) into the first temporary storage area (24 bits x 80 = 1920 bits), and at the same time interval, the second temporary storage area is inputted. The previous one-line amount of data is output in the form of a data stream required by the address driver IC. Such an input / output operation alternately occurs in the first and second temporary storage areas. That is, after the first temporary storage area operates in the input mode and the second temporary storage area operates in the output mode, the reverse operation is then repeated. However, in order to realize a wide screen of 853 × 480 mode, a panel having 8 bits accesses 853 ÷ 8 ≒ 107, that is, one weight of data can be loaded when addressing 107, so the 640 × 480 mode of the conventional apparatus can be loaded. There was a problem that can not be used as the data load clock generator of.

In addition, only 107 clocks are needed to load one weight of data. Since one section of the clock signal clk_480 consists of a reference clock signal of 150 clocks, all 150 clocks are used to load one weight of data, which causes unnecessary malfunctions. There was a problem.

An object of the present invention is to implement a screen display of a wide screen 853 × 480 mode in the PDP-TV, to load the data corresponding to one weight amount in the 150 clock period corresponding to one clock of clk_480 The present invention provides a data load clock generator capable of accurately generating 107 clocks.

According to an embodiment of the present invention, 480 shift clock signals clk_480 and a reference clock signal clk are input to the AND gate 10, and the addressing clock signal clk_480 is provided. Is inputted as a reset signal of the eight counters 20 and 107 counters 40, and the output of the end gate 10 is input to the eight counters 20 and simultaneously with the outputs of the eight counters 20. Input to each end of the AND gate 30, the output signal of the AND gate 30 generates a data load clock for implementing the screen value of the 853 × 480 mode in the PDP-TV input to the 107 counter 40 The device is presented.

1 is a block diagram of a data load clock generator according to an embodiment of the present invention.

2 is a clock and data waveform diagram of each part of FIG.

3 is a block diagram showing the overall configuration of a PDP-TV system;

4 is a block diagram of a memory unit as a main part of FIG.

* Explanation of symbols for main parts of the drawings

1: AV unit 2: ADC unit

3: memory section 4: data interface section

5: timing controller 6: address driving IC

7: holding / scanning driving IC 8: high voltage driving circuit

9: AC / DC switch 10,30: end gate

20: 8 counter 40: 107 counter

40: composite video signal processing unit 50: digital data processing unit

60: PDP drive unit 70: data rearrangement unit

80: address generator 90: control clock generator

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Accompanying drawings, Figure 3 is for explaining the overall operation of the AC-type PDP-TV system. The PDP-TV generally includes a composite video signal processing unit 50 including an AV unit 1 which analog-processes a composite video signal received through an antenna and provides it to an ADC unit, and digitally processes the input analog composite video signal. The ADC unit 2 for performing the operation, the memory unit 3 for rearranging the digital image data input from the composite video signal unit 50, and the rearranged digital image data, and are suitable for PDP gray level processing. Digital data comprising a data interface unit 4 for producing a stream, the memory unit 3, the data interface unit 4, and a timing controller unit 5 for generating and supplying a main clock for controlling the entire system. Maintaining / notes with the address driver IC 6 receiving the data stream from the processing unit 60 and the data interface unit 4 and supplying data to the plasma panel for gradation processing It consists of the PDP drive part 70 which consists of four driver ICs.

The AV unit 1 receives the NTSC composite signal, separates the analog R, G, and B signals from the horizontal and vertical synchronization signals, and obtains an APL (Average Picture Level) corresponding to the average value of the luminance signal (Y). It supplies to (2). This APL is used to improve the brightness of PDP-TV systems. NTSC composite video signal is interlaced scanning method, and one frame is composed of two fields of Odd / Even, horizontal synchronous signal is about 15.73KHZ, and vertical synchronous signal is about 60Hz. The audio signal separated from the composite video signal is output through the audio amplifier directly to the speaker. The ADC unit 2 receives analog R, G, and B signals as inputs, converts them into digital data, and outputs them to the memory unit 3. At this time, the digital data is converted into shapes for improving the brightness of the PDP-TV system. Video data. The ADC section 2 is divided into an amplifier section, a clock generation section, a sampling area setting section, and a data mapping section. The amplifying section in the ADC section 2 amplifies the analog R, G, B and APL signals to a signal level suitable for quantization, and converts the horizontal and vertical synchronization signals into a constant phase and outputs them. The clock generator must use a clock that is synchronized with the input synchronization signal. To this end, the clock generator generates clocks using phase locked loops (PLLs). The PLL is oscillated by the LF (Loop Filter), which outputs the control voltage of PD (Phase Detector), VCXO (Voltage Controlled Crystal Oscillstor), which compares the phase of the input synchronous signal with the phase of the variable pulse output from the loop. A VCXO and a PC (Programmable Counter) for dividing the output of the VCXO and outputting a phase comparison pulse to output a clock synchronized with the input synchronous signal. If the clock synchronized to the input synchronization signal is not used, the vertical linearity of the displayed image is not guaranteed. In addition, the sampling area is set to a vertical position and a horizontal position. The vertical position section is a pulse for setting only the line with the image information among the input signals, and the horizontal position section is a pulse for setting only the time with the image information among the lines set to the vertical position. The vertical position section and the horizontal position section are the standards for sampling. At this time, a total of 480 lines are selected, each with 240 lines in the Odd / Even field. The horizontal position section should be such that there can be at least 853 sampling clocks per selected line. The data mapping unit of the ADC unit 2 maps the R, G, and B data output from the A / D converter into data corresponding to the brightness characteristics of the PDP. In other words, by arranging several vector tables in the ROM and selecting the optimal vector table according to the digitized APL data, the R, G, B, and R: It is provided to the memory unit 3 in the form of B data.

In the memory unit 3, for the PDP gradation processing, it is necessary to reconstruct the video data of one field into a plurality of subfields, and then rearrange from the most significant bit MSB to the least significant bit LSB. In addition, since the image data input by the interlaced scanning method is converted to the progressive scanning method and displayed, an area for storing one frame of image data is required.

4 is a block diagram of a memory unit that performs the above functions. That is, the memory unit 3 can be roughly divided into a data rearrangement unit 80 and an address generation unit 90. In addition, the memory unit 3 includes a control clock generator 100, two frame memories A, B, and a data selector. The data rearrangement unit 80 is composed of shift registers A, B, D-FF MUX. (D flip-flop and multiplexer), and three-state buffers A, B, and the ADC unit 2 in parallel (MSB to LSB). The provided image data is rearranged so as to store bits having the same weight in one address of the frame memory. While the first shift register loads eight samples of image data, in the second shift register, eight samples of image data previously loaded are the least significant bit (LSB, 8) from the most significant bit (MSB, 8 Bits). Bits) are output while sequentially shifting.

In order to continuously rearrange the video data provided by the ADC unit 2, two first and second shift registers are provided, and they alternately load and shift. The D-FF MUX selects the same weighted data (Recordered Data) output in the shift mode and supplies it to the tri-state buffer. In addition, two frame memories are provided for storing one piece of image data (853 x 3 (RGB) x 480 x 8 Bits x 10 Mbit), and they alternately perform write and read operations in units of frames. The video data can be stored and displayed continuously. Therefore, the tri-state buffers A and B serve to connect the rearranged image data provided from the D-FF MUX to the frame memory in the write mode. Since the address generator 90 converts and displays the image data input by the interlaced scanning method in a sequential scanning method, the order of write addressing and read addressing are different. That is, image data of one field stored in the memory is repeatedly read even line data after reading one line of Odd line data.

Further, in the PDP gradation process, one field is divided into several subfields, and image data corresponding to each subfield must be read in turn and provided to the data interface unit 4, so that the reading order is structurally very different from the writing order. Will have Therefore, a write address generator and a read address generator according to the designed memory map configuration are required, and the address selector serves to provide a corresponding address according to each operation mode (write and read mode) of the frame memories A and B.

The control clock generator 100 receives the vertical and horizontal synchronization signals H and Vsync and the main clock as inputs to generate and supply the write / read address clock and all other logic control pulses required to drive the memory unit 3. . The data selector selects the image data output in the read mode among the frame memories A and B and provides the image data to the data interface unit 4. The data interface unit 4 receives R, G, and B data from the memory unit 3. Is stored temporarily and provided in the form of data required by the address driver IC 6. It is required to be arranged in accordance with the arrangement of the R, G, and B pixels output from the memory section 3 and supplied to the address driver IC 6, which is why the data interface section 4 is required. The display size is 853 × 3 (r, g, b) × 480, and the data interface unit 4 should temporarily store one line (853 × 3 = 2559 bits) of data. Since the output must be performed simultaneously, two lines of temporary storage (2559 x 2 = 5118 bits) are needed. That is, a total of 24 bits of data of 8 bits each of R, G, and B from the memory unit 3 are sequentially inputted to the first temporary storage area (107 times) (24 bits x 107 = 2598 bits), and at the same time intervals, the second temporary data is stored. The data of the previous one line of the storage area is output in the form of a data stream required by the address driver IC 6. Such an input / output operation alternately occurs in the first and second temporary storage areas. That is, after the first temporary storage area operates in the input mode and the second temporary storage area operates in the output mode, the reverse operation is then repeated. When the data interface 4 outputs the temporarily stored video data to the address driver IC 6, the data interface unit 4 provides 1 bit of data and 48 bits of video data in a stream form to each driver IC. When data is input to the driver IC in turn (75 times) in this manner, when shifted in parallel, one line of image data (48 bits x 75 = 3600 bits) is loaded into the address driver IC 6. Since this process should be the same as the input mode operation time of the other temporary storage area, the input mode should be operated at a frequency twice that of the output mode. The high voltage driving circuit unit 8 generates various logic outputs from the timing controller unit 5. According to the control pulse of the level, the DC high voltage supplied from the AC / DC converter 9 is combined to generate the control pulse required by the address, scan, and sustain driver IC to drive the PDP. In addition, the data stream provided from the data interface unit 4 to the address driver IC 6 is also raised to an appropriate voltage level so that selective writing is possible on the panel. 60 Hz) is divided into several subfields (64 gradations: 6 subfields, 256 gradations: 8 subfields), and the image data corresponding to each subfield is written to the panel line by line through the address driver IC 6. In the subfield to which MSB data is written, the number of discharge sustain pulses is reduced in order from the LSB subfield, and gradation processing is performed in the total discharge sustain period according to a combination thereof. In addition, the driving sequence of all subfields repeats operations of full screen writing and erasing, data writing, and discharge holding (screen display). This process is outlined as follows.

As the operation mode for erasing discharge, in case of AC PDP, the discharge is formed at low voltage in the period of neutralizing the subordinate charge so that the wall charge is not sufficiently formed or the erase charge pulse having short pulse width is applied to the normal state of the wall charge. To prevent the wall charges from being reached, i.e. to erase the wall charges remaining in the selected (discharged) pixels after sustaining the discharge of the previous subfield, the walls on all the pixels for a short period of time that are not visible. A full screen erasing process of initializing the PDP by writing charges and then erasing all the remaining wall charges by erasing all pixels;

In the case of Pen + mixture of He + Xe and Ne + Xe commonly used in PDP, potential of 240V ~ 280V is applied. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation. In the practical application, a selective operation is performed in which a wall charge is selectively formed on a pixel to be discharged by writing the data in line units through the data writing electrode while shifting the scanning pulse sequentially from 1 to 480 to the line scan electrode. In addition, the data writing and scanning process, which is a driving operation required for initial discharge formation,

In the case of AC PDP, the memory driving method that can separate the selection operation and the holding operation by using the memory function effect by wall charge, and the PDP is large in the case of high gradation display to realize high quality display device. A driving method which can operate without deterioration of brightness also in the display element of is provided. In practice, a sustain pulse is alternately applied between the discharge sustain driver electrode and the line scan electrode to start and sustain the discharge of the pixel on which the wall charge is formed. At this time, since the unwritten pixel is affected by the written peripheral pixels, and there is a possibility of causing an error discharge, the discharge sustaining process is performed so that a small amount of erase is performed every time the sustain pulse is applied.

In the AC / DC converter 9, AC power (220V, 60Hz) is input, and the high voltage required to combine the electrode driving pulses shown in FIG. 8 and the DC voltage required by each part constituting the other PDP-TV system. Create and supply

Hereinafter, embodiments of the present invention will be described in detail with reference to the configuration and operation of the entire system of the PDP-TV. 1 is a block diagram of a data load clock generator for implementing an 853 × 480 mode according to an embodiment of the present invention. The clock signal clk_480 and the reference clock signal clk necessary for the data shift are input to each end of the AND gate 10, and one section of eight subfields included in one frame of the vertical synchronization signal is allocated to an addressing section and a sustaining section. 480 shift clock signals (clk_480) are present in the addressing period, and the shift clock (clk_480) and the reference clock may coincide with each other in the shift clock. The signal is outputted to the eight counter 20 at the time, and the eight counter 20 transmits a signal of delaying the first eight clocks among the 150 clocks of the one section of the shift clock clk_480 to one end of the AND gate 30. The output of the AND gate 10 is input to the other end of the AND gate 30, and the output corresponding to the AND gate 30 is counted to the 107 counter 40 counting 107 clocks. Output, the above shift The clock signal clk_480 serves as a reset signal of the eight counters 20 and 107 counters 40 to generate 107 clock signals required to load one weight amount of data from the 107 counters. Consists of.

2 is a waveform diagram of the operation of each part according to the configuration of the present invention described above. Referring to Figure 2 will be described in detail the operation of the data load clock generator of the present invention. In the case of the 8-bit access, basically, 480 shift clocks (clk_480) and the main clock (clk), which are the reference clocks, are included in the addressing section of the section corresponding to one subfield including the addressing section and the discharge sustaining section. The AND gate 10 is input to the AND gate 10, and the AND gate 10 outputs one section of the addressing clock CLK_480 and 150 main clocks CLK corresponding thereto to the eight counters 20. The eight counter 20 delays eight clocks from the first clock of the 150 main clocks and then turns on the shift clock CLK_480 to input one end of the AND gate 30. The output of the AND gate 10 is input to one end of the AND gate 30. The signal matched by the AND gate 30 is output to the 107 counter 40, and the 107 counter 40 generates 107 clocks and loads the data using the clocks to 107 and 107 clocks. A configuration is provided for outputting corresponding data.

As described above, according to the present invention, in generating a clock for loading data, in order to implement a display size of 853x480 mode, it is assumed that 150 main clocks are included in the address period of the addressing clock in logic design. By using 20) and 107 counter 40 to accurately generate the 107 clocks needed to load one weight of data and to load the data, the effect of preventing errors in data loading due to the use of unnecessary clocks have.

Claims (2)

In the PDP-TV (Plasma Display Panel Television) system, which receives a composite video signal and provides digitally processed data from the digital data processing unit 60 to the PDP driving unit 70 via the data interface unit 4 to display the screen. , An AND gate 10 into which 480 shift clock signals clk_480 and a reference clock signal clk are input at each stage, 8 counters 20 for inputting the 480 shift clock signals clk_480 as reset signals, receiving the signals of the AND gate 10, and outputting a signal delayed by 8 clocks; An AND gate 30 into which the output of the AND gate 10 and the 8 clock delay signal output from the 8 counters are input to each stage, And a clock signal of CLK_480 as a reset signal, and generating 107 clock signals by receiving the output signal of the AND gate (30). The data load clock generator of claim 1, wherein the 107 clock signals are necessary to load one weight of data from a PDP-TV having a display size of 853x480 mode.

Images