KR100397355B1 - Method for preventing erroneous operation in vertical synchronous interval of pdp television - Google Patents

Abstract

PURPOSE: A method for preventing erroneous operation in a vertical synchronous interval of a PDP television is provided to prevent erroneous operation of a counter in a vertical synchronous interval. CONSTITUTION: A timing controller counts a whole vertical synchronization interval by using a 16-bit counter. Due to excessive count frequency within a short time, an unstable clock signal is generated and a high part of a vertical synchronous signal is unstably decreased and increased. Therefore, the next vertical synchronous signal is prevented from coming and the counter returns to the beginning. To prevent erroneous operation of the counter, a logic is constructed to utilize an output signal of the counter as a reset signal and a count time is limited as much as one vertical synchronous interval so that the counter stops counting and maintains current data.

Description

How to prevent malfunctions in vertical dynamics of PDTVs

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to synchronization signal processing of a plasma display panel television, and an error proof method in vertical synchronization area for vertical synchronization (PV) of a PDP television. plasma display panel television).

PDP television is a driving method for PDP gradation processing. It divides one field (60Hz) into several subfields, and the image data corresponding to each subfield is displayed on the panel by line or block of data through the address driver IC of the PDP driver. It is written in, and gradation processing is performed for the total discharge holding period. At this time, the gradation processing is performed by applying driving pulses to each electrode of the PDP panel during one vertical sync period, and repeating the operations of writing or erasing the entire screen, writing data, and maintaining the discharge. Is done. The driving method of such a PDP flat panel display is different from that of a general television using a CRT. In particular, in the method related to the gradation processing, a general television adopts a method in which the electron gun sequentially scans the pixels one by one, and the gradation processing is composed of a simple driving circuit driven by an analog method, and the driving speed is several tens of nanoseconds. (I) Very fast, but when the number of pixels increases to millions, such as high-definition television (HDTV), it is very difficult to implement the driving of millions of pixels by one pixel. However, in the case of PDP, a matrix driving method using strong nonlinearity characteristics of gas discharge is used instead of scanning pixel by pixel. Here, nonlinearity is a feature of gas discharge, and since the gas discharge phenomenon is caused by ionization through the ionization process of the gas, the discharge occurs only when a voltage above the discharge voltage at which the ionization reaction can be sufficiently generated is applied. It is a characteristic of gas discharge that discharge does not occur with respect to voltage.

The PDP is generally driven by a continuous pulse with a constant voltage, and gradation display is implemented by digital rather than analog. Therefore, the system of the PDP television is operated by the configuration and operation for processing digital data.

In the driving method for the gray scale processing of the PDP, it is common to repeatedly read the odd line data after one line of image data stored in the memory unit after reading one line of even line data. In this case, one field is divided into a plurality of subfields (256 gray scales-8 subfields), and image data corresponding to each subfield is read in sequence and provided to the data interface unit. The driving method of one subfield is performed in the following driving order.

As an operation mode for erasing discharge, AC-type PDP forms a discharge at a low voltage in a period of neutralizing the wall charge so that the wall charge is not sufficiently formed, or an erase pulse having a short pulse width is applied to the wall. Eliminate wall charges by preventing charges from reaching steady state. That is, in order to erase the wall charge remaining in the selected (discharged) pixel after the discharge sustain of the previous subfield, the wall charge is written to all the pixels for a short time which is not visible, and then all the pixels. Erasing mode, which initializes the PDP by erasing all remaining wall charges, and writes the data on a line-by-line basis through the data write electrode while shifting the scan pulse to the line scan electrode. The data writing and scan mode and the storage function characteristics of gas discharge required for the initial discharge formation to selectively form the wall charge in the pixel to be made by the sustain pulse of the voltage lower than the selection pulse Discharge sustain operation in which discharge is maintained.

In the driving method of one subfield as described above, the signal processing states of the entire screen erasing section and the data writing and scanning section are fixed unchanged for each subfield. However, since the discharge sustaining section corresponds to the image display section, it functions differently for each subfield according to the length of the input data. That is, the discharge maintenance section is a variable section that gives a repetitive waveform by varying the discharge maintenance section by the weight of each digital data for gradation processing. For such gradation processing in the PDP television, the timing controller unit 5 counts the vertical synchronizing section using a 16-bit counter. At this time, the count clock is using 2MHz (500ns). If the vertical sync becomes unstable due to the variability of the discharge holding section in one subfield, the same line processing is repeated instead of the even line processing and the odd line processing alternately in the high section of the vertical synchronization signal. there is a problem. If the high section of the vertical synchronous signal where the counter operates is increased, the above counter counts one time for even line processing and does not count when a new vertical synchronous signal comes in for the next odd line process. Even if the vertical synchronization signal does not come in, there is a problem in that an abnormality occurs on the screen at the end of the subfield by counting again from the beginning and repeating the operation for even line processing.

The present invention has been invented to solve the above problems by preventing an error of operation when the vertical sync signal of the PDP television which is a problem of the prior art described above is an unstable input. If there is counting operation during one vertical synchronizing without discriminating between unstable or stable time, PDP television which counts only as long as vertical synchronizing and forcibly controls its operation so that it can no longer operate. It is to provide a method for preventing malfunction in the vertical dynamic mechanism of the).

1 is a schematic block diagram of a PDP television;

2 is a detailed block diagram of a data processing unit that is a main part of FIG. 1;

Fig. 3 is a waveform diagram for explaining a method for preventing malfunction in the vertical moving section of the PDP television according to the present invention.

Figure 4 is a logic circuit diagram required to implement the malfunction prevention method of the present invention

<Description of reference numerals for main parts of the drawings>

1: AV unit 2: ADC unit

3: memory section 4: data interface section

5: Timing controller part 6: Address driver IC

7: Hold / Scan drive IC 8: High voltage drive circuit

9 AC / DC converter 10: composite video signal processor

20: digital image data processing unit 30: PDP drive unit

Hereinafter will be described in detail the configuration and operation of one embodiment of the invention as a specific means for achieving the above object of the present invention. First, the general configuration and operation for the gradation processing of a PDP television will be briefly described in order to facilitate understanding of the present invention. Fig. 1 is a schematic block diagram for explaining driving for screen display of an AC type PDP-TV.

The PDP television analog-processes a composite video signal received through an antenna and provides the analog-to-digital conversion unit (ADC unit) with an antenna, a tuner unit (not shown), an IF amplifier unit, and an AV unit (1). (10), the ADC unit (2) for digitally processing the analog composite video signal input from the composite video signal processing unit (10), and the rearrangement of the digital image data input from the ADC unit (2). A memory unit 3, a data interface unit 4 for receiving rearranged digital image data into a data stream suitable for PDP gradation processing, the memory unit 3, a data interface unit 4, Data from the digital image data processing unit 20 comprising a timing controller unit 5 for generating and supplying control signals such as a main clock and a shift signal for controlling the entire system, and data from the data interface unit 4 described above. An address driving IC 6 for receiving trim image data and supplying data to the plasma panel for gradation processing, a high voltage driving circuit 8 for providing a high voltage required to drive the PDP, and the high voltage driving circuit ( It consists of a PDP driver 30 made of a holding / scanning driving IC 7 driven at the output of 8). In order to display on a PDP television, the AV unit 1 receives an NTSC composite signal, separates an analog RGB color signal from a horizontal and vertical synchronization signal, and uses an APL (Average Picture) corresponding to an average value of the luminance signal (Y). Level) is obtained and supplied to the ADC unit 2. This APL is used to improve the brightness of PDP televisions. NTSC composite video signal is interlaced scanning method, one frame is excellent and consists of two fields of odd number, horizontal synchronous signal is about 15.73KHZ, vertical synchronous signal is about 60Hz frequency. The audio signal separated from the composite video signal is output through the audio amplifier directly to the speaker.

The ADC unit 2 receives an analog composite video signal as an input, converts it into digital data, and outputs the converted digital data to the memory unit 3. In this case, the digital video data is converted to improve the brightness of the PDP television. The ADC section 2 is divided into an amplifier section, a clock generation section, a sampling area setting section, and a data mapping section. The amplifying section in the ADC section 2 amplifies the analog RGB color signal and the APL signal to a signal level suitable for quantization, and converts the horizontal and vertical synchronization signals into a constant phase and outputs them. In addition, the clock generator must use a clock synchronized with the input synchronization signal. To this end, the clock generator generates clocks using phase locked loops (PLLs). The PLL outputs a clock synchronized with the input synchronization signal. If the clock synchronized to the input synchronization signal is not used, the vertical linearity of the displayed image is not guaranteed. In addition, the sampling area is set to a vertical position and a horizontal position. The vertical position section is a pulse for setting only the line with the image information among the input signals, and the horizontal position section is a pulse for setting only the time with the image information among the lines set to the vertical position. The vertical position section and the horizontal position section are the standards for sampling. At this time, a total of 480 lines are selected, each with 240 lines of even and odd fields. The horizontal position section should be the time for at least 853 sampling clocks per selected line.

The data mapping unit of the ADC unit 2 maps RGB image data output from the ADC unit to data corresponding to the brightness characteristics of the PDP. In other words, by arranging some vector tables in the ROM and selecting the optimal vector table according to the digitized APL data, the RGB image data output from the ADC unit 2 is mapped to the memory unit in the form of improved RGB image data. 3) to provide.

The memory unit 3 reconstructs the video data of one field into a plurality of subfields for the PDP gradation process, and then rearranges the most significant bit (MSB) to the least significant bit (LSB). In other words, the image data provided in parallel (MSB to LSB) in the ADC unit 2 is rearranged so as to store bits having the same weight in one address of the frame memory. In addition, since the image data input by the interlaced scanning method is converted into the progressive scan method and displayed, an area for storing one frame of image data is required.

In order to continuously rearrange the RGB image data provided by the ADC unit 2, two first and second shift registers are provided, and they alternately load and shift. In addition, two frame memories that can store one RGB image data (853 × 3 (RGB) × 480 × 8 Bits × 10 Mbit) are also provided, and they alternately perform write and read operations in units of frames. This allows the image data to be stored and displayed continuously.

The data interface unit 4 temporarily stores RGB image data from the memory unit 3 and provides the data in the form of data required by the address driver IC 6. In order to display the screen on the PDP, the data interface unit 4 is required because it is arranged in accordance with the arrangement of the RGB pixels output from the memory unit 3 and supplied to the address driver IC 6.

If the size of the display is 853 x 3 (r, g, b) x 480, the data interface unit 4 must temporarily store one line of data (853 x 3 = 2559 bits) and ensure data continuity. Since the input and output must be performed simultaneously, two lines of temporary storage (2559 x 2 = 5118 bits) are required. That is, a total of 24 bits of data each of 8 bits of the RGB image data from the memory unit 3 are sequentially inputted (107 times) into the first temporary storage area (24 bits x 107 = 2598 bits), and at the same time intervals, the second temporary data is stored. The previous one-line amount of data in the storage area is output in the form of a data stream required by the address driver IC 6. Such an input / output operation alternately occurs in the first and second temporary storage areas. That is, after the first temporary storage area operates in the input mode and the second temporary storage area operates in the output mode, the reverse operation is then repeated.

When the data interface unit 4 outputs the temporarily stored image data to the address driver IC 6, the data interface unit 1 provides one bit of data and a total of 64 bits of image data in the form of a data stream to each driver IC. In this way, when image data is input to the address driver IC in turn (40 times) and shifted in parallel, one line (64 bits x 40? 2559 bits) of image data is loaded into the address driver IC 6. This process should be the same as the input mode operation time of other temporary storage areas, so the input mode should be operated at twice the frequency of the output mode.

The high voltage driving circuit unit 8 combines the DC high voltage supplied from the AC / DC converter 9 according to the control pulses of various logic levels output from the timing controller unit 5. Create a control pulse that is needed in to allow the PDP to run. In addition, the data stream provided from the data interface section 4 to the address driving IC 6 is also raised to an appropriate voltage level to enable selective writing on the PDP panel.

The driving method for PDP gradation processing first divides one field (60Hz) into several subfields (64 gradations: 6 subfields, 256 gradations: 8 subfields), and the image data corresponding to each subfield is divided into an address driver IC ( Fill in the panel by line through 6). It is common to reduce the number of discharge sustain pulses in the order of LSB subfield from the subfield to which MSB data is written, and to perform gradation processing in the total discharge sustain period according to the combination thereof. In addition, the driving sequence of all subfields repeats operations of full screen writing and erasing, data writing, and discharge holding (screen display). This process is outlined as follows.

The full screen write and erase operation is an operation mode for discharging the discharge. In the case of an AC PDP, the discharge is formed at a low voltage in a period of neutralizing the substitutive charge so that the wall charge is not sufficiently formed, or the erase pulse having a short pulse width is generated. Applied to prevent wall charge from reaching a steady state, thereby removing wall charge, i.e., erasing wall charge remaining in selected (discharged) pixels after sustaining discharge of the previous subfield. This operation is to initialize the PDP by writing the wall charges to all the pixels for a short time and then erasing all the remaining wall charges by erasing all the pixels.

The data writing and scanning process applies a potential of 240V to 280V for the He + Xe and Ne + Xe penning mixtures commonly used in PDPs. In the case of alternating current, a third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and to adopt a driving method that separates the selection operation from the sustain operation. In practical application, a selective operation is performed to selectively form wall charges on pixels to write and discharge the data by line through the data write electrodes while shifting the scanning pulses sequentially (1 to 480) to the line scan electrodes. Also, it is a driving operation necessary for initial discharge formation.

In the case of the AC type PDP, in the case of the memory type driving method which can separate the selection operation and the holding operation by using the memory function effect by the wall charge, the PDP is applied in the case of the high gradation display for realizing high quality display elements. There is provided a driving method which can operate even a large display element without degrading the luminance. In the practice of the discharge sustaining process, a sustain pulse is alternately applied between the discharge sustain driver electrode and the line scan electrode to initiate and sustain the discharge of the pixel on which the wall charge is formed. At this time, since the unwritten pixel is affected by the written peripheral pixels, and there is a possibility of causing an error discharge, the operation is performed in such a manner that a small erase is performed every time the sustain pulse is applied so that an accurate discharge is performed.

On the other hand, the AC / DC converter 9 generates and supplies the high voltage required to combine the electrode driving pulses with the AC power source (220V, 60Hz) and the DC voltage required by each part constituting the other PDP television. do.

Hereinafter, the configuration of the data processing system including the memory unit 3, the data interface unit 4, the timing controller unit 5 and the address driver IC 6 of FIG. 1 will be described. This will be described. 2 is a block diagram illustrating a system for data processing of the PDP television described above. The shift clock signal clk_480 is a control signal required when shifting data from the memory unit 3 to the data interface unit 4. That is, in order to display a screen of one frame on a PDP television, 480 lines of 240 lines of good and odd fields are required. The shift clock signal clk_480 repeats high and low clocks for a period corresponding to 480 lines for a period corresponding to 3 ms corresponding to one scan. The selection signal slct is used for writing (storing) data from the memory unit 3 and storing the stored data to the address driver IC 6 in two temporary storage areas, which are spaces for storing one line in the data interface unit 4. It is a control signal that repeats high and low operation so that reading (output) can be alternated. The first instruction control signal f_107sft is a control signal required when shifting data from the memory unit 3 to the data interface unit 4. Since the R, G, and B data are shifted by 8 bits in the memory unit 3, the data is 24 bits. On the other hand, since 853 pieces of data exist for each RGB, one line amount of data corresponds to a data amount of 2559 bits. In order to process one line of 2559 bits by 24 bits, 107 shift signals are required. However, it is unreasonable to switch 107 times for 3 lines of time to process one line of data. Therefore, each data processing section is treated as a group so that only the first indication control signal f_107sft indicating the start time of each group is provided. When the data group comes in, data is continuously processed according to the instruction of the first clock of the first instruction control signal f_107 sft. Subsequently, 480 lines are processed by continuously processing data according to the instruction of the second clock of the same first instruction control signal f_107 sft even during the second one line time.

By the storage signal (high signal) of the selection signal slct in the same manner as described above, one line of data stored in the first temporary storage area of the data interface unit 4 in accordance with the instruction of the first instruction control signal f_107sft. Is outputted to the address driver IC 6 by the output signal (low signal) of the selection signal slct, and the data storage operation for one line is finished by the first instruction control signal f_107sft. The data is shifted to the address driver IC 6 in accordance with the instruction of the second instruction control signal f_32sft indicating the output timing. The output terminal of the address driver IC 6 is 64, and the input terminal is four. Due to the problem of data processing, grouping two address driver ICs together can be simplified to 32 processes. Therefore, thirty-two second instruction control signals f_32sft are required to output data from the data interface unit 4 to the address driver IC 6. That is, f_32sft is a control signal for indicating that the data of the data interface unit 4 is the beginning of the first 32 signals which can be written to the address driver IC 6.

Hereinafter, the present invention will be described in detail with reference to the configuration of the PDP television and the data processing procedure for the gradation processing. FIG. 3 is a waveform diagram illustrating a method of preventing a malfunction in a vertical dynamic period of a PDP television of the present invention.

As described above, there is an operation for PDP gradation processing such as full screen writing and erasing, data writing, and room keeping, which correspond to the operation of one subfield, in the vertical driving mechanism. For these operations, the timing controller 5 uses the 16-bit counter to count the entire vertical dynamic period. In one vertical drive, the time is 16.5 msec. The clock is counting by using 2MHz (500nsec). That is, it operates by counting all 2 ¹⁵ as a whole. In such a short time, the clock signal is unstable due to excessive count times. Due to the unstable clock signal generation, the high portion of the vertical synchronization signal decreases and increases, so that the next vertical synchronization signal does not come in and the counter returns to the beginning and starts counting. For this reason, the end of the screen of one subfield cannot be output to the normal screen. The present invention is to limit the count time to the time of one vertical mechanism in order to prevent the malfunction of the counter in the vertical mechanism between forcibly stop the count and maintain the current data Here's how.

4 is a conceptual diagram of logic for implementing a method for preventing a malfunction of a counter in a vertical driving mechanism of the present invention. In other words, the logic is configured to use the output signal in the counter as a reset signal so that it is no longer operated at a position of 16.5 msec corresponding to the time between the fixed vertical movements by fixing the reset to the counter. Therefore, in a 16-bit counter using a clock of 2MHz, 16.5msec corresponds to 33000. When the counter counts 33000, it stops operation by the stop signal of the logic circuit and maintains the value.

As described above, the present invention does not distinguish between when the vertical synchronization signal is unstable or stable, and if there is a counting operation during one vertical synchronizing period, it counts only as long as the vertical synchronizing period and cannot operate any more. By using the method of acting as the reset signal of the output signal of the PDP television (Plasma Display Panel Television) it is possible to prevent the malfunction of the counter in the vertical dynamics of the display.

Claims (1)

In a PDP television that uses a 16-bit counter to count the system-wide vertical dynamics as a counter clock of 2 MHz, A counting process of counting the entire vertical dynamics of the timing controller; A pulse generation process of generating a pulse after a time set by the vertical dynamic period in a logic circuit configured to generate a pulse after counting for one vertical dynamic period, and A counter resetting step of resetting the counter counting the pulses generated in the pulse generation process in the counting process so that the counter counts and stops for the time set in the pulse generation process; To prevent malfunctions

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