KR100269641B1 - A data interlace method of pdp television - Google Patents

Abstract

PURPOSE: A data interlace method of a PDP(Plasma Display Panel) television is provided to form a data recording/discharging for an upper terminal data line of 1 frame, and to form a data recording/discharging for a lower terminal data line of 2 frame. CONSTITUTION: A system loads data from a memory(31) as a sequential method to temporally store the data in a data interface(32), and outputs the data as a form required by a data driver(60). The system counts the data of the sequential method in order to have line information of 480 numbers during the first vertical synchronous section. The system classifies upper terminal data and lower terminal data during the second vertical synchronous section to perform an interlace operation.

Description

Data Interlacing Method for PDTV

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data interlacing method of a plasma display panel, and more particularly, to a data of a PDTV which discharges the data by distinguishing the upper data line displayed by the upper addressing driver IC from the lower data line displayed by the lower addressing driver IC. It relates to an interlacing method.

In the image display method of a television, the CRT, which is a general television system, adopts a sequential scanning method in which an electron gun sequentially scans pixel by pixel, and the gradation is composed of a simple driving circuit driven by an analog system. It is very fast as tens of nanoseconds (ns), but when the number of pixels is increased to millions such as HDTV, it is very difficult to implement the driving of millions of pixels by one pixel. However, in the case of a PDP, a flat panel display, a matrix driving method using a strong nonlinearity characteristic of gas discharge is used instead of scanning a pixel by pixel. Nonlinearity is a characteristic of gas discharge. Since the gas discharge phenomenon is caused by ionization through the ionization process of the gas, the discharge occurs only when a voltage higher than the discharge voltage at which the ionization reaction can occur sufficiently is applied. Is a characteristic of gas discharge in which no discharge occurs.

On the other hand, PD is generally driven by a continuous pulse having a constant voltage, the gray scale display is implemented by digital rather than analog. However, since gas discharge usually requires a relatively high voltage of several hundred volts, the video signal is amplified and driven. The reason why the PD is suitable for the enlargement is that not only the process but also the characteristics useful for the enlargement of the gas discharge can be applied to the driving method.

The concept of PDP driving technology is as follows. PD is an active light emitting display device in which ultraviolet rays generated from gas discharge excite a fluorescent film to realize an image. In other words, since the PDP uses ultraviolet light emission by gas discharge as a light source corresponding to each pixel, the driving circuit simply functions to form or erase gas discharge for each pixel in order to implement a display image. The driving circuit includes an image signal and signal control unit for each pixel constituting an image, and a high speed high voltage switching control unit that can form or eliminate ultraviolet rays generated from each pixel. The driving operation of such a PDTV system can be classified into three types: selection operation, holding operation and erasing operation.

The selection operation is a driving operation necessary for initial discharge formation. In the case of Pen + mixture of He + Xe and Ne + Xe which are generally used in PD P, apply potential of 240V ~ 280V. In the case of AC, the third electrode is introduced to reduce the high current caused by the sustain electrode in the surface discharge form and the parasitic capacitor caused by the dielectric, and adopts a driving method that separates the selection operation from the sustain operation.

The holding operation is a driving operation in which discharge is maintained by a holding pulse having a lower voltage than the selection pulse by using the storage function characteristic of gas discharge. In the case of the AC type PD, the memory function effect by the wall charge and the DC type PD have the self-priming effect. In the case of the memory driving method which can separate the selection operation and the holding operation by using the memory function, the PDP can operate without losing the luminance even for a large display device in the case of high gradation display for realizing a high quality display device. It provides a driving method.

The erasing operation is an operation mode for discharging the discharge. In the case of a DC type PD, the voltage is lowered to a voltage lower than the discharge sustain voltage. The wall charges are removed by preventing them from forming or preventing wall charges from reaching a steady state due to an erase pulse having a short pulse width.

FIG. 1 is a diagram illustrating a data structure of a general plasma display panel, wherein reference numeral 1 shown in FIG. 1 is an upper address driver IC, and reference numeral 2 is an address driver IC at a lower end. The upper address driving IC includes R0, B0, G1, R2, B2, G3,... Data is inputted to the lower address driving IC, and G0, R1, B1, G2, R3, B3,... Data is input. That is, even data of R and B and odd data of G are input to the upper address driving IC, and odd data of R and B and even data of G are input to the lower address driving IC. When displaying the above R, G, and B data for one frame, the upper data is written and discharged through the upper address driver IC 1, and the lower data is written and discharged through the lower address driver IC 2. The discharge was implemented to realize the video screen. Accordingly, there is a problem in that power consumption is increased by simultaneously writing and discharging the upper data line and the lower data line to implement an image screen for one frame.

Accordingly, the present invention is to solve the above problems, in particular, an object of the present invention is to form a data write and discharge in the upper data line from one frame having information about 480 lines during the first vertical synchronization period, Data erasing is performed on the lower data line, data is erased on the upper data line as opposed to one frame on the second frame displayed during the second vertical synchronization period having information on 480 lines, and data writing and discharging is performed on the lower line. To form. That is, data writing and discharging are formed only for the upper data line of one frame, and data writing and discharging are formed only for the lower data line in two frames, thereby forming a screen through data writing and discharging of the one and two frames. The present invention provides a data interlacing method of PDTV that can reduce power consumption.

1 is an electrode structure of a conventional plasma display panel

2 is a block diagram of a data interlacing apparatus of a PDTV.

3 is a state diagram of a data interlace in accordance with the present invention;

<Code description of main part of drawing>

1: upper address driver IC 2: lower address driver IC

20: analog signal processing unit 21: AV unit

22: synchronization signal separation unit 23: ADC unit

30: digital data processing unit 31: memory unit

32: data interface unit 40: counter unit

50: timing controller 60: data driver

62: scan sustain drive section 64: sustain drive section

66: PD 100: First vertical synchronization signal

110: second vertical synchronization signal

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 2 is a block diagram showing a data interlacing apparatus of a PDTV.

2 includes an AV unit 21 for receiving a composite video signal of a broadcasting station through an antenna, a synchronization signal separation unit 22 for separating vertical and horizontal synchronization signals from an output signal of the AV unit 21; An ADC unit 23 for converting an analog composite image signal applied from the synchronization signal separation unit 22 into a digital unit; a memory unit 31 storing digital image data applied from the ADC unit 23; The data interface unit 32 temporarily stores the image data applied from the memory unit 31 and rearranges the data in a form required by the data driver 60, and outputs the data interface unit 32. The data interface unit 32 is provided from the data interface unit 32. The data driver 60 enables selective writing on the panel by raising the data stream to an appropriate voltage level, and through the address electrode while sequentially shifting the scan pulse to the scan electrode. Is a scan sustain driver 62 for selectively forming wall charges in pixels to be written and discharged data line by line, and a sustain pulse is alternately applied between the sustain electrode and the scan electrode to determine the pixels of which the wall charges are formed. A sustain driver 64 for starting and holding a discharge;

On the other hand, the counter unit 40 is connected to the synchronization signal separation unit 22 and counts the vertical synchronization signal applied from the synchronization signal separation unit 22, and data writing / discharging starts from the counter unit 40. When a pulse and a data erasing pulse are applied, the timing controller 50 is configured to control the timing of the data driver 60, the scan sustain driver 62, and the sustain driver 64.

Hereinafter, each block diagram of the above configuration according to the present invention will be described in detail.

The AV unit 21, the synchronization signal separation unit 20, and the ADC unit 23 are analog signal processing units 20 and generally process the analog composite video signal received through an antenna as an input. That is, the AV unit 21 receives a composite signal of NTSC video and audio, is divided into analog R, G, and B, and obtains an APL (Average Picture Level) corresponding to the average value of the luminance signal (Y). The APL is used to improve the brightness of the PDTV system via the synchronization signal separation unit 22.

In addition, the composite video signal of the AV unit 21 is applied to the sync signal separator 22 to be separated into a horizontal sync signal and a vertical sync signal. The NTSC composite video signal is interlaced and has one frame composed of two fields of Odd / Even. The horizontal sync signal has a frequency of about 15.73KHZ and the vertical sync signal has a frequency of about 60Hz. The signal is output directly to the speaker via a voice amplifier (not shown).

The ADC unit 23 receives analog R, G, and B signals as inputs, converts them into digital data, and outputs them to the memory unit 31. At this time, the digital data is converted into images for improving the brightness of the PDTV system. Data.

The memory unit 31 and the data interface unit 32 are digital data processing units 30. In the memory unit 31, image data of one field of a digital signal applied from the ADC unit 23 for the PD gray level processing is applied. After reconstruction into a plurality of subfields, it is necessary to rearrange the most significant bit (MSB) to the least significant bit (LSB). In addition, since image data input by interlaced scanning is converted and displayed by progressive scanning, an area for storing one frame of image data is required. Thus, the memory unit 31 can be roughly divided into a data rearrangement unit and an address generation unit, and is composed of a control clock generator, two frame memories A, B, and a data selector.

The data rearrangement unit is composed of shift registers A, B, and D flip-flop & multiplexer, and three-state buffers A and B, which are provided in parallel (MSB to LSB) in the ADC unit 23. The video data is rearranged so as to store bits having the same weight in one address of the frame memory. While the first shift register loads eight samples of image data, in the second shift register, eight samples of image data previously loaded are the least significant bit (LSB, 8) from the most significant bit (MSB, 8 Bits). Bits) are output while sequentially shifting.

In addition, two first and second shift registers are provided to continuously rearrange the image data provided by the ADC unit 23, and they alternately repeat the load and shift operations. The D-FF & MUX selects the same weighted data (Recordered Data) output in the shift mode and supplies them to the tri-state buffer. In addition, two frame memories are provided for storing one piece of image data (853 x 3 (RGB) x 480 x 8 Bits x 10 Mbit), and they alternately perform write and read operations in units of frames. The video data can be stored and displayed continuously. Therefore, the tri-state buffers A and B serve to connect the rearranged image data provided from the D-FF & MUX to the frame memory in the write mode.

In the address generator, since the image data inputted by the interlaced scanning method is converted into the progressive scanning method and displayed, the order of write addressing and read addressing are different. That is, image data of one field stored in the memory is repeatedly read even line data after reading one line of Odd line data. In addition, since one field is divided into several subfields and the image data corresponding to each subfield must be read in turn and provided to the data interface unit 32, the reading order is structurally very different from the writing order. Will have Therefore, a write address generator and a read address generator according to the designed memory map configuration are required, and the address selector serves to provide a corresponding address according to each operation mode (write and read mode) of the frame memories A and B.

The control clock generator generates and supplies the vertical / horizontal synchronization signals H and Vsync and the main clock as inputs and all other logic control pulses required to drive the write / read address clock and the memory unit 31. The data selector selects and outputs the image data output in the read mode among the frame memories A and B to the data interface unit 32. The data interface unit 32 temporarily stores R, G and B data from the memory unit 31 and provides the data in the form of data required by the data driver 60. That is, the data interface unit 32 is required to be arranged in accordance with the arrangement of the R, G, and B pixels output from the memory unit 31 and supplied to the data driver 60. The display size is 853 × 3 (R, G, B) × 480 in the wide mode. The data interface unit 32 temporarily stores one line of data (853 × 3 = 2559 bits). A two-line (2559 x 2 = 5118 bits) temporary storage area is required because it must be guaranteed (input and output simultaneously). That is, a total of 24 bits of data of 8 bits each of R, G, and B are inputted from the memory unit 23 into the temporary storage area A in turn (107 times) (24 bits x 107 = 2598 bits), and at the same time intervals. The previous one-line amount of data of the temporary storage area B is output in the form of a data stream required by the data driver 60. Such input / output operations occur alternately in the first and second temporary storage areas. That is, after the first temporary storage area operates in the input mode and the second temporary storage area operates in the output mode, the operation is then reversed.

When the data interface 32 outputs the temporarily stored image data to the data driver 60, the data interface 32 provides 1 bit of data and 48 bits of video data in a stream form to each drive. When data is input to the driving unit in turn (75 times), when shifted in parallel, one line (48 bits x 75 = 3600 bits) of image data is loaded into the data driving unit 60. Since this process should be the same as the input mode operation time of other temporary storage areas, the input mode should be operated at twice the frequency of the output mode.

The scan sustain driver 62 attempts to write and discharge corresponding data in units of lines through the address electrodes 60a, 60b ... while shifting the scan pulses sequentially to the scan electrodes 62a ... of the PD 66. The wall charges are selectively formed on the pixels, and the sustain driver 64 alternately applies a sustain pulse between the sustain electrodes 64a... And the scan electrodes 62a... To initiate and maintain the discharge of the pixels on which the wall charges are formed. In this case, since the unwritten pixel may be affected by the written pixel and cause an error discharge, a small erase is performed every time the sustain pulse is applied to ensure accurate discharge.

Meanwhile, the counter unit 40 detects the vertical synchronizing signal from the horizontal synchronizing signal and the vertical synchronizing signal separated by the synchronizing signal separating unit 22 to perform a counting operation. That is, in order to perform data writing and discharging and data erasing operations, the vertical synchronization signal is countered to output data writing and discharging start pulses and data erasing pulses. The timing controller 50 writes and discharges data and erases data. Control the timing so that the

3 is a vertical synchronization signal according to the present invention implemented by the configuration of FIG. There is one frame (480 lines) of image data in every vertical synchronization signal section, and one frame is implemented as two fields. That is, data writing and discharging are formed through the upper data line during the first vertical driving mechanism 100, and data is erased through the lower data line. During the second vertical driving period 110, data is erased through the upper data line and data write and discharge are formed through the lower data line. Therefore, one image screen is formed by data writing and discharging through the upper data line of the first vertical synchronization section and the lower data line during the second vertical synchronization section. In other words, 30 screens are displayed in 1 second through the upper data line in the first vertical synchronization section, and 30 screens are implemented in 1 second through the lower data line in the second vertical synchronization section. One screen is completed through the data line at the bottom of the data line and the second vertical synchronization section.

Further, even data of R and B and odd data of G are applied through the upper data line, and odd data of R and B and even data of G are applied through the lower data line.

As described above, in the embodiment of the present invention, one screen is formed with one frame of data in the sequential manner. During the first vertical synchronization signal period, data is written and discharged through the upper data line, and the data is erased through the lower data line. During the second vertical synchronization signal period, data is written and discharged through the lower data line, and the data is erased through the upper data line, so that the upper data line and the second vertical signal during the first vertical synchronization signal period are One screen is implemented through the lower data line during the synchronization signal period, that is, data writing and discharging are performed by separating the upper data line and the lower data line. Therefore, since the discharge is formed by dividing the upper and lower data lines as described above, 30 perfect screens are displayed per second, thereby reducing power consumption without squeaking.

Claims (2)

In a PD system which converts a complex video signal of an interlaced television into a sequential method and displays it on a plasma display panel comprising a scan electrode, an address electrode and a sustain electrode, A data output process of loading data from the memory unit 31 in a sequential manner and temporarily storing the data in the data interface unit 32 and then outputting the data in a form required by the data driver 60; A vertical synchronous signal counting process of counting sequential data applied from the data output process to have 480 line information in one vertical synchronous section; The data interlacing method of a PDTV comprising a data interlacing process to implement a screen by dividing the data of the upper and the lower data during the two vertical synchronization periods counted by the vertical synchronization signal counting process. The method of claim 1, wherein the data interlacing process forms data writing and discharging through the upper data line during the first vertical synchronization period, and erases the data through the lower data line. During the second vertical synchronization section, data is erased through the upper data line and data writing and discharging is formed through the lower data line, so that the upper data line of the first vertical synchronization section and the lower data line of the second vertical synchronization section A data interlacing method of a PDTV, characterized in that one screen is formed by data writing and discharging.

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