KR19990027734U - PD TV power check - Google Patents

Abstract

The present invention relates to a power supply check device of a PDTV, and a device for checking a power supply state of a logic power supply unit for supplying a voltage required for driving a PDP system and protecting the system according to whether there is more or more. In the present invention, the power supply state of the logic power supply unit for supplying the DC voltage required to drive the PD system is converted into an 8-bit digital voltage value through the A / D conversion unit, and the microcomputer detecting it checks the digital voltage value. In the case of below the predetermined reference value which means the normal power supply state, by turning off the voltage of the high voltage driving circuit part through the power control port, the power check device of the PDTV television which automatically protects the system in case of power down and occurrence of abnormal voltage is proposed. have.

Description

PD TV power check

The present invention relates to a power supply check apparatus of a PDTV, and a device for checking a power supply state of a logic power supply unit for supplying a voltage required for driving a PDTV system and protecting the system according to the abnormality.

PD is generally driven by a continuous pulse with a constant voltage, and gradation display is implemented by digital rather than analog. However, since gas discharge usually requires a relatively high voltage of several hundred volts, the video signal is amplified and driven. The reason why the PD is suitable for the enlargement is that not only the process but also the characteristics useful for the enlargement of the gas discharge can be applied to the driving method.

The driving concept of PDPD is as follows. That is, the PD is an active light emitting display device in which ultraviolet rays generated from gas discharge excite a fluorescent film to implement an image. In other words, since the PDP uses ultraviolet light emitted by gas discharge as a light source corresponding to each pixel, the driving circuit simply functions to form or erase a gas discharge for each pixel in order to implement a display image. It consists of a video signal and signal control unit for each pixel constituting the image and a high-speed high-voltage switching control unit that can form or eliminate the ultraviolet rays generated from each pixel.

The driving operation of the PDTV system as described above is classified into three types of selecting operation, holding operation and erasing operation, and the selecting operation means driving operation necessary for initial discharge formation. In the case of the He + Xe and Ne + Xe penning mixtures which are generally used in the PDPD, a potential of 240 V to 280 V is applied. In the case of AC, when a third electrode is introduced, the sustain electrode and the dielectric in the discharge form The driving method of reducing the high current caused by the parasitic capacitor and separating the selection operation and the holding operation is adopted.

In addition, the above holding operation means a driving operation in which the discharge is maintained by a holding pulse having a lower voltage than the selection pulse by using the storage function characteristic of gas discharge. In the case of an AC PD, the storage function by wall charge In the case of direct current type PDPD, self-priming particle supply effect is used. In the case of the memory driving method which can separate the selection operation and the holding operation by using the memory function, the PDP can operate without losing the luminance even for a large display device in the case of high gradation display for realizing a high quality display device. It provides a driving method.

Subsequently, the erasing operation is an operation mode for discharging the discharge. In the case of a DC type PD, the voltage is simply lowered to a voltage below a discharge sustaining voltage. In the case of an AC type PD, a discharge is formed at a low voltage in a period of neutralizing the wall charge. The wall charges are removed by preventing the wall charges from being sufficiently formed or by applying an erasing pulse having a short pulse width to prevent the wall charges from reaching a steady state.

The PDP system driven as described above is provided with a logic power unit and a high voltage driving unit, and the logic power unit is configured to supply high voltage and other PDTV systems required to combine the electrode driving pulses with AC power as input. The DC voltage is generated and supplied, and the high voltage driving circuit unit generates the control pulse by combining the DC high voltage supplied from the logic power unit according to the logic level control pulse to drive the PD.

However, when the power of the logic power unit is down while the power is supplied to the PD system, the high voltage driving unit continues to be supplied with power, thereby destroying the system.

Accordingly, the present invention is to solve the above problems, and an object of the present invention is to provide an apparatus for protecting the system by controlling the supply of power in accordance with the presence or absence of power supply in the PDTV.

The technical idea of the invention required to achieve the object of the present invention is that the power supply state of the logic power unit is indicated by the digital value converted by the A / D conversion unit, the microcomputer detecting this is compared with the preset reference value If this occurs, it is assumed that the power of the high voltage drive circuit unit is turned off to maintain the stability of the system.

1 is an overall block diagram of a typical PDTV system.

2 is a block diagram showing a power supply check apparatus of the PDTV according to the present invention.

<Code Description of Main Parts of Drawing>

1: AV unit 2: ADC unit

3: memory section 4: data interface section

5: timing controller 6: address driver IC

7: Hold / Scan drive IC 8: High voltage drive circuit

9: AC / DC converter 10: microcomputer

80: composite video signal processor 90: digital data processor

100: PD drive part

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an overall configuration of a typical PDTV system.

Referring to FIG. 1, a composite video signal processing unit 80 including an AV unit 1 which analog-processes a composite video signal received through an antenna and provides an ADC unit, and samples the input analog composite video signal. ADC 2 for processing digital data, a memory unit 3 for rearranging the digital image data input from the composite image signal processing unit 80, and the rearranged digital image data to receive PDG grayscale processing. A digital data processing unit 90 comprising a data interface unit 4 for producing a data stream suitable for the present invention, and a timing controller unit 5 for generating and supplying a main clock for controlling the memory unit 3 and the entire system. An address driving IC 6 which receives a data stream from the data interface unit 4 and supplies data to the plasma panel for gradation processing; A PD driver 100 comprising a sustain / scan driver IC 7 and a high voltage driver circuit unit 8 and a logic power unit 9 for supplying a DC voltage to the PD driver 100.

The AV unit 1 receives an NTSC composite signal, separates the analog R, G, and B signals from the horizontal and vertical synchronization signals, obtains an APL (Average Picture Level) corresponding to the average value of the luminance signal Y, and then converts the ADC unit ( 2), the APL is used to improve the brightness of the PDTV system.

In addition, the NTSC composite video signal has an interlaced scanning method in which one frame is composed of two fields of Odd / Even, the horizontal synchronous signal is about 15.73KHZ, and the vertical synchronous signal is about 60Hz. The audio signal separated from the composite video signal is directly output to the speaker via an audio amplifier.

The ADC unit 2 receives analog R, G, and B signals as inputs, converts them into digital data, and outputs the digital data to the memory unit 3. The digital data is converted to improve the brightness of the PDTV system. The ADC unit 2 is composed of an amplifier unit, a clock generator, a sampling area setting unit, and a data mapping unit.

For reference, the operation of the amplification unit amplifies the analog R, G, B, and APL signals to a signal level suitable for quantization, and converts horizontal and vertical synchronization signals into a constant phase and outputs them. In addition, the clock generator must use a clock that is synchronized with the input synchronization signal. For this purpose, the clock generator generates a clock using phase locked loops (PLLs), and the PLL is output from the phase and loop of the input synchronization signal. Phase comparison pulse by dividing the output of the PD (Phase Detector) comparing the phase of the variable pulse, the LF (Loop Filter) outputting the control voltage of the Voltage Controlled Crystal Oscillator (VCXO), the VCXO oscillating by the control voltage, and the VCXO. It is composed of a PC (Programmble Counter) that outputs a clock, which outputs a clock synchronized with the input synchronization signal.

Here, if the clock synchronized with the input synchronization signal is not used, the vertical linearity of the displayed image is not guaranteed.

In addition, the sampling area set by the sampling area setting unit is set to a vertical position and a horizontal position, wherein the vertical position section is a pulse for setting only a line having image information among input signals, and a horizontal position section is a line set to a vertical position. Among the pulses for setting only the time in which the image information is, the vertical position section and the horizontal position section serve as a reference for sampling. In this case, a total of 480 lines are selected with 240 lines of Odd / Even fields. The horizontal position section should be a time at which at least 853 sampling clocks can exist for each selected line.

The data mapping unit of the ADC unit 2 maps the R, G, and B data output from the A / D converter into data corresponding to the brightness characteristics of the PDP. In other words, by arranging several vector tables in the ROM and selecting the optimal vector table according to the digitized APL data, the R, G, B, and R: The memory unit 3 is provided in the form of B data.

As described above, the memory unit 3 receiving data from the ADC unit 2 reconstructs image data of one field into a plurality of subfields for PDP gray level processing, and then, from the most significant bit (MSB) to the least significant bit (LSB) The reason for this is that the image data inputted by interlaced scanning is converted and displayed by progressive scanning so that an area for storing one frame of image data is required. Because.

In other words, two frame memories capable of storing one piece of image data (853 x 3 (RGB) x 480 x 8 Bits x 10 Mbit) are provided, and they alternately perform write and read operations in units of frames. The video data can be stored and displayed continuously. Furthermore, one field is divided into several subfields in the PD tone gradation process, and the image data corresponding to each subfield is read in sequence and provided to the data interface unit 4.

The data interface unit 4 temporarily stores the R, G, and B data from the memory unit 3 and provides the data in the form of data required by the address driver IC 6.

Referring to the case where the display size is 853 x 3 (R, G, B) x 480 mode in the above-described PDTV system, the data interface unit 4 has one line (853 x 3 = 2559). Bit data must be temporarily stored. Since data continuity must be guaranteed (input and output are performed at the same time), two lines (2559 × 2 = 5118 bits) of temporary storage are needed. That is, a total of 24 bits of data of 8 bits each of R, G, and B from the memory unit 3 are sequentially inputted (107 times) into the first temporary storage area (24 bits x 107 = 259 bits), and the same time interval As a result, the data of one previous line of the second temporary storage area is output in the form of a data stream required by the address driver IC 6, and such an input / output operation occurs alternately in the first and second temporary storage areas.

That is, after the first temporary storage area and the second temporary storage area operate in the input mode and the output mode, respectively, the reverse operation is then repeated.

In addition, when the data interface unit 4 temporarily outputs the temporarily stored image data to the address driver IC 6, the data interface unit 4 provides 1 bit of data and 48 bits of image data in a stream form to each driver IC. When data is input to the driver IC in turn (75 times) in this manner, when shifted in parallel, one line (48 bits x 75 = 3600 bits) of image data is all loaded into the address driver IC 6. Therefore, since the above process should be the same as the input mode operation time of the other temporary storage area, the input mode should be operated at twice the frequency of the output mode.

On the other hand, the high voltage driving circuit unit 8 combines the DC high voltage supplied from the logic power unit 9 in accordance with a control pulse of various logic levels output from the timing controller unit 5 to address, scan, and sustain drive ICs. The control pulse required in (7) is generated to enable the PDP to be driven, and the data stream provided from the data interface unit 4 to the address driver IC 6 is increased to an appropriate voltage level to selectively write to the panel. To be.

As described above, the driving method for the PD gradation process first divides one field (60 Hz) into several subfields (64 gradations: 6 subfields, 256 gradations: 8 subfields), and corresponds to each of the above subfields. Image data is written to the panel by line through the address driver IC 6, and the number of discharge sustain pulses is decreased in the order of LSB subfields in the subfield where MSB data is written, and the total discharge is maintained according to the combination thereof. It is common to perform gradation processing in a period, and the driving sequence of all the subfields repeats operations of full screen writing and erasing, data writing, and discharge holding (screen display).

In the logic power unit 9 connected to the PD drive unit 100, AC power (220 V, 60 Hz) is input as a high voltage required to combine the electrode driving pulses with each part of the other PD TV system. It generates and supplies the required DC voltage.

In this case, in order to protect the system when the logic power unit 9 is powered down, it is necessary to turn off the power remaining in the high voltage driving circuit unit 8, and to check the power state of the logic power unit 9 for this purpose. It must be accompanied. This will be described with reference to FIG. 2.

2 is a block diagram showing a power supply check apparatus of the PDTV according to the present invention, the logic power unit 9 is connected to the A / D conversion unit 10, the A / D conversion unit 10 is a logic The analog DC voltage of the 0-5V output from the power unit 9 is converted into an 8-bit digital value, and when converted into the 8-bit digital value, the digital voltage corresponding to 0V is a digital voltage corresponding to 0V to 5V. The voltage range up to the value 255 can be indicated.

After the microcomputer 11 connected to the A / D converter 10 is supplied with power to the logic power unit 9, whether the digital data value of the voltage output from the logic power unit 9 varies. When the digital value below the preset reference value, which indicates the normal power supply state, is detected, the power of the high voltage driving circuit unit 8 is turned off through a power control port (not shown) formed in itself.

Therefore, the detection of the digital value below the reference value as described above means that the power supply of the logic power unit 9 is abnormal, including when the power of the logic power unit 9 is turned off, and the high voltage is generated by the microcomputer 11. By turning off the power supply of the drive circuit part 8, the system is safely protected.

As described above, the present invention converts the power supply state of the logic power unit supplying the DC voltage necessary for driving the PD system to an 8-bit digital voltage value, and the microcomputer checks this to supply a normal power supply. When the reference value is equal to or less than a predetermined reference value, the microcomputer turns off the voltage of the high voltage driving circuit unit through the control port, thereby effectively protecting the system in the event of a power down and an abnormal voltage.

Claims (2)

In the device for checking the power supply abnormality of the PD system, A / D conversion means for converting the DC voltage supplied to the PD system to a digital value, Control means for controlling the power supply according to the digital value converted by the A / D conversion means, and And a high voltage driving means for generating a control pulse required for driving a PD in accordance with the control of the control means. The method of claim 1, wherein the control means checks the digital value converted by the A / D conversion means, if the checked digital value is less than the normal power supply, characterized in that the high voltage driving means is turned off. Power supply check of PDTV.