JP2001268527A - Picture signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently obtain picture signals of plural formats. SOLUTION: Picture data are read out from a frame memory 10 in the unit of line and picture data for the required number of lines are stored in a line memory 12. Data read out from the line memory 12 are converted into the desired number of lines by a vertical filter 14 and converted into the desired number of pixels through a horizontal filter 16. In this case, the reading of data from the memory 12 and processing in the filters 14, 16 are executed in time division so as to correspond to plural kinds of format conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus for obtaining image signals of a plurality of formats.

[0002]

2. Description of the Related Art In a digital television (TV) system, image signals of various vertical and horizontal sizes are handled. The operation method includes an interlace method (jump operation method) and a progressive method (sequential operation method).
There are two types. Therefore, the digital TV has to handle image signals of various formats.

[0003] In summary, there are image format types as shown in Table 1.

[0004]

[Table 1] On the other hand, the received signal is a signal encoded by MPEG or the like, and image data is obtained by decoding the signal.
This is stored in the frame memory. Then, the image data stored in the frame memory is read out, converted into a signal for driving the display, supplied to the display, and displayed here.

[0005] Here, the display differs in the television set, and various displays are used. Therefore, if the format of the received image signal is different from the format required by the display, the format must be converted.

For example, if the TV is 1080i (1920 × 1)
080, Interlace) HDTV (HDT)
In the case of V), the received original image signal may be 1080i, but if it is different, format conversion needs to be performed.

Further, there is also a case where a video is recorded on a video tape recorder (VTR) at the same time as being displayed on a TV. For a home VTR, the image format is currently 4
80i (720 × 480, interlace) is employed. Therefore, when recording on a VTR while displaying an image on a high-definition TV, both the 1080i image signal and the 480i image signal must be output simultaneously.

Further, in a high-definition television or the like, the screen may be divided or a region for character information may be provided in a part of the screen. For this reason, in order to display the image on a TV, a function of converting the format of the received image signal at an arbitrary conversion magnification is required.

As described above, a function of outputting image signals of a plurality of formats is required in a digital TV.

Therefore, a required number of circuits for reading image data from a frame memory for storing one frame of image data and performing format conversion processing are provided, and the required number of format-converted image signals are separately processed. Was getting.

[0011]

As described above, the conventional circuit requires two or more format conversion circuits, so that the circuit scale becomes large. Further, since each format conversion circuit accesses the frame memory independently, the frequency of access to the frame memory increases. MPEG decoded image data is written in the frame memory. However, in the case of MPEG decoding, it is necessary to read the already decoded data, and the frequency of accessing the frame memory is high. Therefore, a high responsiveness to access is required in the frame memory, which causes a problem that the cost of the memory increases.

The present invention has been made in view of the above problems, and has as its object to provide an image signal processing circuit that can efficiently generate image signals of a plurality of formats.

[0013]

According to the present invention, there is provided a frame memory for storing a digital image for each frame, a line memory for storing a plurality of lines of data read from the frame memory, and a line memory for storing the data. Format conversion means for reading out the stored data and outputting image signals of a plurality of types of formats.

As described above, according to the present invention, image signals in a plurality of formats are generated from data read from one line memory. Therefore, the frequency of reading from the frame memory to the line memory can be reduced.
Further, since only one line memory is required, the circuit scale can be reduced.

It is preferable that the format conversion means generates image signals in a plurality of formats in a time-division manner. As described above, by performing the format conversion processing in a time-division manner, only one format conversion unit is required, and the circuit scale can be reduced.

[0016]

Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

The image data that has undergone the MPEG decoding processing is
It is stored in the frame memory 10. Here, in the case of MPEG decoding, in order to use the image data of a plurality of frames at the time of decoding, the frame memory 10 stores the decoded image data of a plurality of frames.

The image data read from the frame memory 10 is supplied to a line memory 12. Here, the number of lines required for format conversion differs depending on the enlargement / reduction ratio and the method. That is, the more the number of lines is, the better the image can be obtained. Therefore,
The line memory 12 is set to have a size capable of storing image data of the number of lines (horizontal lines) required for format conversion. For example, when performing a 1/4 reduction, usually 4 lines of data are required. The line memory 12 stores the image data of the next required line on the image data of the unnecessary line.

The image data from the line memory 12 is supplied to a vertical filter 14. The vertical filter 14 performs filtering in the vertical direction. For example, if the reduction is 縮小, the vertical filter 14 performs processing so that the number of lines becomes １ ／. In this 縮小 reduction process, for example, data for two lines may be averaged and data for one line may be sequentially generated. However, data for three or more lines is used to generate data for one line. Performing the weighted averaging operation is preferable because higher image quality can be obtained. Also, in the case of enlargement, it is preferable not to simply perform interpolation from data of upper and lower lines, but to perform interpolation from data of more lines.

The output from the vertical filter 14 is
It is supplied to a horizontal filter 16. This horizontal filter 16
Changes the number of data (the number of pixels) in one line of the data output from the vertical filter 14. That is, in the output from the vertical filter, since the number of data in the horizontal direction is not changed, the number of data is increased or decreased to a desired number by calculation.

In the above configuration, format conversion is performed separately in the vertical direction and the horizontal direction, so that the correlation in the oblique direction is not considered. Vertical filter 14 and horizontal filter 1
6 may be combined to create and output data of the required number of vertical lines and horizontal data from image data of a block of a predetermined size. Thereby, the correlation in the oblique direction can be considered.

Here, output of data from the line memory 12 and processing by the vertical filter 14 and the horizontal filter 16 are controlled by the controller 18.

The output of the horizontal filter 16 is output via the switch 20. Here, this switch 20
Has two types of outputs, a main output and a sub output, and outputs the output of the horizontal filter 16 as a main or sub output in a time-division manner. This switch 20 is also connected to the controller 18.
Is controlled by Note that a format conversion circuit 22 is configured by the line memory 12, the vertical filter 14, the horizontal filter 16, and the controller 18.

The main output and the sub output are provided to OSD (on-screen display) frame memories 24 and 26 provided for displaying characters and the like.
Is written to. Note that the output data storage memory may be used instead of the OSD frame memories 24 and 26.

The line memory 12 and the vertical filter 1
4, horizontal filter 16, controller 18, switch 2
0 forms a format conversion circuit.

Next, the operation will be described. Here, in order to simplify the explanation, the number of lines of the original image stored in the frame memory 10 is doubled to obtain a main output, and
And obtain a sub-output. It is also assumed that the horizontal filter 16 outputs as it is.

For example, the line memory 12 stores two lines of data. When new data for one line is written, the controller 18 sends the new one-line signal and the previous one-line signal to the vertical filter. The vertical filter 14 creates intermediate line data from the two lines of signals by interpolation, and sequentially outputs the data of the previous line and the created data of the intermediate line. As a result, the data of one line is supplied to the vertical filter 14 twice from the line memory 12,
A new two-line signal is output from the vertical filter 14, and the number of lines is doubled. At this time, the switch 20 has selected the main output side under the control of the controller 18. Thus, an image signal having twice the number of lines as the original image is obtained in the main output.

On the other hand, when this operation is performed twice, the data stored at that time for two lines is supplied to the vertical filter 14 again. At this time, the mode for the sub output of the vertical filter 14 is switched by the controller 18. Then, by interpolating the supplied two lines of data, one line of data is
6 is output. This allows 1 input for 2 lines of input.
A line output is obtained. At this time, the controller 18
As a result, the sub output is selected by the switch 20, and an image signal having a half number of lines of the original image is obtained as the sub output.

In this way, as shown in FIG. 2, the sub output is output once for every two main outputs from the switch 20, and these are output in a time division manner. Therefore, the line memory 12, the vertical filter 14, the horizontal filter 16
And the circuit scale can be reduced. Further, since the data read from the frame memory 10 is used for generating image signals of two types of formats, the frequency of access to the frame memory can be reduced.

Here, as for the output from the switch 20, the main output and the sub output are performed in a time sharing manner. Therefore, the output from the switch 20 is not synchronized with the synchronization signal of the display or the like. However, in digital TV, OSD
(On-screen display) also performs normal character display. In this case, a TV set, a VTR and the like have OSD frame memories 24 and 26 for superimposing character display on image display. And this OS
The image data is read from the D frame memories 24 and 26 in accordance with the display timing of the display, and is displayed.

Therefore, even if the image data obtained at the main output and the sub-output is sent in a time-division manner without being synchronized with the display or the like, the image data is temporarily stored in the OSD frame memories 24 and 26 so that the timing of the display can be read from here. Can read the image data without any problem.

As described above, according to the present embodiment, the main output and the sub output are obtained by using the line memory 12, the vertical filter 14, and the horizontal filter 16 in a time division manner. Therefore, the reading of data from the frame memory 10 to the line memory 12 may be performed only once for two outputs. Further, one line memory 12, one vertical filter 14, and one horizontal filter 16 may be used. Therefore, the frequency of access to the frame memory can be reduced, and the circuit scale can be reduced to perform efficient processing.

[0033]

As described above, according to the present invention,
Image signals of a plurality of formats are generated from data read from one line memory. Therefore, the frequency of reading from the frame memory to the line memory can be reduced.

Further, by performing format conversion processing in a time-sharing manner, even when converting to a plurality of formats,
Since only one format conversion circuit is required, the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an apparatus according to an embodiment.

FIG. 2 is a diagram showing processing timing.

[Explanation of symbols]

10 frame memory, 12 line memory, 14 vertical filter, 16 horizontal filter, 18 controller, 20 switch, 22 format conversion circuit, 2
Frame memory for 4,26 OSD.

Claims (2)

[Claims] 1. A frame memory for storing a digital image for each frame, a line memory for storing a plurality of lines of data read from the frame memory, and a data stored in the line memory,
An image signal processing apparatus comprising: a format conversion unit that outputs image signals of a plurality of types of formats. 2. The image signal processing apparatus according to claim 1, wherein said format conversion means generates image signals in a plurality of types of formats in a time-division manner.