JPS62241059A - Data buffer circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of data writing by selecting the number of words with which a main processor writes sequentially data on a memory circuit and a part of the address designated directly and using them as the write addresses on the memory circuit. CONSTITUTION:When it is designated that a high-order address signal 100-H writes data sequentially, a decoder circuit 4 defines a genuine write address selection signal 400 and writes it on the address of a memory circuit 6 indicated by a count value held by a counter circuit 5. If it is not designated to write data sequentially via the signal 100-H, a writing action is carried out on the address of the circuit 6 indicated by a low-order address signal 100-L. A read designating address signal 200 of an additional processor 20 designates the read address of the circuit 6. A read designating signal 201 is given to the circuit 6 as a read strobe signal and the read data output signal 500 of the circuit 6 is applied to the processor 2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data buffer circuit, and in particular, in data transfer from a main processor to an additional processor, data writing is performed sequentially and data is written directly by the main processor. The present invention relates to a data buffer circuit for writing data by specifying an address within the data buffer.

[Conventional technology]

Conventionally, this type of data buffer circuit has been used in cases where it is possible to write data sequentially when passing data from the main processor to an attached processor, and when the main processor directly specifies a memory address within the data buffer. There were cases where it was possible to write data, but only the former or the latter was possible.

[Problem that the invention seeks to solve]

When using the conventional data buffer circuit that can write data sequentially as described above, the seed process
When passing data that is out of order from the source to the additional processor, the data must be rearranged on the main processor side in advance and then the data must be written sequentially.
When using the conventional data buffer circuit described above in which the main processor can write data by directly specifying a memory address within the data buffer, the main processor is aligned from the main processor to the additional processor. When data is transferred sequentially, the main processor must write data while sequentially changing the memory address in the data buffer, and in either case, the processing time of the main processor increases, etc. There is.

[Means for solving problems]

The data buffer circuit of the present invention is an information processing apparatus having a main processor and an additional processor, and includes a storage means having a plurality of words, and a data buffer circuit that stores the number of words that the main processor sequentially writes data to the storage means. A counting means for counting, a value held by the counting means, and a write address of the storage means by selecting part of the address when the main processor directly specifies the address of the storage means to write data. and a decoder means for supplying a part of the address when the additional processor reads data from the storage means to the read address of the storage means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, this embodiment is an information processing apparatus having a main processor 1, an additional processor 2, and a memory circuit 6, in which the main processor can output an address signal 100, a write instruction signal 101, and a data signal 102. , the additional processor 2 is configured to be able to output a read designation address signal 200 and a read signal 201, and the main processor 1
It has a data buffer circuit for writing data by specifying .

Address signal 100 from main processor 1 is divided into lower address signal 100-L and upper address signal 100-H, and lower address signal 100-L is applied to one selected signal input of selection circuit 3. Upper address signal 1
00-H is given to the decoder circuit 4. When the upper address signal 100-H specifies sequential data writing, the decoder circuit 4 sets the write address selection signal 400 to true. Write address selection signal 400 is applied to the control input of selection circuit 3. Write address selection signal 400 is applied to the clock input of counting circuit 5.

The counting circuit 5 increases the count value when the write address selection signal 400 changes from true to false, that is, when the upper address signal 100H cancels the designation of sequential data writing. The counting circuit 5 is a 0 selection circuit 3 which outputs the count value signal 500 to the other selection signal input of the selection circuit 2.
selects the count value signal 500 and outputs the write address signal 300 when the write address signal 400 is true, that is, when the upper address signal 100-H specifies that data is written sequentially. Output to. Write address signal 30
0 specifies the write address of the memory circuit 6. Data signal 102 is applied to the write data input of memory circuit 6. Write instruction signal 101 is applied to memory circuit 6 as a write strobe.

If the upper address signal 100-H specifies that data be written sequentially, the data is written to the address of the memory circuit 6 indicated by the count held by the counting circuit 5.

If the upper address signal 100-H does not specify that data be written sequentially, the lower address signal 100-H
Writing is performed to the address of the memory circuit 6 indicated by -L.

The read designation address signal 200 of the additional processor 2 specifies the read address of the memory circuit 6. Read designation signal 20
1 is given to the memory circuit 6 as a read strobe.

The read data output signal 500 of memory circuit 6 is provided to the additional processor.

[Effects of the Invention] As explained above, the present invention selects the number of words in which the main processor sequentially writes data to the memory circuit and a part of the address of the memory circuit directly designated by the main processor. By using this address as a write address to the memory circuit, the main processor can efficiently write data both sequentially and when directly addressing the memory circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Main processor, 2... Additional processor, 3.
... selection circuit, 4 ... decoder circuit, 5 ... counting circuit, 6 ... memory circuit.

Claims (1)

[Scope of Claim] An information processing device having a main processor and an additional processor, comprising: a storage means having a plurality of words; and a method for counting the number of words sequentially written data to the storage means by the main processor. Selecting a counting means, a value held by the counting means, and a part of the address when the main processor directly specifies the address of the storage means to write data, and writing to the write address of the storage means. and a decoder means for supplying a part of an address when an additional processor reads data from the storage means to a read address of the storage means.