JPS6184746A - Tracer memory data recording circuit - Google Patents

Tracer memory data recording circuit

Info

Publication number
JPS6184746A
JPS6184746A JP59206860A JP20686084A JPS6184746A JP S6184746 A JPS6184746 A JP S6184746A JP 59206860 A JP59206860 A JP 59206860A JP 20686084 A JP20686084 A JP 20686084A JP S6184746 A JPS6184746 A JP S6184746A
Authority
JP
Japan
Prior art keywords
inputted
data
register
comparator
tracer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59206860A
Other languages
Japanese (ja)
Inventor
Takeo Kakuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59206860A priority Critical patent/JPS6184746A/en
Publication of JPS6184746A publication Critical patent/JPS6184746A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it unnecessary to record all data to use a memory effectively by providing a means which counts and records the number of the same trace data which are inputted to a tracer memory continuously.
CONSTITUTION: Input trace data S1 is inputted to an input buffer register 11 and a trace data comparator 12. An output signal S2 of the register 11 is inputted to the comparator 12 and a tracer memory 13. A data coincidence output signal S3 of the comparator 12 is inputted to a counter 14, and it is counted only when the same trace data are inputted continuously. The output continuous data number of the counter 14 is inputted to a register 16 for the purpose of recording the counted sum total. The tracer memory 13 and the register 16 are addressed successively by an output address signal S7 and an enable signal S8 of a control circuit 15 to record data.
COPYRIGHT: (C)1986,JPO&Japio
JP59206860A 1984-10-01 1984-10-01 Tracer memory data recording circuit Pending JPS6184746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59206860A JPS6184746A (en) 1984-10-01 1984-10-01 Tracer memory data recording circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59206860A JPS6184746A (en) 1984-10-01 1984-10-01 Tracer memory data recording circuit

Publications (1)

Publication Number Publication Date
JPS6184746A true JPS6184746A (en) 1986-04-30

Family

ID=16530238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59206860A Pending JPS6184746A (en) 1984-10-01 1984-10-01 Tracer memory data recording circuit

Country Status (1)

Country Link
JP (1) JPS6184746A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244235A (en) * 1989-03-17 1990-09-28 Nec Corp Tracer device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244235A (en) * 1989-03-17 1990-09-28 Nec Corp Tracer device

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