JPS59138894U - dot display device - Google Patents
dot display deviceInfo
- Publication number
- JPS59138894U JPS59138894U JP3316683U JP3316683U JPS59138894U JP S59138894 U JPS59138894 U JP S59138894U JP 3316683 U JP3316683 U JP 3316683U JP 3316683 U JP3316683 U JP 3316683U JP S59138894 U JPS59138894 U JP S59138894U
- Authority
- JP
- Japan
- Prior art keywords
- memory address
- signal
- dot display
- dot
- display section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Computer Display Output (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の二実施例の外観正面−≠ある。第２
図はこの考案の一実施例の構成ブロック図である。第３
１図は、第２図めブロックの動作を −゛−説明するた
めのフロー図である。 −−図において、１はドツ
ト表示装置、２はドツト表示部、３はキーボード、７は
制御回路、８はメモリ、１０は反転回路、２１は表示手
段（ドラ））、３１はテンキーを示す。
し然ツ叶−一一FIG. 1 shows a front view of two embodiments of this invention. Second
The figure is a block diagram of an embodiment of this invention. Third
FIG. 1 is a flow diagram for explaining the operation of the block in FIG. 2. --In the figure, 1 is a dot display device, 2 is a dot display section, 3 is a keyboard, 7 is a control circuit, 8 is a memory, 10 is an inversion circuit, 21 is a display means (drag), and 31 is a numeric keypad. Shizentsu Kano - Kazuichi
Claims (3)
表示手段群によって構成されるドツト表示部と、該表示
部に与えられる信号を記憶する手段と、その記憶手段か
ら信号を読出し、−前記ドツト表示部に与える側御手段
とを含むドツト表糸装置において、 。 前記記憶手段は、前記各表示手段群に対応するメモリア
ドレスを有し、該アドレスには前記−−−２値信号のい
ずれかが記憶されていて、さらに、前記メモリアドレス
を指定する手段と、 層 該指定手段によって指定されたメモリアドレスに記
憶された２値信号を反転させる手段とを含む、ドツト表
糸装置。−。(1) A dot display section composed of a group of display means that takes one of two stable states in response to an i-value signal, means for storing the signal given to the display section, and reading the signal from the storage means. , - a side control means for applying the dot display section to the dot surface yarn device. The storage means has a memory address corresponding to each of the display means groups, and one of the binary signals is stored in the address, and means for specifying the memory address; layer: means for inverting a binary signal stored at a memory address specified by the specifying means. −.
、実用新案登録請求あ範囲第１項記載のドツト表示装置
。(2) The dot display device according to claim 1, wherein the memory address designating means is a numeric keypad.
アドレスに記憶された２値信号を読出す手段と、 前記読出された信号の状態を反転する手段と、−前記読
出したメモリアドレスに、該反転後の信号を書込む手段
とからなる、実用新案登録請求の範囲第１項または第２
項記職安ドツト表示 −装置。(3) The binary signal inversion means includes means for reading out the binary signal stored in the specified memory address, means for inverting the state of the read signal, and - the read memory address. and a means for writing the inverted signal into the utility model registration claim 1 or 2.
Item Employment Security Dot Display - Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3316683U JPS59138894U (en) | 1983-03-07 | 1983-03-07 | dot display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3316683U JPS59138894U (en) | 1983-03-07 | 1983-03-07 | dot display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59138894U true JPS59138894U (en) | 1984-09-17 |
Family
ID=30163969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3316683U Pending JPS59138894U (en) | 1983-03-07 | 1983-03-07 | dot display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59138894U (en) |
-
1983
- 1983-03-07 JP JP3316683U patent/JPS59138894U/en active Pending
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