JPS60232595A - Memory address circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character signal generating device such as a printing device or a display device used as an output device of an information processing system, and particularly to a memory address circuit of a character signal generating device based on a character pattern. It is something.

Figure 1 shows an example of an address circuit in a conventional character signal generating device of this kind. Each time the 0PU1f central processing unit (0PU1f central processing unit) writes data to the memory 3 (in case C or when reading data), (or each time data is read). Therefore, for example, when writing or reading one character, opυ1 needs to be calculated by 1° to specify addresses several to hundreds of times, which takes a lot of time for characters with a large number of strokes. There was a drawback.

Since it is not desirable for @OPU to do something like this, the present inventors and others have conducted various researches and found that an address for reading or writing from memory can be generated in place of OPH without requiring a large amount of time. I have completed a circuit that can do this, so I would like to offer it here.

That is, the present invention includes an up/down counter circuit and a circuit for controlling the up/down circuit, and when an address for reading or writing from a memory is given from the CPU to the up/down counter circuit. , each time data is read out, the next address is generated by counting up or down L7.

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, where 1 and 3 are the same CPU and memory as the conventional circuit shown in FIG. 1, and 4 is a memory address circuit according to the present invention.

The and - memory address circuit 4 is composed of an up/down counter circuit 4t1 and an up/down control # circuit 4b.

Next, the operation will be explained. First, 0PU1 sets the start address C or end address) to the counter 4, and then 0PUI sets the up/down control circuit 4.
b Set on the hair turn or down instruction signal Bi.

Here, when 0PUI reads data to the memory 3, the up/down control circuit 4b operates, and the up/down control circuit 4b performs a shift by sending the up/down counter circuit 4a hairturn or down count basic signal 0. - The down counter circuit 4a creates and sends the next required address D'ft.

As explained above, the present invention has the advantage that it can be put into practical use simply by adding the address counter circuit 4 that counts up or down the address, and is industrially suitable as a method for generating all address signals. It is something.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional device, and FIG. 2 is a block diagram of an embodiment of the present invention. 1... oPtr, 2... Register, 3... Memory, 4... Address counter circuit, 4a... Up.
Down circuit, 4b...up/down control circuit. Patent applicant: NEC Corporation

Claims (1)

[Claims] Up/down counter circuit and its up/down control circuit? and the up/down counter circuit is (
A memory address circuit that generates the next address by counting up or down every time a read or write is performed according to an instruction from an IPU.