JPS62293289A - Character pattern generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a character pattern generation circuit used in an information processing system, such as a driver/matrix printer.

[Conventional technology]

In the character pattern generation circuit used in the conventional dot matrix printer, the character pattern is
A common method is to construct a dot matrix of n and store this mXn bit information in a character pattern storage circuit. However, when handling Japanese, an enormous amount of memory capacity is required for the character pattern storage circuit.

[Problems to be solved by the invention] Since the capacity of this character pattern storage memory becomes enormous,
There is a problem that the equipment is expensive. This may be due to the huge number of Japanese characters, or it may be due to the fact that when looking at each character pattern as row or column data, the same pattern data is memorized as completely different patterns. It is the cause.

The object of the present invention is to
X n dot matrix data to m bits or n
The object of the present invention is to reduce the required capacity of a character pattern storage memory and provide an inexpensive character pattern generation circuit by storing data as a combination of bits.

[Means for solving problems]

The character pattern generation circuit of the present invention converts a character pattern consisting of an m×n dot matrix into a data set of one dot line in the row direction or column direction and stores the start address corresponding to each character code of this character pattern. The table and the row pattern address of each row of one character are continuously output in correspondence with the read address of this code conversion table, and this row pattern address is set as control bits of the 8-bit data width, with the most significant bits 1 to 7 as control bits. A row pattern address memory that stores 7XF bits in units of bits, a row pattern address register that reads each row pattern address data from this row pattern address memory and temporarily holds it as a row pattern address, It is characterized by comprising a row pattern memory in which a character pattern is read out and n bits or m bits are stored as one word in descending order of frequency of use, starting from the lowest address.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an entire embodiment of the present invention;
FIG. 2 is a block diagram of an example of the row address register circuit 4 of FIG. 1, and FIG. 3 is a block diagram showing details of the timing control circuit 6 of FIG. 1. In the figure, 1 is a code conversion table, 2 is an address counter, 3 is a row pattern address memory, 4 is a row pattern address register circuit, and 5 is a row pattern address register circuit.
is a row pattern memory, 6 is a timing control circuit, 7 to 1
0 is a register, 11.14 is a flip-flop, 12 is a clock generation circuit, 13 is an AND circuit, 15
is a reset signal generation circuit, ]6 is a line counter.

When reading a character pattern, a character code a indicating the character pattern to be read and a read start signal are given. Given this character code a, code conversion table 1
The corresponding address of the row pattern address storage memory 3 is outputted and stored in the address counter 2 at the rise of the read signal S, which is a negative logic signal. On the other hand, the flip-flop 11 in the timing control circuit 6 is also turned ON at the rising edge of the read start signal S, so that it becomes continuous mode, and the clock generation circuit 12 starts generating the clock signal C.

The row pattern address storage memory 3 outputs 8-bit data in response to the output of the address counter 2.
Among these, the lower 7 bits are stored in the register 7 of the row pattern address register circuit 4 at the rising edge of the clock signal C. On the other hand, the L-most bit of the output of the row pattern address storage memory 3 is a row pattern address control signal e which indicates that the address continues when it is "0" and indicates the end of the address when it is "1". The data is stored in the second flip-flop 14 at the rising edge of the clock signal C.

Further, at the rising edge of the clock signal C, the contents of the address counter 2 increase by rl. This flip-flop 14 is
O'', the clock signal C does not stop, so the data read from the row pattern address storage memory is stored in the register 7 in the row pattern address register circuit 4, and at the same time, the previous contents of this register 7 are stored in the register 8.
is memorized. At this time, the row pattern address control signal e
is also stored in flip-flop 14. When the content stored in the flip-flop 14 is "1", one of the AND circuits 13 in FIG. 3 becomes "0", the clock signal C stops, and the reset signal generating circuit 15 starts operating. This reset signal generation circuit 6 and circuit 15 are configured as a counter, and the number of circuits 17 and 15 is 1.
A reset signal is generated at a fixed time of Δ, the flip-flop 14 is reset, and the n of this flip-flop 14 is
Externally output as a signal to logic output or row pattern output JJ
The output take of the row pattern storage memory 5 is read by an external circuit.

On the other hand, the row address register circuit 4 is reset by the reset signal (.), and at the same time, the line counter 16 in FIG. 3 is incremented by "1".

The above operations 1- are repeated, and the row pattern takes g are successively read out until the read end signal j is generated from the line counter 16. When the read end signal i is output from the line counter 16, the flip-flop 11 is reset and the read operation for one character is completed.

1. Effects of the Invention] As explained above, according to the present invention, character patterns are stored in the line pattern storage memory 5 in order of frequency of use by focusing on line data, and one character pattern is stored in the line pattern as a combination of line pattern addresses. By storing the pattern address in the address storage circuit 3 and configuring the row pattern address register circuit 4 as a shift register in units of 7 bits,
The memory capacity required for the character pattern generation circuit can be reduced, and an inexpensive character pattern generation circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Detailed block diagram of row address register circuit 4 in Figure 3.
FIG. 1 is a detailed block diagram of the timing control circuit 6 shown in FIG.

Claims (1)

[Claims] A code conversion table that stores a character pattern consisting of an m×n dot matrix as a set of one-dot line data in the row or column direction, and the start address corresponding to each character code of this character pattern; Continuously outputs the row pattern address of each row of one character in response to the read address, and stores this row pattern address in 7×l bits with the most significant bit of the 8-bit data width as the control bit and the lower 7 bits as a unit. a row pattern address memory for reading each row pattern address data from the row pattern address memory and temporarily holding it as a row pattern address; and a row pattern address register for reading each row pattern address data from the row pattern address memory and temporarily holding it as a row pattern address; 1. A character pattern generation circuit comprising a row pattern memory storing m bits as one word in order of frequency of use starting from the lowest address.