JPS6134588A - Image memory control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an image storage control circuit used in an image processing apparatus.

(Prior art) Usually, a memory circuit has a readout mode,
There are three operating modes: write mode and read-then-write mode. When using this memory circuit as an image memory, "0" is written to all image memories only when initializing so that images can be superimposed, and when writing actual image data, the read-then-write mode is used. using,
A method of writing the logical sum of write data and read data is adopted.

Conventionally, when writing image data to an image memory, it is necessary to write all data regardless of the content of the data to be written, so even if the image data is white (0) t-keynote, all image data is The disadvantage is that it takes time to write the data.

For example, when memorizing a 32x32 dot character pattern, it is necessary to memorize all 32x32 dots, even though most of the characters are white in the case of simple characters such as "r-J, r2". Ta.

(Object of the Invention) An object of the present invention is to eliminate such drawbacks and reduce the time required to write image data by providing an operation mode that bypasses writing to the image memory when the content of the write data is "0". It is an object of the present invention to provide an image storage control circuit that can be shortened.

(Configuration of the Invention) The configuration of the image storage control circuit of the present invention includes a rewritable storage circuit, an address register that temporarily stores an address to the storage circuit, and a lead that temporarily stores output data read from the storage circuit. a data register; a write data register that temporarily stores input data to be written into the memory circuit; and a write data register that outputs the logical sum of the output of the read data register and the output of the write data register when the operation mode is the logical sum mode; an OR circuit that outputs the output of the write data register when the operation mode is not the OR mode; and a zero detection circuit that generates a zero detection signal when a predetermined number of bits of the contents of the write data register are all "0". , generates a control signal for writing the output of the OR circuit into the storage circuit in response to a memory access request, if the zero detection signal is not output, and if the zero detection signal is output, generates the control signal. and a timing control circuit that outputs an access end signal without generating an access end signal, and bypasses writing to the storage circuit when the write data is "0".

(Example) Next, the present invention will be explained in detail using the drawings.

Figure 1 shows an image storage control circuit according to an embodiment of the present invention! FIG. In this embodiment, the memory circuit 1. Address register 2. Write data register 3. Read data register 4. OR circuit 51 "0" detection circuit 6. It is composed of a timing control circuit 7. Figure 2 1al~(j
1 is an operation time chart when the write data of this embodiment is not "0", and FIGS. 3 1a) to 1(f) are operation time charts when the write data is "0". Note that this operation is explained using negative logic.

Next, the operation when the write data is not "0" will be explained with reference to FIG. The operating mode at this time is input terminal 1.
The signal from input terminal 13 is the write-after-read mode, and the "0" detectable signal from the input terminal 13 is "1", which is the "0" detectable mode. First, when writing image data to the image storage control circuit, the address from the input terminal 11 (see FIG. 2(a)
) is set in the address register 2, and the write data from the input terminal 12 (FIG. 2(b)) is set in the write data register 3, and then the access request signal from the input terminal 16 (FIG. 2(b)) is set in the write data register 3. (C1) is given. Since the data set in the write data register 3 is not "0", the "0" detection circuit 6 does not generate a "0" detection signal (FIG. 2(d)). The access request signal tel is a negative logic pulse signal that activates the timing control circuit 7 at its rising edge.Since the timing control circuit 7 does not generate the "0" detection signal (d), it sends the memory access signal to the storage circuit 1. (Fig. 2(e)) 'e is output small. At this time, the access mode to the memory circuit 1 is the read mode.Subsequently, the timing control circuit 7 outputs a negative logic first gate signal (Fig. 2(e)). f > ) is generated, and the previous data of the write address is output as a read signal (FIG. 2 (i)). This read signal is sent to the read data register 4 at the rising edge of the first gate signal (f). The contents are sent to the OR circuit 5.

On the other hand, from the outside 4. When the determined operation mode is the write-after-read mode, the operation mode of the OR circuit 5 is the OR mode. After the first gate signal 1f) rises, a negative logic second gate signal (gl) is generated, and the OR circuit 5 reads out the write data stored in the write data register 3 and the read data from the storage circuit 1. Data that is the logical sum of the previous data of the memory circuit 1 stored in the register 4 is output.Following the second gate signal, a write signal (FIG. 2 (h)) is generated from the timing control circuit 7. , the data (FIG. 2 (i)) which is the logical sum of the write data and the previous data of the memory circuit 1 is written into the memory circuit IK again. When the writing to the memory circuit 1 is completed, a negative logic memory access signal is generated. (FIG. 2(e)) is the stand-up access end signal (FIG. 2(c)) is output to the outside.

Next, the operation when the write data is "0" will be explained using FIGS. 1 and 3. The operation mode at this time is the read-after-write mode, and the rOJ detection mode. Also, before the access request signal (FIG. 3(C)) is given, the write address (FIG. 3(a)) is stored in the address register 2, and the write data (FIG. 3(b)) is stored in the write data register 3. It is set. Since the content of this write data register 3 is "0", the "0" detection circuit 5 outputs a "0" detection signal (FIG. 3(d)), and this "0" detection signal is transmitted to the timing control circuit. 7 is connected. Negative logic access request signal (Figure 3 (C))
is applied from the outside (input terminal 16), the timing control circuit 7 is activated at the rising edge of the access request signal, but by the time this access request signal rises, the “0” detection signal (see FIG. 3) is already activated.
d)) has occurred and the operation mode of the timing control circuit 7 has changed, so the memory access signal to the storage circuit 1 (FIG. 3(e)), the first gate signal, the second gate signal, and the write No signal is generated, and a write end signal (see Figure 3) is immediately output to the outside.

As an example of this embodiment, when a character pattern of 32×32 dots is to be stored, input data is temporarily stored in the write data register (3) every 8 or 16 bits. In the case of a simple character such as an 8-bit or 16-bit input to this register where all bits are "0", the memory circuit can be used effectively by bypassing this white information without storing it in the memory circuit. Moreover, the writing time can also be shortened.

(Effects of the Invention) As explained above, in the present invention, a means for detecting that write data is "0" is provided, and when the operation mode is the write-after-read mode, the write data is "0".
” By bypassing writing to one image memory, the writing time to the image memory can be shortened. In particular, if the image data to be written is based on white,
Most of the data does not need to be written, so rounding has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. Figures 2 (a) to (j) are operation time charts when the write data in Figure 1 is not "0", Figure 3 1al.
~(f) is the behavior when the write data in Figure 1 is “0”.
, is a production time chart. In the figure, 1...
・Memory circuit, 2...Address register, 3...
...Write data register% 4...Read data register, 5...OR circuit, 6...
... "0" detection circuit, 7 ... timing control circuit, 11 to 16 ... signal input terminal, 18.
19... Output terminal.

Claims (1)

[Claims] a rewritable memory circuit, an address register for temporarily storing an address to the memory circuit, a read data register for temporarily storing output data read from the memory circuit, and a temporary memory for image input data to be written to the memory circuit. a write data register that outputs the logical sum of the output of the read data register and the output of the write data register when the operation mode is the logical sum mode, and an output of the write data register when the operational mode is not the logical sum mode. a zero detection circuit that generates a zero detection signal when a predetermined number of bits in the contents of the write data register are all “0”, and a zero detection circuit that generates a zero detection signal when the zero detection signal is not output, and a and a timing control circuit that generates a control signal for writing the output of the OR circuit into the storage circuit, and outputs an access end signal without generating the control signal when the zero detection signal is output. . An image storage control circuit, wherein writing to the storage circuit is bypassed when the write data is "0".