JPS6246874B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character pattern generation circuit, and particularly to a character pattern generation circuit for a dot matrix printer.

When printing on a dot matrix printer, the host device must use JIS-C-
A character code such as 6226 is given, and the address of the character pattern memory where the corresponding character pattern is stored is obtained by some method from the given character code, and the character pattern necessary for printing is extracted and printed.

A common method for obtaining a character pattern memory address from a character code is to use a code conversion table that stores the correspondence between a character code and a character pattern memory for each character due to its versatility and logical simplicity.

However, with the method of storing character pattern memory addresses in code conversion tables, when printing characters of multiple sizes or characters of multiple fonts, multiple code conversion tables are required, which increases the hardware required to configure them. There was a drawback.

A first object of the present invention is to provide a character pattern generation circuit that can print characters of multiple sizes or characters of multiple fonts without having multiple code conversion tables.

A second object of the present invention is to divide a set of characters of the same size or a set of characters of the same font into one character set into a plurality of groups, and to divide the characters of each group into different groups. An object of the present invention is to provide a character pattern generation circuit that allows character patterns to be stored in a character pattern memory.

The method for dividing groups within a character set is as follows:
Differences in storage elements such as whether the character pattern memory is read-only memory or rewritable memory, and whether it is used as internal character pattern memory or external character pattern temporary storage memory, or read-only A possible method is to divide the memory according to the method of use, such as whether to use it as a character pattern memory for replacing or adding a part of the internal character pattern formed in the memory.

Next, using a drawing showing an embodiment of the present invention,
The present invention will be explained in detail.

As shown in FIG. 2, the character pattern memory in one embodiment of the present invention is composed of three types of dot matrix representations of one character: 24×24, 32×32, and 40×40. Here, the characters are classified based on the size of the dot matrix and are called character sets. 24 again
Each of the x24, 32x32, and 40x40 character sets consists of two groups: read-only memory and rewritable memory. The first addresses are A ₂₄ , A ₂₄ ′, A ₃₂ ,
A ₃₂ ′ and A ₄₀ , A ₄₀ ′.

Referring to FIG. 1, the code conversion table 1 is configured so that by giving a character code a made up of a rewritable memory, the character pattern corresponding to the character code a is stored in a read-only memory or is rewritable. The group selection signal e and character number d stored in the memory are output. Here, the character numbers are numbers sequentially assigned to each read-only memory and rewritable memory so as to correspond one-to-one to the character pattern memory. For example, in each memory group of character pattern memory, the storage order of characters is "A",
If the order is "B", "C", . . . , "0", "1", "2", . . . are assigned as the character numbers d, respectively.

The data length generation circuit 2 generates a character set selection signal b
By giving , the character pattern data length f of one character of the character set to be selected is output. For example, when a character set of 24 x 24 dots is selected, a data length of 24 x 24 = 576 bits = 72 bytes is output. In addition, the reference address generation circuit 3
is composed of a register and a selection circuit, and has the start addresses A ₂₄ , A ₂₄ ′, A ₃₂ , A ₃₂ ′ and A ₄₀ , A ₄₀ ′ written in advance, and the character set selection signal b and code conversion table 1. A ₂₄ , A ₂₄ ', which is the start address of the corresponding memory group of the corresponding character set, is determined by combining with the group selection signal b obtained by giving the character code
One of A ₃₂ , A ₃₂ ′ and A ₄₀ , A ₄₀ ′ is output as the group reference address g.

On the other hand, the character number d, which is one of the outputs of the code conversion table 1, is connected to the multiplication circuit 4 together with the character pattern data length f, which is the output of the data length generation circuit 2, and outputs the intra-group relative address h as the multiplication result. . That is, the character pattern memory 7
For example, in the case of a character set of 24 x 24 dots, the character pattern of one character can be read out by 72 characters.
(=576/8) addresses will be read.
Therefore, in the character pattern memory 7 that stores this character set, for example, the pattern for the letter "A" is stored at addresses 0 to 71, the character "B" is stored at addresses 72 to 143, and so on.
The character "C" is stored at addresses 144-185. In other words, the intra-group relative address h (starting address) of the pattern of the character "A" is the relative address h of the pattern of the character "B" by d×f=0×72=0.
is d×f=1×72=72, and the relative address h of the pattern of letter “C” is d×f=2×72=144
It can be calculated by

Further, the counting circuit 5 is set to 0 by the counting start signal c.
Counting starts from , and continues counting until the counted value matches the character pattern data length f. The output character pattern relative address i is connected to an adder circuit 6 together with the group reference address g and the group relative address h, and outputs a character pattern memory absolute address as the addition result.
Here, the counting circuit 5 receives the counting start signal c as described above.
Since counting is performed from 0 until it matches the character pattern data length f, the character pattern memory absolute address j increases sequentially from the first address to the last address of the target character pattern, and when the read/write control signal l is OFF, Character pattern memory 7
The desired character pattern is sequentially generated as pattern data k as an output, and the read/write control signal l is output.
When ON, pattern data k is sequentially stored in the target character pattern storage area.

The process by which character pattern memory absolute address j is determined by character set selection signal b and character code a has been described above.

The circuit configuration described above makes it possible to arrange a plurality of character sets with different matrix sizes in one address space. Furthermore, each character set can be divided into multiple groups and placed in non-contiguous address spaces. That is, there are differences in the storage element of the character pattern memory, such as whether it is a read-only memory or a rewritable memory, whether it is used as an internal character pattern memory or an external character pattern temporary storage memory, Alternatively, one character set can be divided into multiple groups depending on how it will be used, such as whether it will be used as a character pattern memory to replace or add a part of the internal character pattern configured in read-only memory. It becomes possible to allocate it to any position on the memory address space.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing details of the character pattern memory 7 in FIG. 1. DESCRIPTION OF SYMBOLS 1... Code conversion table, 2... Data length generation circuit, 3... Reference address generation circuit, 4... Multiplication circuit, 5... Counting circuit, 6... Addition circuit, 7...
...Character pattern memory, a...Character code, b...
...Character set selection signal, c...Counting start signal, d
...Character number, e...Group selection signal, f...
Character pattern data length, g...Group reference address, h...Relative address within the group, i...Relative address within the character pattern, j...Character pattern memory absolute address, k...Pattern data, l
...Read/write control signal.

Claims (1)

[Claims] 1. A code conversion circuit that outputs a character number and memory group selection information corresponding to a character code by giving a character code; a character pattern data length generation circuit that outputs a character pattern data length according to character set selection information; a reference address generation circuit that outputs a group reference address based on the selection information and the memory group selection information; a multiplication circuit that multiplies the character number by the character pattern data length; a counting circuit that counts until it matches the pattern data length; an addition circuit that adds the output of the counting circuit, the output of the multiplication circuit, and the output of the group reference address generation circuit; A character pattern generation circuit comprising: a character pattern storage circuit that generates a character pattern.