JPH0228474B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a printer device capable of vertical and horizontal printing, which can perform vertical and horizontal printing using a simple circuit.

In conventional printing devices, characters are printed such that the vertical center line of the characters is perpendicular to the moving direction of the carrier. This type of printing is called horizontal printing. However, recently, dot printers have been used to print vertically written text, that is, vertically printed text. 1A shows horizontal printing, and FIG. 1B shows vertical character printing. Various methods have been proposed for printing vertical and horizontal characters with dot printers, but one method is to prepare a character generator for vertical printing and a character generator for horizontal printing separately. Another method is to share one character generator for both vertical and horizontal printing. The former method has the disadvantage that the amount of hardware increases. Although the latter method has the advantage that it requires less hardware than the former, the conventional printing control system of this type has the disadvantage that the control circuit becomes extremely complex.

The present invention is based on the above considerations, and includes:
The object of the present invention is to provide a printer device capable of vertical and horizontal printing, which can take out pattern data for vertical printing or pattern data for horizontal printing from one character pattern memory using a simple circuit. Therefore, the printer device of the present invention capable of vertical and horizontal printing is capable of printing characters in the i-th row and k-column (where i=0,
1, 2...m-1, k=0, 1, 2...n-1) for storing the dot information of the partial area at a relative address of (i×n+k), and an m-adic row direction address.・Counter group 3 having a counter, an n-ary column address counter, and an l-ary bit-direction address counter that specifies the bit position within a word; and in the case of horizontal printing, a row address counter is set to a predetermined value. In the case of vertical printing, the above counter group 3 is connected so that the bit direction address counter counts the number of times the bit direction address counter reaches a predetermined value, and the column direction address counter counts the number of times the bit direction address counter reaches a predetermined value. The number of times the bit direction address counter reaches a predetermined value is calculated as the column direction address counter.
a counter control circuit 2 that connects the counter group 3 so that the counter counts and the row address counter counts the number of times the column address counter reaches a predetermined value; and the contents of the row address counter. an address conversion circuit 4 for generating a pattern memory read address corresponding to the combination of the bit direction address counter and the contents of the column direction address counter; It is characterized by comprising an output data selection circuit 7 that selects one bit in the data, and a serial input/parallel output conversion circuit 8 that converts the output of the output data selection circuit 7 into an m-bit printing pattern. be. below,
The present invention will be explained with reference to the drawings.

FIG. 2 is a diagram showing the print pattern on the pattern memory, FIG. 3 is a conceptual diagram of the pattern memory, and FIG. 4 is a diagram explaining the reading order in the case of horizontal printing.
FIG. 5 is a diagram explaining the reading order in the case of vertical printing, FIG. 6 is a block diagram of an embodiment of a printer device capable of vertical and horizontal printing of the present invention, and FIG. 7 is a block diagram of an embodiment of a counter circuit. It is.

One character consists of 24 x 24 dots. As shown in FIG. 2A, if a 24×24 dot character is divided into 24 rows in the horizontal direction and 3 columns in the vertical direction, there will be 8 dots in each divided area. FIG. 2B shows the structure of a pattern memory for one character. This one character pattern・
The memory area is 72 words x 1 byte.
Pattern the divided area in the first row and first column of Figure 2 A.
The divided area at the first row, second column is assigned to the first address of the pattern memory, and the divided area at the first row, third column is assigned to the second address of the pattern memory at address 0 of the memory. Thereafter, in the same way, the divided area in the 24th row and 1st column in FIG.
The divided area in the second row and column is assigned to the 70th address, and the divided area in the 24th row and third column is assigned to the 71st address of the pattern memory.

FIG. 3 is a conceptual diagram of the pattern memory. A single dot that makes up a character can be specified by specifying the divided area to which the dot belongs using the row address and column address, and then specifying the position of the dot within the divided area. . That is, one piece of dot information can be specified by the position in the row address direction, the position in the column address direction, and the position in the bit direction.

FIG. 4 shows the reading order in the case of horizontal printing. In the figure, numbers such as 1, 2, . . . , 24 indicate the order in which dot columns consisting of 24 dots extending in the positive column address direction are read out. It is also assumed that the printing pin is 24 pins. In the case of horizontal printing, the initial state is the line direction address,
The column direction address and bit direction address are set to "0". Next, the row direction address is updated sequentially and the dot information is read. When the row direction address reaches "23", the row direction address is set to "0", the bit direction address is set to "1", and the row direction address is sequentially updated. I'll update it. By repeating this operation, when the bit direction address becomes "7" and the row direction address becomes "23", next change the row direction address to "0", the column direction address to "1", and the bit direction address to "0". Then, the row direction addresses are sequentially updated. By repeating such operations, characters in the pattern memory can be printed horizontally.

FIG. 5 shows the reading order in the case of vertical printing. 1, 2, 3, 4, 5, 6... in the same figure.
The numbers , etc. indicate the reading order of a dot array consisting of eight dots extending in the negative bit direction. In the case of vertical printing, the initial state of the row direction address is "0", the column direction address is "2", and the bit direction address is "7". When reading starts, the bit direction address is sequentially decremented by 1, and when the bit direction address becomes "0", the column direction address is set to "1" and the bit direction address is set to "7".
The bit direction address is sequentially decremented by 1. When the bit direction address becomes "0", the next column direction address is set to "0", the bit direction address is set to "7", and the bit direction address is sequentially incremented by one. When the bit direction address becomes "0", the row direction address becomes "1", the column direction address becomes "2", and the bit direction address becomes "7". Thereafter, by repeating the same operation, characters in the pattern memory can be printed vertically.

FIG. 6 is a block diagram of one embodiment of a printer device capable of vertical and horizontal printing according to the present invention. In FIG. 6, 1 is a counter circuit, 2 is a counter control circuit,
3 is a counter group, 4 is an address conversion circuit, 5 is an address information selection circuit, 6 is a pattern memory, 7
Reference numeral 8 indicates an output data selection circuit, 8 indicates a serial input/parallel output conversion circuit, and S1 to S8 indicate signal lines, respectively.

The counter circuit 1 generates row-direction addresses, column-direction addresses, and bit-direction addresses. The counter control circuit 2 controls the connections between the counters of the counter group 3 based on the vertical printing/horizontal printing instruction signal H/V. The counter group has three types of counters indicating row-direction addresses, column-direction addresses, and bit-direction addresses. The address conversion circuit 4 converts the row-direction address and column-direction address generated by the counter circuit 1 into pattern memory addresses, and is composed of, for example, a ROM. The address information selection circuit 5 selects an address on either the address line S3 or the address line S4 based on the signal on the address selection line S1.
As mentioned earlier, pattern memory S6 is 72
An area of word x 1 byte is allocated to one character, and the character area is specified by a character code. The output data selection circuit 7 is
One bit is selected from one byte of data read from the pattern memory 6 based on the bit direction address on the signal line S6. The serial input/parallel output conversion circuit 8 receives 3 bytes of data and outputs it as a parallel signal. The signal line S1 is an address selection line, and for example, when it is "1", it selects the pattern address of the signal line S3, and when it is "0", it selects the pattern address of the signal line S.
Select address 4. The signal line S2 is for sending an input pattern to the pattern memory 6. The address of the signal line S5 is the address of the pattern memory 6. The signal line S6 is
This is for sending the bit direction address to the output data selection circuit 7. The signal line S7 has a 24-bit configuration and is used to transmit print pattern data. The address conversion circuit 4 contains a ROM for vertical printing and a ROM for horizontal printing.
ROM exists, but the signal on signal line S8 is 2
This specifies which of the various ROM types should be used.

FIG. 7 shows one embodiment of the counter circuit. In the figure, 9 indicates a 24-base counter, 10 an octal counter, and 11 a ternary counter. The 24-decimal counter 9 specifies the address in the row direction, the ternary counter 10 indicates the address in the column direction, and the octal counter 10 indicates the address in the bit direction. Counters 9, 10, and 11 are up counters. Note that solid lines indicate connections for horizontal printing, and dotted lines indicate connections for vertical printing.

In the case of horizontal printing, the carry of 24-decimal counter 9 is 8.
The carry of the octal counter 10 is input to the ternary counter 11. The contents of the 24-decimal counter 9 and the contents of the ternary counter 11 designate an address within one character area of the pattern memory, and a combination of these is sent to the address conversion circuit 4. For example, if the content of the 24-decimal counter 9 is "10111" and the content of the ternary counter 11 is "00", the address conversion circuit 4 is
Specify address 69. The contents of the octal counter 10 specify the bits to be selected by the output data selection circuit 7. For example, when the content of the octal counter 11 is "000", the output data selection circuit 7 selects the leftmost bit.

In the case of vertical printing, the offset of the octal counter 10 is input to the ternary counter 11, and the digit of the ternary counter 1
One key is input to the 24-decimal counter 9. The contents of the 24-decimal counter 9 and the contents of the ternary counter 11 specify an address within a one-character area of the pattern memory 6. For example, when the content of the 24-decimal counter 9 is "00001" and the content of the ternary counter 11 is "00", the address conversion circuit 4 inputs the pattern memory 6
Specify the 5th address. When the content of the octal counter 11 is "000", the rightmost bit of the output data selection circuit is selected. In addition, octal counter 1
0 and the ternary counter 11 are used as down counters, and the octal counter 10 is set to "7" as an initial value.
If "2" is set in the ternary counter 11,
The same ROM for address conversion as for horizontal printing can be used.

As is clear from the above description, according to the present invention, the reading of dot information from the pattern memory in the case of vertical printing and the reading of dot information in the case of horizontal printing are performed using a common hardware. This method has the effect of significantly reducing the amount of hardware compared to conventional methods.

[Brief explanation of drawings]

Figure 1 is a diagram explaining vertical printing and horizontal printing, Figure 2 is a diagram showing the printing pattern on the pattern memory, Figure 3 is a conceptual diagram of the pattern memory, and Figure 4 is reading in the case of horizontal printing. Diagram explaining the order, No. 5
The figure is a diagram explaining the reading order in the case of vertical printing, and FIG.
The block diagram of the embodiment, FIG. 7 is one of the counter circuits.
FIG. 2 is a block diagram of an embodiment. DESCRIPTION OF SYMBOLS 1... Counter circuit, 2... Counter control circuit, 3... Counter group, 4... Address conversion circuit, 5... Address information selection circuit, 6... Pattern memory, 7... Output data selection circuit, 8 ……
Series input/parallel output conversion circuit, S1 to S8...
...Signal line, 9...24-base counter, 10...8-base counter, 11...3-base counter.

Claims (1)

[Scope of Claims] The i-th row and k-column of a character pattern divided into m×n partial areas each consisting of 1 l bits (where i=
0, 1, 2...m-1, k=0, 1, 2...n-1)
A pattern memory 6 that stores dot information of a partial area in a relative address of (i×n+k), an m-ary row address counter, an n-ary column address counter, and a bit position within a word. In the case of horizontal printing, the bit direction address counter counts the number of times the row direction address counter reaches a predetermined value; The counter group 3 is connected so that the column direction address counter counts the number of times the bit direction address counter reaches a predetermined value.In the case of vertical printing, the column direction address counter counts the number of times the bit direction address counter reaches the predetermined value.
a counter control circuit 2 that connects the counter group 3 so that the counter counts and the row address counter counts the number of times the column address counter reaches a predetermined value; and the contents of the row address counter. an address conversion circuit 4 for generating a pattern memory read address corresponding to the combination of the bit direction address counter and the contents of the column direction address counter; Vertical and horizontal printing characterized by comprising an output data selection circuit 7 that selects one bit in data, and a serial input/parallel output conversion circuit 8 that converts the output of the output data selection circuit 7 into an m-bit printing pattern. Possible printer device.