JPS5891493A - Character pattern generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character pattern generation circuit, and particularly to a character pattern generation circuit for a dot matrix printer.

When printing with a dot matrix type printer device, the host device gives a valid character code specified by JI8-C-6226, etc., and stores a character pattern corresponding to the given character code in some way. It obtains the address of the character pattern memory in the memory, takes out the character pattern necessary for printing, and prints it.

A common method for obtaining a character pattern memory address from the character =- is to use a code conversion table that stores the correspondence between character codes and character pattern memories for each character due to its versatility and logical simplicity.

However, with the method of storing character pattern memory addresses in code conversion tables, multiple code conversion tables are required when printing characters of multiple sizes or characters in multiple fonts, so the hardware required to configure them is There were growing drawbacks.

A first object of the present invention is to provide a character pattern generation circuit that can print characters of multiple sizes or characters of multiple fonts without having multiple code conversion tables.

A second object of the present invention is to divide the characters constituting the character set into a plurality of groups, and to divide the characters in each group into different groups when a set of characters of the same size or a set of characters of the same font form one character set. An object of the present invention is to provide a character pattern generation circuit which enables storing a character pattern in a character pattern memory.

The method of group division within a character set depends on whether the character pattern memory storage element is read-only memory or
Differences in storage elements such as whether the memory is rewritable, whether it is used as internal character pattern memory or external character pattern temporary storage memory, or whether it is used as read-only memory to replace a part of the internal character pattern or A possible method is to divide it depending on how it is used, such as whether it is used as a character pattern memory for adding.

Next, the present invention will be described in detail using drawings showing one embodiment of the present invention.

As shown in FIG. 2, the character number turn memory in one embodiment of the present invention has 24
There are three types: X24, 32X32 and 40X40. Here, they are classified based on the size of the dot matrix and are called character sets. Ma・ta 24X24, 32X32
Each of the 40×40 character sets is composed of two groups: read-only memory and rewritable memory. The first address of each
＾4゜A4:, AH, AH' and AH, A@'.

Referring to FIG. 1, the code conversion table l is composed of a rewritable memory, and by giving the character code number, the character pattern corresponding to character code 1 is read out, and the special memo 'JK' is stored or rewritten. Outputs the group selection signal and character number d stored in the available memory. Here, the character number is the character no (
These numbers are sequentially assigned to each read-only memory and rewritable memory so as to have one-to-one correspondence with turn memories.

The data length generating circuit 2 outputs the character pattern data length f of one character of the character set to be selected by applying the character set selection signal S. Furthermore, the base f17)' response generation circuit 3 is composed of a register and a selection circuit, and has a starting address of @4, kB', AH.

A, 1', A4D, A46' are written in advance, and the corresponding characters of the corresponding character set are determined by the combination of the character set selection signal and the group selection signal obtained by giving the character code to the code conversion table 1. A, which is the start address of the memory group,
A, 4', A,, A,,'# and Aae # 'a'
One of them is output as the group reference address g.

On the other hand, the character number d, which is one of the outputs of the code conversion table 1, is connected to the multiplication circuit 4 together with the character pattern data length f, which is the output of the data length generation circuit 2, and the intra-group relative address h is obtained as the multiplication result. Output.

Further, the counting circuit 5 starts counting from O in response to the counting start signal C, and the counted value is the character number (turn data length f and -
7- Continue counting until the count is complete. It is connected to an adder circuit 6 together with its outputs, which are the character pattern relative address 11, the group reference address g, and the group relative address h, and outputs a character pattern memory absolute address as the addition result.

Here, since the counting circuit 5 counts from 1:0 until it matches the character pattern data length f by the counting start signal C as described above, the character pattern memory absolute address j is the target character) (the start address of the turn). When the read/write control signal 1 is OFF, the characters are sequentially increased from 1 to the final address. If so, the pattern data k is sequentially stored in the characteristic patent pattern storage area.

The process by which the character pattern memory absolute address j is determined by the character set selection signal and the character code a has been described above.

The circuit configuration described above makes it possible to arrange a plurality of character sets with different matrix sizes in one address space. Furthermore, each character set can be divided into multiple groups and placed in non-contiguous address spaces. That is, whether the storage element of the character pattern memory is a read-only memory or a rewritable memory, whether it is used as an internal character pattern memory or an external character pattern temporary storage memory, Alternatively, one character set can be divided into multiple groups depending on how it is used, such as whether it is used as a character pattern memory to replace or add a part of the internal character pattern configured in read-only memory. It becomes possible to allocate to any position in the memory address space.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a diagram showing details of the character pattern memory 7 in FIG. 1. DESCRIPTION OF SYMBOLS 1... Code conversion table, 2... Data length generation circuit, 3... Reference address generation circuit, 4... Multiplication circuit, 5... Counting circuit, 6... Addition circuit, 7...・Character pattern memory, G...Character code, b...Character set selection signal, C...Counting start signal, d...Character number, e...Group selection signal, f...Character pattern data length, g...group reference address, h...relative address within the group, g...relative address within the character pattern, j...character pattern memory absolute address, k...
・Pattern data, ・・Read/write control signal filling in d

Claims (1)

[Claims] A code conversion circuit that outputs a character number and group selection information corresponding to a character code when a character code is given, a character pattern data length generation circuit that outputs a character pattern data length according to character set selection information, and a character cella. A reference address generation circuit that outputs a reference address based on the target selection information and the memory circuit attribute, a 5 multiplication circuit that multiplies the character number and the character pattern data length, and a count start command that starts operation. a counting circuit that counts until it matches the character pattern data length, an addition circuit that adds the output of this counting circuit, the output of the multiplication circuit, and the output of the reference address generation circuit; A character pattern generation circuit characterized by comprising a character pattern storage circuit that generates pattern data.