JP2526042Y2 - Memory / register control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial application field> The present invention relates to an improvement of a memory / register control circuit.

<Prior Art> As shown in FIG. 3, a virtual memory (here, a memory whose bit width and address length can be set to any size without being restricted by hardware. In a configuration in which the number of bits of 1 is N times the number of bits of the physical memories (registers) 2a to 2d (here, the register is 8 bits, the virtual memory 1
Is 32 bits), and writing from the memory 1 to the register is performed N times (four times). At this time, the address of the lower few bits (2 bits in this case) of the memory and
Circuitry for sending a write signal to the register (Q ₀ ~Q _3), that is, required memory register control circuit 3.

The memory / register control circuit 3 usually has a configuration as shown in FIG.

In the figure, 31 is an up counter for counting the end of writing to each register, 32 is a NAND (NAND) element for detecting that all writing has been completed, and 33 is a D for clearing the counter 31 by detecting the end of writing. A type flip-flop 34 is a shift register that outputs a signal for sequentially writing four registers (not shown) each storing 8-bit data.

In such a configuration, a start signal is supplied to set the output of the flip-flop 33 to a high level (hereinafter, the high level is simply referred to as HIGH), and the start signal is supplied to the D input terminal of the first stage of the shift register 34. The output of the shift register is set to HIGH at the rise of the clock CLK input during the period when the start signal is HIGH.

Output signal Q ₀ of the first shift register becomes a write signal for the register of the first (0th), memory contents (data of 8 bits) (not shown) is written to that register. In this case, the address of the lower 2 bits for the memory is 0 (the 2-bit output of the counter 1 is 0).

On the other hand, the counter 31 counts one clock and its output becomes 1.

Second output Q ₁ is HIGH next flip-flop of the shift register 34 at the rising edge of the next clock, the write signal is applied to the No. 2 register, the data from the memory is written. In this case, since the output value of the counter 31 is 1, the contents of the address whose lower two bits of the memory address are 1 are written to the register.

Thereafter, data is written in the third and fourth registers in the same manner, and the data of 8 × 4 bits is stored in four 8-bit registers four times.

<Problem to be Solved by the Invention> However, such a conventional memory / register control circuit has a problem that it has a large number of components and is expensive.

An object of the present invention is to solve such a problem, and to provide a memory / memory having a simple and inexpensive circuit configuration.
It is intended to realize a register control circuit.

<Means for Solving the Problems> In order to achieve such an object, the present invention requires that the number of bits of a virtual memory whose bit width and address length can be arbitrarily set be N times (N times) the number of bits of a register. A memory register control circuit that sends an address to the virtual memory and a write signal to the register when writing from the virtual memory to the N registers in N times in the configuration A shift register for individually transmitting a write signal for each of the registers in synchronization with a clock; a shift register having a least significant bit input terminal fixed at a HIGH level and a second or more higher-order bit input terminal from the lower bit. Each output from the first stage onwards is sequentially assigned and input, and the higher-order bit input is preferentially encoded for these bit inputs. Output priority
An encoder is provided, wherein the output of the priority encoder is provided to the virtual memory as an address signal, and a signal output from each stage of the shift register is provided to each of the registers as a write signal.

<Operation> By using the register write signal alternatively obtained by the shift register for the input of the priority encoder, it is possible to control the memory address and the register write signal as in the past with fewer components than in the past. .

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a memory / register control circuit according to the present invention. In the figure, the same parts as those in FIG. 3 of the conventional example are denoted by the same reference numerals, and the description thereof will be omitted. Reference numeral 40 denotes a priority encoder, and the relationship between its input and output is as shown in Table 1.

However, 1 indicates HIGH, 0 indicates LOW level signal, and when there are a plurality of inputs (signals of 1) at the same time, only the upper bit input is preferentially encoded.

Here, for simplicity of explanation, a 4-input 2-output priority encoder is taken as an example.

In the priority encoder 40, the least significant bit input (D ₀ ) is forcibly set to HIGH, and the output Q of the first flip-flop A of the shift register 34 is applied to the second lowest input (D ₁ ). ₀ is input, the output Q ₁ of the second flip-flop B of the shift register 34 is input to the third input (D ₂ ) from the lower order, and the _third input (D ₃ ) is input to the most significant bit. the output Q ₂ of the flip-flop C are respectively connected.

The operation in such a configuration will be described next with reference to the time chart of FIG. Gives the start signal, it outputs Q ₀ of the flip-flop A of the shift register 34 is HIGH at the rising edge of the clock CLK arrives during HIGH. As a result, the memory output (contents of address 0) is written to register 0. On the other hand, the output of the priority encoder 40 becomes 1 (A1 is 0 and A0 is 1) slightly after the rise of the clock, and the contents of the address 1 are output from the memory.

The following output Q ₁ is HIGH next flip-flop B of the shift register 34 at the rising edge of the clock CLK, the register 1
Is written into the memory at address 1. Then the output of the priority encoder 40 is 2 (A ₁ is 1, A ₀ is 0) and a.

Then, at the next rising edge of the clock, the shift register 34
Output Q ₂ of the flip-flop C for becomes HIGH, register 2 in the contents of memory address 2 is written. And then the output of the priority encoder 40 is 3 (A ₁ is 1, A ₀ is 1) become.

Similarly, at the next rising edge of the clock, the shift register
The output Q ₃ of flip-flop D 34 becomes HIGH, the register 3 the contents of the memory address 3 is written. Thereafter, the output of the priority encoder 40 becomes 0.

As described above, the contents of the memory can be stored in the four registers four times.

Although the embodiment deals with the case where the data length is 32 bits, the control circuit of the present invention is not limited to this, and can be applied to longer data lengths such as 64 bits and 128 bits. It can be dealt with simply by adding a shift register and an encoder according to the number of bits.

<Effects of the Invention> As described in detail above, according to the present invention, while having the same functions as the conventional circuit, the number of parts is smaller than that of the conventional circuit, and the man-hour and the occupied area when mounting the printed circuit board are reduced. Can be reduced by half, and a memory / register control circuit that is inexpensive can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a memory / register control circuit according to the present invention, FIG. 2 is a time chart for explaining the operation, and FIG. 3 is a system for storing data of a virtual register in the register. FIG. 4 shows a conventional memory device.
FIG. 3 is a configuration diagram of a register control circuit. 34 shift registers, 40 priority encoders.

Claims (1)

(57) [Scope of request for utility model registration] 1. A configuration in which the number of bits of a virtual memory whose bit width and address length can be arbitrarily set is N times the number of bits of a register (N is an integer).
When writing to the registers in N times,
A memory register control circuit for transmitting an address for the virtual memory and a write signal for the register, a shift register for individually transmitting a write signal for each register in synchronization with a clock, and a least significant bit input terminal being HIGH. The outputs from the first stage of the shift register are sequentially assigned to and input to the upper bit input terminals of the second or higher order from the lower order, and the upper bit input is preferentially encoded for these bit inputs. A priority encoder that outputs a converted value, and supplies an output of the priority encoder to the virtual memory as an address signal, and a signal output from each stage of the shift register as a write signal to the register. Register control circuit.