JPS60108891A - Dynamic display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (8) Technical Field of the Invention The present invention relates to a control circuit for a dynamic display device using a matrix arrangement of light emitting elements by a main controller in an electronic system such as an electronic exchange.

(b) Background of the Technology In electronic systems such as electronic exchanges, dynamic display devices in which light emitting elements are arranged in rows and columns are generally controlled by the main controller of the system. Therefore, display operations such as storage of display contents, address circulation, readout of display contents, transfer of display parts, and timing thereof all place a burden on the main controller, and improvements have been expected.

(C), Prior Art and Problems As mentioned above, in the past, the main control device created display contents,
In addition to the inevitable operations as a main control device such as &I collection, updates, changes, etc., we also perform dynamic display operation equipment.
This has the disadvantage of increasing the load.

(d) 9 Purpose of the Invention The present invention focuses on the above points, and the display operation is performed by a circuit added to the display device, and the main control device is used as a main control device for creating and updating display contents. The purpose is to significantly reduce the load on the main controller by performing only unavoidable operations.

(e) 6 Structure of the Invention The above object is to generate a clock signal in an electronic system such as an electronic exchange, which has a display device in which light emitting elements are arranged in rows and columns, and the display device is controlled by a main controller of the system. circuit, a counting circuit for cyclically specifying a row address using a clock signal generated by the circuit, a decoder and a flip-flop for selecting one row of the display device specified by the address, and storing display contents. memory.

It is equipped with a flip-flop for reading one line of display content from the memory according to the address and temporarily storing it, and a drive circuit for supplying the power necessary to turn on the light emitting element by the output of both the flip-flops. When the main controller of the system reads and writes the display contents to the memory, the main controller switches the read/write designation, 2 line address designation, 2 display content transfer, etc. lines to the main controller. This is achieved by a dynamic display circuit characterized in that it is equipped with a switching gate circuit for this purpose, and the load on the main controller is significantly reduced.

(f)0 Embodiments of the Invention An embodiment will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a time chart of waveforms at each part in FIG. 1, including a, b...j, and X.

y corresponds to the portion indicated by the same letter in FIG.

In the display device of this embodiment, the main controller CC of the system creates and edits display contents and writes them into the memory M, but subsequent display operations are performed by a circuit added to the display section DPLY.

Generally, the display section DPLY has m rows and n columns of light emitting elements, but in this example, in order to make the explanation 71 iliR, the time chart in FIG. 2 uses m=13. n is shown as an arbitrary number. The display section DPLY displays data by cyclically selecting one of the m rows X and simultaneously giving the display contents of that row to the n columns y.

First, the display operation will be explained. In the main controller CC, in this case, the terminals C3 and CR are at logic "1". Therefore, the output of the AND gates WA and RA of the switching gate circuit SWG causes the three-state driver WG to
, RG are in a high impedance state and the AND gate C
A causes the output of the terminal AD of the main controller CC to be logic “0”.
(OR game) is input to OR.

A clock signal a is generated by a clock signal generation circuit CLK. When the clock signal a is input to the m-time counting circuit CTR, the output of the m-time counting circuit CTR is obtained with the falling edge of the black/7 signal a as a change point. m =
8, the output b is output on three lines as shown in FIG. In response to this output b, decoder DCR outputs row selection signal C.

When m=8, this row selection signal C is output to 8 lines,
As shown in FIG. 2C, each line becomes a logic "1" cyclically. Clock signal i input to flip-flop FFX
As mentioned above, the logic "1" is output from the terminal CS of the main controller CC, and the clock signal "1" from the AND gate 8A of the switching gate circuit SWG has the same waveform as the clock signal a. Therefore, flip-flop FFX
latches the input of the row selection signal C at the rising edge of the clock signal 1 and holds it until the next rising edge of the clock signal i, thereby outputting the row selection signal d as shown in FIG. 2d. This row selection signal d is outputted by the drive circuit DRX to a drive output X as shown in FIG.
Select the FLY row.

On the other hand, the address designation f input manually to the terminal AD (three when m=8) of the memory M is the AND gate SA, C of the switching gate circuit SWG because the terminal cs is logic "1".
By ORing A and the OR gate, the output of the m estimator circuit CTR becomes the same waveform, and the decoder function of the memory M selects the row address 1, and the contents of that address are transferred to the terminal RW of the memory M. (n pieces), resulting in an output g as shown in Fig. 2g. This output g is the flip-flop F
The flip-flop FFY outputs an output j as shown in FIG. 2j by being launched at the rising edge of the clock signal i and held until the next rising edge of the clock signal i. This output j is the drive circuit D
RY causes a drive output y as shown in FIG. 2 y, and the display content of the row selected by the drive output X on the display section DPLY becomes the display content.

Next, the display contents are changed by the main controller CC.

The case of reference will be explained. (Not shown in the time chart of FIG. 2) In this case, the terminal CS of the main controller CC is set to logic "0". Therefore, switching gate circuit SWG
By the AND game 1-SA, all the outputs of the m counting circuit CTR become logic "0" and are input to the OR gate (OR gate), and the terminal AD of the main controller CC (for m=8, 3+1&
The addressing output from
Terminal A of memory M is connected as it is by CA and OR.
It will be input to D.

When changing the display contents, the monarch fall device CC sets the terminal CRt to logic "0" and switches the switching gate circuit SWG to
The driver WG is set to the operating state by the output of the AND gate WA, and the write operation is determined by inputting logic "0" to the terminal WE of the memory M, and m messages are sent to the terminal AD of the main controller CC. An address in the format of the output of the counting circuit CTR is given, and the displayed content of the address is given to the terminal DT (nll), thereby writing to the end f-RW of the memory M via h.

When referring to the display contents, the main control bag Wcc is connected to the terminal CR@
As logic 1”, switching data 1-AN of circuit SWG
The output of the D gate RA puts the driver RG into the operating state, and the read operation is designated by inputting logic "l" to the terminal WE of the memory M, and the terminal A of the main controller CC is set to the operating state.
An address in the format of the output of the m estimation circuit CT R is given to D, and the display contents of the address outputted from the terminal RW of the memory M are read from the terminal DT.

During display content change or reference operation, Furi-7Fronop FF
The clock signal i input to X and FFY is set to logic "0" by the AND gate ΔA of the switching gate circuit SWG, and the inputs of the flip-flops FFX and FFY are not launched, so the write and read operations by the main controller CC are not performed. The content displayed inside is not displayed for fun, and the display remains in its previous state.

As described above, changes and references to the display contents of the memory M from the main controller CC are performed asynchronously with the display operation. Also, writing by the main controller CG.

Since the time required for successive readout operations can be made extremely small compared to one cycle of clock signal a, the display surface of display section DPI, Y is hardly affected by write and read operations, and when the operation ends, terminal CS becomes logic When the clock signal i passes through the AND gate AA and the clock signal i is output, the logic becomes "1" and rises, the new display content starts from the row selected at that time. Is displayed.

In this example, we will explain how to create, change, and view display contents. 16 is an example in which this is done by the main control device CC of the system, but if a control device is provided that has the same function as the main control bag 7cc described above in terms of creating and changing display contents (referring to them if necessary), A separate display device is also possible.

(g) Effects of the First Invention As will be explained in detail, according to the present invention, the dynamic display is performed by a circuit added to the display device, and the dynamic display device is operated by an external control device (for example, the main control device of the system). It is now possible to change the display content 1 and refer to it asynchronously, and the main controller no longer needs to have a memory for the display content being displayed, eliminating the load for Guinaminok operation and significantly reducing the load on the control unit. be.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG.
It is a time chart of the waveform of each part of a figure. In the figure, °ζ and CLK are clock signal generation circuits. CTR is Inn base number circuit DCR is decoder, FFX,
FFY is a flip-flop, DRX, DRY are drive circuits, DPLY is a display section 9M is a memory, SWG is a switching gate circuit, SA, CA, AA. WA and IMA are AND gates, and OR is an OR gate. WG and IMAG are drivers, CC is a main controller, and AD. C5, CR, DT, WE, and RW are terminals.

Claims (1)

[Claims] In an electronic system such as an electronic exchange, which has a display device in which light emitting elements are arranged in rows and columns and is controlled by the main controller of the system, a clock signal generation circuit is used, and a clock signal generated by the circuit is used to generate a cyclic signal. A stitch count circuit for specifying a row address, a decoder and a flip-flop for selecting one line of the display device specified by the address, a memory for storing display contents, and a stitch count circuit for selecting one line of the display device specified by the address; The content of the memory is displayed by comprising a flip-flop for reading out and temporarily storing the display content and a drive circuit for supplying the power necessary for lighting the light emitting element by the output of both the flip-flops. When the main controller of the system reads and writes display contents to the memory, a switching gate circuit is installed to switch the lines such as read/write specification 1 line address specification 2 display content transfer etc. to the main control device side for control. A dynamic display circuit characterized by comprising: