JPS5852689A - Display driving system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display driving method for driving a display device such as a liquid crystal display.

In the preceding FI, the stored contents of the random access memory configured by the integrated circuit are displayed on the R7F.
- A storage area for each address, that is, a cell constituting each bit of the random access memory, is provided with an individual borrow line, and a gate is provided for each cell. . Therefore, there is a problem that the groove 1 becomes larger.

An object of the invention is to provide a one-line display driving system that allows for miniaturization of the structure.

FIG. 1 is a perspective view of one embodiment of the present invention.

The large-scale integrated circuit CHIP 1 includes a circuit for driving a display device 2 using liquid crystal, and these circuits are as follows.
It is housed in a wiring board (not shown). On both sides of the terminal board 3 of the display 2, input terminals Sla, S3a, S5 of one group Gla out of the two groups are provided.
a , -= , S 63 a and the input terminals SUa, S2a, S4a..., of another group GOa.
562a is placed. This display device 2 has segment electrodes to be described later, and sequentially selects every other segment electrode to be applied sequentially and divides them into two groups Gla and GOaK, and segments for each group.
Input heir Sυa-563a connected individually to the tun pole
are arranged loosely on both sides of the terminal board 3 as shown in the figure.

The circuit configuration within the large-scale circuit chipl is shown in FIG. In this large-scale integrated circuit, basically,
Random access memory 4 that stores display number 18, and the store value of the random access memory 4 is assumed to be non-standard) (soft registers 5A and 5B that output , a circuit provided outside the large-scale integrated circuit chipl), a serial/parallel switching circuit 6 for data transfer, a chimbu select control circuit 7, In the unlikely event that the clear circuit 8 and display unit 2 complete set-J, the driver should be used! j A, 9 B, and Cronk generation circuit■0
including.

There are 16 large-scale integrated circuits cbipl, as described in connection with Figure 39, which shows quick speed.
”, their product circuits are shown in the figure cl]ipl~chip
16. Chip select control circuit 7eyu,
In response to signals that can be input from terminals C80 to C53, large-scale integrated circuits chipl to chip16 to be operated are activated.

(1) Random access memory 4 In this embodiment, the random access memory 4 has a width of 64×
A storage area of 20 vertical bits is provided, as shown in FIG. 3, t1+. The display 2 has the same number of display dots for each bit as the storage area, as shown in FIG. 3(2). Each bit of the random access memory 4 and each dot of the display 2 have an individual correspondence of 1-.

In the following description, components and signals applied to the components may be indicated by the same reference numerals.

In FIG. 2, 13, 14. i! 5,120 indicates the number of bits of the signal line. In Figure 3, reference 1
'l sign ADo~A, i) 7 is a signal to represent the address of the random access memory;
Signal ADO-AD5 is used for row selection, and signals AD6 and AD7 are used for column selection.

Backplate force timing signal HO to H1 on display 2
9, (a+timing signal HO-H7 corresponds to At)6=U, AD7=0 at the time of column selection, (1)) Timing signal H8 to 1115 is the address for column selection. No. 43 A, D 6 = 1.
, AI) Corresponding to 7=0, (C) Timing signal 1 (16 to i (19 is address a-SAL for column selection) 6=0, corresponding to AD7=1 (8). Segment voltage 4m of display unit 2 SO~563 is the address signal that cannot be selected by low.
) There is 1 corresponding to 5.

4 to 81'XJ specifically show the random access memory 4 and its related circuit configuration. Each cell of the random access memory 4 is divided into an even number group 4a and an odd number group 4b by selecting every other address (r-1) derived sequentially in timing order and grouping them into an even number group 4a and an odd number group 4b. The signals from the cells of the even group 4a are sent to the output terminal s mentioned above.
o, s2°S4. ..., derived from S62. The signal of each cell of life number group 4b is sent to the aforementioned output terminal S.
l.

53, S5. ..., derived from S63. Signals from cells in even group 4a are led out to shift register 5A, and signals from cells in odd group 4b are led out to soft register 5B, where data transfer is performed.

The address signal given to the random access memory 4 is obtained as follows. The address controller 11 is supplied with signals from each cell Al-A3 of an 8-bit register A having cells AO-A7, and also receives signals from each cell C0-C4 from a 5-bit register C having cells CO-C4. A signal is given. data selector 12k
ld, cell AfJ of register A, A6. A7 and cell hO
A signal from a five-pit kakunta h consisting of ~114 is given. Cells CO to C4 and cells hO to h4 are used to extract the contents of the random access memory 4 in one burst and display the serial signals SRU and XA used to configure the SRI.
l-reru. The cell AU-A7 is provided to the random access memory 4 only when data is transferred to/from the outside.
It is composed of 70 flips. Therefore, normally cells Co-C4 and hO-h are used for display.
4-Ai Random access memory 4 address and data selection) Data transfer from the outside is performed in the form of an interrupt. At the time of this interrupt, an address signal completely different from the address signal from which the display value is to be derived is given, so during that time, the display signal may become distorted and the display 2 may not be able to display tJ normally. In order to solve this problem, the present invention provides launch type flip-flops 13 and 14 (see FIGS. 5 and 6) that act as data buffers for the output of the random access memory, and at what timing can data be input from the outside. Even if a transfer is interrupted, the display 42 is set to V so that a correct display can be obtained.

The signal C5 in FIG. 7 is an output signal obtained from the 71J block C8 shown in FIG.
When the value is -0, the large-scale Tokyo bond circuit chip1 is not selected. The signals RAS and RAF are signals generated when data is transferred from the outside, and when C3=1, the signal R
, AS occurs, address and data selection tJ of random access memory 4, address signals A1 to A7
It can be changed to the operation using q. When c5=o-t or i-RAS is not occurring, address decoder 15F (id, cells C0A-C of counter C) derives the low selection force signal of random access memory 4.
The signal 8 from cell h3.4 is given to the column selector 16, and the cell h3. Trust from h4 is given. Counters c and h are counters used to generate display signals as described later. The column selector 16 is connected to a group selector 17 for depositing the even group 4a and the odd group 7'4b, and a read write controller 18. The read/write controller 18 is manually supplied with a write clock WR. The @ numbers Ni and Mi (i=0 to 7) from the group selector 17 are the clip 70 knobs 13 shown in FIGS. 5 and 6.
．． 14, and this output ni,m] is used in the circuit of FIG. Thus, the signal SRO is obtained by the circuit shown in FIG. Another signal S
Rl can also be obtained in exactly the same manner.

Referring to FIG. 9, the signal RAS is shown in FIG. 9(1), the signal RAF is shown in FIG. 9(2), and the resulting address of the random access memory 4 is The signals used for this are determined as shown in FIG. 9+31K.

The structure of the electrodes in the display device 2 is as shown in FIG. They are indicated by reference signs HO to H19.

FIG. 11 is a waveform diagram showing the output state of the counter C,
FIG. 12 is a wave diagram showing the output state of the counter h. With reference to these drawings, for example, Vanquebrae) H
While the signal to drive I3 is being generated, cell l]
(1~h 4Ur OJ, column a B < v of random access memory 4) so A D 6 = 0
, A, I) 7 = 0. Since hU=hlnib2=0, the signal SRO has mO, i.e., the 0th focus line of the even group 4a of the random access memory is scanned by the outputs from cells CO to C4 of the counter C and is converted into serial data. is obtained. Signal SRI
The same applies to In this way, pack plate H19
While the signal H19 is being generated, the display data to be derived during the generation period of the next bank plate HO signal is shifted to the soft registers A and B, and is launched and derived when the signal H19 is changed to HO. be done. Thereafter, the contents of the random access memory can be retrieved as display 1) by sequentially incrementing the counter h.

Referring again to FIG. 9, when data is transferred from the outside to the random access memory 4, the signals RAS, RA
F will occur. Flip-flops 13 and 14 (see Figures 5 and 6) are row flip-flops whose clock operates as D = C8@RAF, and when C5 = υ゛ or signal RAF is generated and I/-1 is not present. When, input signal Mi
, outputs the contents of Ni to the seventh box, and outputs the signal RA when C3=1.
When F occurs, that is, when ON = LOW, data is held. Therefore, signals RA S and RA F are generated during data transfer with the outside, and even if the output from the random access memory 4 changes to another content, the previous correct display data is flipped.
can be memorized. This prevents the display d8 from being disturbed during an interrupt.

The reason why the signal RA F is configured to temporally include equal % RA S is that the address 17J of the random access memory 4 is changed by the signal RA S K, and the output of the random access memory at the time of this 17I change is This is to prevent changes in price from being transmitted to the 7-lip tabs 13 and 14. The signals RA S and RAF will be explained in detail later.

121 Soft registers 5A, 5B As a means to receive the stored contents of the random access memory 4 as a display signal, originally a single byte output is converted to a serial signal zero, and this is sent to the soft registers 5A, 58
K is transferred and latched at latching times %19A and 19B using a clock O8 synchronized with the display blade to obtain a segment signal. As shown in Figure 2, soft register &, lI
:, 5A, 5B are divided into two blocks, one soft register 5A is configured to correspond to the 61 number of the segment, and the capacity soft register 5B is configured to correspond to the even number of the segment. In this way, soft registers 5A, 5
The reason for dividing the output terminal into 8, 4iJ4, and odd numbers is to similarly divide the output terminal of the large-scale integrated circuit cbip1 into two, an even number and an odd number.

As mentioned above, FIG. 10Q shows the pattern of electrodes in the display 2 according to the present invention. The idea of the present invention is that it is possible to display kanji and graphics.

In this case, the number of segments is large, and the input terminal S Oa~5
If you try to give a signal to the segment electrode from 63a,
Due to terminal pitch constraints, it is necessary to separate every other terminal into upper and lower sections as shown in FIG. Therefore, in order to prevent the lines connecting the input terminals SOa~563a and the output terminals SO~563 from crossing each other, the output terminals SO~S6
3 is also divided into two parts: even number and number of digits. To Sam,
Another reason for dividing into two groups is to reduce power consumption of the large scale integrated circuits Chip 1 to Chip 16. By dividing into two groups, the clock for sending data from random access memory 4 to shift register sA, 5Bvtci is 3
Only 2 pieces are enough. If there were no 17 divisions, 64 transfer locks would be required, and in order to create 64 transfer locks within a certain period of time, the basic oscillation direction wave number would have to be doubled, as in the Honten example. When configured with K C-+vIOS (fourth complementary planned oxidized semiconductor), the amount of power is doubled.

+31 kakunta c, h FIGS. 11 and 12 show the timing of the counters h and C, and FIGS. 13 to 17 show details of the configuration of the counters h and c and their errors. The basic clock 01 shown in FIG. 11 (1) generated by the clock generation circuit 10 causes the counter CL shown in FIG. 13 to perform a runt operation,
c4・c3・c2・cl@c (when J=1, clock a
S is generated as shown in FIG. 11 (7). A signal H is input to the reset terminal of the counter C.
Synchronization is achieved by Counter C is a 32-decimal counter. Figure 12 +21 to Figure 12 (6) are signal C
The waveforms of O to C4 are shown respectively. Clock XS is obtained by an AND gate shown in FIG.

The counter h shown in FIG. 14 is a counter clocked by O8 in FIG.
It can be given by HOR. H is the signal of the synchronous force reservoir,
Signal HOR in FIG. 12(8) is determined by the output from register N having cells N0-N3. 12+21 to 1216) show the waveforms of the signals from cells 1]0 to h4, respectively, and FIG. 12(7) shows the waveform of the signal HS.

The value of register N must be set externally.
From the matrix shown in FIG. 16, the 1]6+J- only memory is a circuit that generates a reset signal HOR for the counter h using the VC of the register N. 12th
In the waveform diagram shown in the figure, signal 1 (OR is (H4・h 3・H
2・b 1Φho), and the counter h
is in base 20. The flip-flop 21id1, which is positive in FIG. Fortune-telling, I say-
! -J110 Invert every R.

As is clear from the above, the count number of the counter h determines the duty of the puck play (HO to Hl 9). Register N is a register for setting the due date.

The sweet signal f(S) is a signal that constitutes the alternating voltage '1'.

(4)! Similar parallel/parallel converter circuit 6 All internal data processing is performed in parallel, and in order to transfer data serially to the outside, a serial/parallel register is required. This is a shift register with functions of Lld, +M column/parallel out, parallel in, and series out. Fig. 38 (1) shows the signal field CLO;
FIG. 8(2) shows the waveform of the signal LC, and FIG. 38(3) shows the waveform of the signal RAS. Reference symbol SDU is a serial data bus, CLO is a serial transfer lock, and L Cid synchronization signal.

The 8-bit data serially transferred from the outside via terminal SI) 0 is temporarily stored in the register shown in Figure 18, and is stored in the internal random access memory 4 as well as the address, chip select and duty data, and the random access memory. 1 is used as data that can be written to 4.

Ill store the contents of random access memory 4 externally.
The data in the VC 61 and the random access memory 4 are first input in parallel to registers, and then output as serial data to the outside by a shift function. In order to distinguish between the above data transfer types, [2 bits are added before the 8-bit serial data, [00J, [U
Four types of I J , [I U J , and [11J] are detected and each data transfer is performed.

Here, "00" is writing of duty and chip select data, 1'-t) IJIr, t, writing of address data of random access memory 4, "10" is unraveling of data of random access memory 4, "11" reads data from the random access memory 4. After data is written into the random access memory 4 or ml is extracted, the address register 8 of the random access memory 4 is automatically incremented by +1. This is to prevent an accumulation of addressing each time in continuous random access memory 4 and notator transfer.

19 to 36 show details of the serial/parallel conversion circuit 6. Figures 37 and 38 show time charts for serial data transfer. Serial data transfer operation is performed by the third
Signal L in FIG. 37 (2) and FIG. 38 (2) using CLO in FIG. 7 +1+ and FIG. 38 (1) as the basic clock.
Starts as soon as C rises.

37+1+ shows the waveform of the signal CL O, FIG. 37+211'j shows the waveform of the signal LC+7), and FIG.
3) Shows the waveform of the signal WSDO, and Fig. 37 (4) to 3
Figure 7 (7) shows the output waveform from cell 3 to cell KO ~, Figure 37 (8) kj and Figure 37 (9) ke signal -jJOLsO
The waveforms of k and nLsl are shown respectively in Figure 37 (10
1 and 37 (11) respectively show the waveforms of the signals LSO and LSI, FIG. 37 (121 shows the waveform of the signal 3 and 2, and FIG. FIG. 37 (14y shows the waveform of signal RA F,
37(,+51) shows the waveform of the signal FL, and FIG. 37(I6) shows the waveform of the signal S1D.

The counter Kid shown in FIG. 19 is a 4-bit pinary counter, and performs a counting operation while the signal 8LC is "L", and is reset when the signal LC becomes "oJ".The counter has 0 or II-, 14-j. A series of serial data transfers is completed by counting with .The data is 8 bits, but 2 bits are added to the front to distinguish the data type.The signal OLS0 in Fig. 20 and 0LSI shown in Fig. 21 are ,
This is a clock that receives the contents of this control 2 bits, and is used by the flip-flop 22 in FIGS. 22 and 23.
゜23 is the control 2 bit (Fig. 37 131 K
(contents of bits PA and PB) are statically stored in the serial data transfer interval. O L +4 obtained by the configuration shown in FIG.
and 12, the previous eight clocks are for the register L to perform a soft operation, and the last clock is a clock for storing the contents of the built-in random access memory 4. This distinction is made by register ■
, by the K 3 -K 2 signals that control the input gates of .

The signal RAS shown in FIG. 24 has a counter K of 10°1,
Between l and l2, the RAF shown in Figure 25 is 9.1f.
J, 11, 12.13 are clearly audible, and the signal RAsfd chip select, duty write circle.
It is used as a clock for writing and writing addresses, and is also used for switching addresses when reading and reading data into the random access memory 4.

□ Signal RAF is as described in section (1). The signal in Figure 29 is a bidirectional data line and is normally an input, but the flip 70 knob 2 in Figure 30 is
When 7 is "l", it becomes an output. Signal 51) D is the 38th
As shown in the time chart in the figure, this is the output from the flip 70 knob 27 that is set only when reading out data from the random access memory 4, and after two control bits are given, the random access memory 4
In order to transmit a serial signal of data to the outside, it is set at "Lc transfer end i".

Chip select and duty writing Referring to the time chart in FIG. 38, FIG. 38+41 shows the waveform of the signal SDO, and FIG.
Figure 38 (17) shows the waveform of S D D, Figure 38 (8
) shows the waveform of OC8. Control 2 bit [O
When UJ is sent, LSO=0°LS ] =:Q, and clock OC5 is generated by the configuration shown in FIG.

At the rising edge of the clock OC5, the shift of the 8 bits of serial data following the control pin is completed, and the upper 4 bits of the 8 bits are shifted to the register.
The contents of L7 are transferred to register N whose specific configuration is shown in FIG. In addition, as shown in the input conditions of the flip-flop 28 that derives the signal C8 in FIG.
- If the contents of L3 match, the flip-flop 28
is set, and reset if there is a mismatch. In other words,
If you transfer chip select data to a large-scale integrated circuit (hip') with many hard-wired chips, set the selected cbipl's 7-lip 70-tube C8 to match this code, and chip2～1
All six flip-flops 28 are reset. Here L 4 = L 5 = L 6 : L 7 :
= 1, the signal OC8 is inhibited as shown in FIG. This is because when this code is used, chip selection and duty settings are prohibited, and auto-flash cancellation is performed. Writing the address shown below and transferring data to the random access memory 4 is as follows:
It is valid only when flip-flop 28 is set.

Infiltration of address data Figure 38 shows the waveform of +91 tr:J:, ftt number S DO, Figure 38 shows the waveform of SO Figure 38 shows the waveform of signal S1 (112), and Figure 38 (+31) shows the waveform of signal OA.

When control 2 bits “01” are given, L S
O=O, L S l = 1, and the cloffish A is generated by the configuration shown in FIG. 33. 4E4 j+1
1 A +7) Ii, the 8 bits of serial data following the control hit are soft photons in the register, and as shown in Figure 38 (rule), LSU = 0.
Therefore, the input to the address flip 70 block AONA7 is from cells LO to L7, and the address data is solved.

Writing data to random access memory 4 Figure 38 (14) shows the waveform of i.
Figure 11 rll signal I-S (l) waveform, i, f
~3s figure (+61 iJ: shows signal f-S l i71 waveform, 381st sentence 1 (17) i1; SSI) I)
Figure 38 (+8) CJ a, -1 and +
WlgJ) Indicates wave 11 d 12, 38th g> l (l!
I)? :i (+'i 8OA (7) Indicates wave 1 -
4-1o con 10-le 2 pill-[I U j selects 1), ■, 80=].

1, S] Two ()tonas, random access memo 1. +
4 [Against - (Kikomi Kurotsuta~'J
As shown in Figure 4 (/'), 'i(, raw-rru.Message 1.L W
RT, t1 9 RA S fl 1 MI K = 3i
fi/li - Sururi I7 Tsuku de Shin! = J.R.
A P Go, Control Pi while S is out) VC
8 bits of serial data (", register r, 7 bits..., Figure 2 9i 2> 1 <t" 2 eζ (digit 3I, 0 to L7 are random access memory 4 manpower LJ gill 71, Ri[Cook W R(,
5 Therefore, random ack-his/write to Mori 4 6o
In this case (7), the address is t-'j! -J'f<
Accordingly, the address decoder 15 and the ram selector lf]Qj- are shown in FIGS. 35 and 30e (shown in FIG.
4l; JA, 0~A 775"jk plus 1% ik
t), data is written to addresses indicated by km 't' AU to A7.

Here, counter K, 4V f& of 13, clock OA
or occur. If L SO = 1, then this signal m
A register A+1 ink 1 noment is made by A.

This means that when writing T-events continuously to the internal random access memory 4, the address is incremented by +1, and the address is incremented by 41 times by 40°, just by writing the data, without having to specify the address each time. It is possible to transfer data quickly even if it is not certain.

Reading data from random access memory 4 or I- Fig. 38 shows the waveform of signal SDO, Fig. 38 shows the waveform of signal SDO, Fig. 38 shows the waveform of IB L80, and Sentence 1 of 381 shows the waveform of signal LSl. Figure 38 (21() is Shinba S
The waveform of DD is shown, and Figure @38 (', !, 4) is the signal yA.
The waveform of is shown. Control 2 bits r l l j'
When f is sent, LSO=1. LS1=0, the flip 70 knob 27 is set to derive the signal 5l)D from the next bit of the serial data, and as shown in FIG. r-.

is given, the contents of the register L are softened by the I cook OL, and the n column data and 17 are given to the terminal SDO2 to the outside. Here, the data of the random access memory 4 shown in the register LK (CL, register At) is written. During data pr''■, the four operations shown in Fig. 38 are necessarily performed.On the contrary, and (7)
6: J-1 Figure 138 shows the clock OL and Ij-7W RA.
S is obtained by 1. in 7ir.

clock fi61. Pi'+) (Juki PC given) L Ruri 1j Tsuku no Tachi 1 Ri 01 random access to IIM-;
In memory 4 KML, 1.1' RA S is output (V), and address signals A O to A7 are given.
As outputs 00 to 07 of random access memory 4, l\
The contents of the random access memory 4 indicated by 0 to A7 are output. - Force, drive shown in Figure 18 A huru': The input of the register L is (IJsu CJ O~o7 is
and the signal yLL7) Tz of the last clock
As a result, the contents of the random access memory 4 indicated by the register Vtci and signals AO to A7 are read. Therefore, when reading data 17 from random access memory 4 is started from 1, register LK always records the contents of random access memory 4 as 1, and this can be stored externally by software. By outputting the data, the contents of the data in the random access memory 4 can be read and output. In this way, the data contents can be read from the random access memory 4.

At the end of reading data from the random access memory 4, f-, fl, the clock OA is generated (V) ld, by exactly the same extrusion as when writing data to the random access memory 4.

(5) Nap select control circuit 7 The segment signal of the large-scale integrated circuit chipl is SO~
There are 64 S63, usually -1, and a plurality of these large-scale integrated circuits CHIP 1 to CHIP 6 are used. In this case, select one of the large-scale circuit boards from among the multiple ones.
There are 3 children C8O to CS. 4 wooden chip select terminals CSO to CS: 3 &11,')
+61 solid daihiki model tohaku times 1st class cbi pl ~c++i
p l 6 f-4 & snoring Qo Here, as a special number for the tree brother, it is necessary to connect the left signal + r;'/no line, GNf)
or VCC city α, (level K l'l hY l',
Hti deyo I (, Koni 7'): Ake 1 will be.

ffl, 39 Kl &; 1.16 pieces (7) large iJ,
! , ,tu,! L reconnaissance cbil-+1~cbip
If 16 is connected to I'l'', ly is q, even if it is 1''-1SD (1,
CI-(J, 0゜11 〕take is fine. As municipal heavy uranium VA, VB, VCC, G N l), Vl) IS
P Ka must 'JI T Alo. +jl” I UAr I
7) Line Daigen Model Toei Episode - Each CL + IPL ~ CBI
pl (up to 7 for i;; B] 1 to 1 for BL direction, 1 to 1 mouth, 1 mouth for Tensoujiku) and 1] for 1).

Richi 28 Figure 1'(11<su'', Uic, 7 II 7p71:I Rada C8 or tomorrow, when I'm reading this fritsflobe C8 or 7) circuit c
bi1) l&Uselect II! ! , 1, flip 70 tab C5 (cell), 4 select section VCYr 6° chip"? Left data Q, serial input from outside? j "J" as register La) cell L
If you compare O-L 3 and compare it, this toki σ) Cell LO~L
3's inner world Tochitsubu select clause A-F CS L1~
c s 3cm + Uchitani or content, then the cuff is set to flip-flop C3 (I), and if there is a mismatch, the flip-flop C8 is set to II-t = soft. Random access memory 4 address data, random access memory If you send data in and out of 4, you will receive a 1711' block from the f1 receiver.
Large-scale unaffected circuit chip 2 to cbip 1 that has a hippl problem and has reset the flip 71m1 tube C8
6 is not accepted. The flip-flop C5 has the 26th
Clock clock C that is broken by the configuration shown in Figures and Figure 27
S is given.

Flip-flop CS (7)-+z Soft reset condition 6'lni-no-1('') is equivalent to +J1j description 1-.

Because of the above-mentioned theory 1 da J fu yobiki (7" ii
) A signal derived from a flip-flop may be designated by the same reference numeral.

,+l O)・For clear wood brother 1fJ, back plate, segment (g-+
And annity Q, the force which is controlled by notware from outside 611 is +tV r&, notware processing J), then after the power is turned on, it is normal (all)' 6. It takes a long time to produce the product, and during that time, the display M1, 42 will not be able to display a normal surface, which may disturb the image of it as an RTS product.

So, in this play, I put VL in, and I immediately put 1 in the inner game.
〇Figure 40 eζ4'< 5 Fritsuzo 70 tube ALC
While the flip-flop ALC is set, data is stored in the soft registers 5A and 513, and the display 2 is kept in a resting state.

41st) l'gl V, reference + 4 non) P,
N tl and throat the PsuX channel and the Nf'l' channel.

The frig float ALC & resent is done by an external 1) signal. In the example, the duty setting is
When the code for IIIJ is sent, the duty is not set and the flip 70 tube ACL Noritake is performed.

Therefore, after inputting the source, cut out the pack plate and segment with a soft sea urchin/', set the value, set the earth duty, and then use the above-mentioned Hira Flip Frog AC.
Resetting L allows display 2 to transition from a resting state to normal display 1 operation.

In flip-flop ACL, Vcc or 41st
When VC is applied as shown in Figure (1), the AA point becomes the wave 1 shown in Figure 41 + 21 due to the capacitor 30 and resistor 31, and the wave 1 shown in Figure 41 + 21 is generated. "1.jK upper set 2"L. In this situation, it will be difficult to input the reset input. 9th
As mentioned in relation to w+K, flip-flop AC
1, #;j:, Manual power S to soft registers 5A, 5B
It is the 11th time to evaluate RD and S Rl, and the 70th 70th A CL is kept as "1". Since "0" data is given to the soft registers 5A and 5B, the display is in a dormant state. Keep +M. flip 70 tuzo acl
The reason why the answer remains 1 is that when the code corresponding to the duty is selected as [111, l J in the chip select and duty writing in FIG. 38, the reset signal +tReset in FIG. do.

(7) Driver 9A, OB Drivers 9A, 9B''J in Figures 42 and 43
A41] Show +. Input V of shift registers 5A and 5B
C is given the BHXcLusrvg OR of the signal H8 and the signal sRl to the signal HS and the number SRO. This allows an inverted signal to be generated in synchronization with the signal H5flfi1 period. Clock d1. O8 is the first
The clock m shown in Figure 1 and the timer of the 12th flash
1. , O8. ! Inner column data Vc exchanged +Li"-38RO, S Rl iJ2, rip oi
Accordingly, the runner 5 is written to the soft registers 5A and 5B, and the runner 5 is sent to the next stage flip-flop 117) by the clock O5K.

Signals S G f) to S in FIGS. 42 and 43
63 (・Clock S S ICC open and latched segment signals. #l, -#2 are liquid crystal driver cells, the configurations of which are shown in FIG. 45 and FIG. 46, respectively. .Here, Figure 46-2 Display 2
FIG. 45 shows a driver that can be used for both a segment and a back plate, and is a driver cell that can be used as either a segment or a back plate simply by changing the mask of the large-scale integrated circuit CHIP1. draft plan
The cell indicated by 32 and similar cells are ! ,'
, J change switch t7) works fully.

In this embodiment, driver cells #-1 to C are connected to the output terminals 80 to S19, and the output terminal 5O-519 can be outputted as a back plate or a segment.

FIG. 47 shows the power source of the reference number-#3 driver shown in FIG. 44, and FIG.
VB, Vlvl') connection, the timing diagram shown in FIG. 51 is shown. Also, #1 is shown in Figures 48 and 49.
Indicates the type of driver cell with segment-segment or back plate segregation. In these drawings V (% (SGI), (SGi), (T) indicate the belief that iiM No. SGi, SG〒, if S all levels have been converted.?; In Figure 51, t Yu, bank plate (dzuν Fig. 51 111i/iZ, Segment borrowing 3 is the 51st
+'Atz+, and Figure 51 (3) is the level vA.
, V 13 , VM and believe ',' (1-I
S ) &14 (51 In Figure 141, signal (sGo) 1
．． Seven notes are shown in Figure 51.

Here, the feature of the present invention is that the backplate signal and the segment signal are all differentiated only by selecting the output of the backplate type or segment type in the driver section, and the random access method The back plate and segment can be treated as the same data as 4.

Figure 52 shows the data arrangement of the random access memory 4 when VC4i+'j S O ~ S l 9 is given to the back plate. The data is set in Figure 11 and Figure 12.
Count like r varnish. Barafu” rate 1-11
At the timing of 9, A7Ati = Oon random access memory 4trro pin [Im is sent to the second line or soft registers 5A and 5B, and the latch clock O8 causes the flip-flop to switch to the next backplate ti o timing. -SG63 is output.

The driver corresponding to the communication 'flSGO has the configuration shown in FIG. 49. Soft register 5A in the case,
Human power to 513-], s I< oshin H8゜S Rl
Since the ΦII S'c is configured, the output waveform of the Shinsu SGO becomes the waveform shown in Figure 51 (5), and the 51st
The back plate becomes corrugated as shown in Figure (1).

WS G 20 to S G 63, the segment 46 is a driver that does not move), and in conjunction with the content, for example, t6N/(mfudosuJ, eel wave jshito) in figure 51. Here, if you change the setting of register N, the duty corresponding to table board 2 can be changed to VC.A signal is output to the back plate of the case. By repeating MJ
You can learn about it.

18 + Ritsk generation circuit 1° large-scale integrated circuit chipl to chipl 6, each of which has a display function is internally installed in 1ζ to have a display function. Mantissa large-scale integrated circuit h
When connecting i p1 to C1 p16, σ)
The clock is oscillated by one of the clock generation ports [110], and the large-scale integrated circuit (BIP2 to CBIP)
lf'iid: Overall synchronization is performed by receiving the same signal 5 as the basic clock. summer! , is the base Aζ clock shown in Figure 2, and H is the synchronous month. Basically [same as Jtsuk y] Large-scale confusion 1. How many months 1-1 will occur? jJ Ayu chip 1～chip1
6's mask will make a big difference.

〃Untall, c and I■S are 1mi +m after inputting the city source, but the same JIj is due to the first same lvJ ShinsuH
] will be done. The same number H is the fd number that is generated every frame of the display 2, and the direction 1t is generated every 1 frame.
/1 is taken. counter h by signal 11
, c and i] S is reset σ and synchronized 1. As explained in connection with FIGS. Therefore, in the repeating blade, it is a long signal of [(minor direction + 171, pulse 1llfi v: i clock y]) and is the same as the one-time signal.

As shown in FIG. 53, there are two types of synchronizing signal 11: one is supplied to the outside and the other is known to be supplied from the outside, and this can be switched by a mask.

On the other hand, the 11th internal clock is
Using the clock O1 shown in the figure, hl (not shown in the figure) generates a two-phase clock 1°02 in this embodiment, and the entire circuit configuration is 1. The 0 shown in the diagram is the basic clock consisting of 2 tithes 1 and 1.
The above-mentioned l-i:JW'' (, is made into a blade [21 old clock Ql by I, 02 is also 1t/].

FIG. 54 shows and discusses a circuit for generating a 24I truncation according to an example. One word 511T is 'Figure 54 (4)
This is the signal d generated by the signal I-1, and converts the clocks gl and 02 into jvI.

Figure 56 r (shows the time signal, shows that the +1 digit of the clock 01.02 for 4R'ft H has been changed by r8H, h71°) 561ZIII shows the waveform of the clock y, Figure 56 (2j ~Figure 56 (
4) The wave J of signal 'j a + b + C used in t, 541111) to Fig. Figure 16) shows clock 02 from 0 to Figure 56 (71
indicates the synchronization signal H, and Fig. 56 (8) indicates the signal 11T (]
- Show. A specific configuration of the circuit shown in FIG. 55(1) is shown in FIG. 55, 121K.

As mentioned above, according to Mishaku (Tera), the contents stored in the random access memory are sequentially read out and given to the buffer, so there is no need to provide a signal line for each cell of the random access memory. , and there is no need for a gate for that purpose.

Because there are seven parts, the configuration is smaller. When writing to the random access memory, the contents of the buffer are retained, so the display is not disturbed and the display quality is improved.

[Brief explanation of the drawing]

FIG. 1 is a diagonal diagram showing a display device 2 and a large-scale integrated circuit chipl according to an embodiment of the present invention; FIG. 2 is a block diagram showing the structure of a large-scale integrated circuit cbipl according to the present invention; Figure Q is a diagram showing the store value range of the random access memory 4. Figures @4 to @8 are block diagrams of the random access memory 4 and related blocks. Waveform diagram, 1st O Figure 1-1 Display 2
Figures 11 and 12 are waveform diagrams for explaining the operations of counters c and h, respectively.
3 to 17 are block diagrams showing the counters c and h and their related configurations, FIGS. 18 to 36 are block diagrams showing the serial/parallel conversion circuit 6 and its related configuration, and FIGS. Figure 38 is a waveform diagram for explaining the operation of serial/parallel data transfer, and Figure 39 is a large-scale integrated circuit channel.
40 is a block diagram showing the structure of the flip 70 tube ACL, and FIG. 41 is a block diagram showing the connection state of the flip 70 shown in FIG. 40.
Tsubu ACL fi # waveform diagram explained in the work, 4th
2 to 49 are block diagrams showing the configuration of the drivers 9A and 9B, FIG. 50 is a block diagram showing the connection state between the Q-scale collector circuit cbipl and Ichihara, and FIG. 51 is the display 2. Figure 52 shows the signal waveform diagram used for displaying the back plates SO to S19.
Figure 3 is a block diagram showing the IQJ signal (7) to generate the same IQJ signal, and Figures 54 and 55 are clock diagrams.
701.02) A block diagram showing the occurrence of the disaster is shown in Figure 56.
This is a waveform diagram for explaining the operation when L'j=1. 2...Display g, 4...Random access memory, 5
A, 5B...Shift register, 6...II'L column
Parallel father exchange circuit, 7... Nutup select control circuit, 8.
... Auto clear circuit, IO... Clock generation circuit, l]... AT (NOS controller, 12... Data selector, 19A, 19B-... Latch circuit, cbi
p 1- cltip l 6-Large scale integrated circuit, A.
...Register, "' c, h...Counter, C8
... Flip-flop, S() ~ 863 ... Output terminal, 5Oa-563a ... Input agent agent Patent attorney Kei Nishi Department Department Figure 1; 1580 = E
Ehe Figure 5 Figure 6 Figure 7) 4 Figure 8 Figure 9 1 [H1? Figure 10 Figure 24 Figure 25 Figure 26 Figure 27 Figure 30 Figure 32 Figure 34 Osama 58-5.26890 meeting? I:)I)-AINCl Channel 3b 〉〉〉〉〉〉〉〉〉 〶 Contains N, I N, ノ ζ, -Nt
Ln Σ 〉 591-

Claims (1)

[Claims] In a display driving method for driving a display device, there is provided a random access memory in which a signal representing the content to be displayed is inputted from the outside and stored therein, and the content stored in the random access memory is stored in the random access memory. When the random access memory is loaded, the buffer temporarily stores the signal from the random access memory of the loaded song. A display driving method characterized by not receiving signals from an access memory.