SU1381586A1 - Display device - Google Patents

Abstract

The invention relates to computing and can be used to indicate parameters in information processing systems. The purpose of the invention is to expand the field of application of the device by providing an operative change of the sequence of indication of parameters corresponding to the specified command identifier. The device contains a generator of 1 clock pulses, a counter 2, a decoder 3, registers 4-6, a multiplexer 7, a character memory block 8, a column signal generator 9, a column signal generator 10, matrix indicators 11 and 12, a signal selector 13 and an indication element 14 . The purpose of the invention is achieved by introducing into the device a multiplexer 7, a selector 13 of signals and an element 14 of indications, their connections with each other and with other units of the device. 1 il.

Description

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The invention relates to computing and can be used to digitally indicate parameters in devices for controlling and processing deformation.

The purpose of the invention is to expand the field of application of the device by providing an operative change of the sequence of parameters corresponding to a given command indicator.

The drawing shows a functional diagram of the device.

The device contains a clock pulse generator 1, a counter 2, a decoder 3, a first register 4, a second register 5, a third register 6, a multiplexer 7, a symbol memory unit 8, a column signal generator 9, a row signal generator 10, matrix indicators 11 and 12. signal selector 13, display element 14. Positions 15 and 16 denote the informational inputs of the device and its control input, respectively.

The device works as follows.

Informational messages 15 of the device are received from the external data bus by a message of two types of code of a two-symbol command identifier or state parameter codes of the monitored system (not shown in the drawing). U) and this is the single state of the sixteenth bit of the data bus defined by the transmission of the command identifier code, and the zero state is the system parameter codes. The control input 16 of the device receives a synchronization signal, according to which, depending on the state of the sixteenth bit, the selector 13 generates either a signal to write the identifier code to the |) Registry 5, or signals to write the parameter codes to register 6.

When transmitting the idea of gi (} 1ik, the mountain of the command / and. It is recorded in reshstr 5, with the output of which it is fourfolds (the code of the two signal identifier goes to the information inputs of the multiplexer 7. The information outputs of the multiplex ()) 8 memory characters.

The address of the block 8 memory addresses is equal to nine, of which three youngest bits are formed by counter 2, and the remaining six come from the multiplexer outputs 6 bits, while the ninth bit determines the location of the symbol in one of two blocks 8. Of the eight bits of the block, eight of the memories are used, only seven — by the number of rows of matrix indicators 11 and 12, in which the two-signal coma identifier code is indicated. Each of the indicators 11 and 12 has five columns, therefore, to connect the columns of both matrices, it is enough to have ten outputs of the decoder 3, which determines the choice of the number of bits of the counter 2. The high bit of the counter 2 is used to control the selection of the columns of the first and second matrix indicators, depending on which of the two symbols is indicated. Displaying the command identifier symbols is performed by applying a high voltage level to the columns of the matrix indicators 11 and 12, to the rows of which data is fed through the shaper of 10 rows from the outputs of the 8-character-memory block. If it is necessary to display the system parameters, the information inputs of the register 6 from the outputs of the second group of register 4 receive binary parameter codes, and the information inputs of the selector 13 from the outputs of the third group of register 4 are accompanying bits, the number of which corresponds to the number of displayed parameters.

At the outputs of the selector group 13, control signals are generated, according to which

the selected parameter is written to the third register 6 and is indicated by its display element 14. The sequence of the formation of these signals determines the order of indication of parameters

for example, in order of importance, or another criterion.

Thus, the device, together with the indication of the command identifier, allows indicating the corresponding parameters of the system state, ensuring that the sequence of indication of the parameters is operatively changed.

Claims (1)

Invention Formula A display device containing a clock pulse generator, the output of which is connected to the counter input of the counter, the outputs of the low-order bits of which are connected to the inputs of the decoder, the first and second matrix indicators, the horizontal and vertical tires of which are aligned respectively to the outputs of the signal conditioner lines and the formers of the SSC lbtsov, whose information inputs are connected to the outputs of the decoder A set of characters, the first register whose information inputs are the information inputs of the device, the second and third registers, characterized in that, in order to expand the field of application of the device by providing an operative lamination of the display order of parameters corresponding to the specified command identifier, signal selector, display element and multiplexer, information inputs of the first and second groups of which are connected to the outputs of the corresponding groups of the second register, control input of the multi ipleksora coupled to the control input of the column output signals and MSB score The output of the low-order bits of which is connected to the address inputs of the first group of the character memory block, the address inputs of the second group of which are connected to the information outputs of the multiplexer, the output of which is connected to the control input of the character memory block, the control input of the first register is connected to the first control The signal input of the signal selector is the control input of the device, the second control input of the signal selector is connected to the high-order output of the first register, the outputs of the first, second and third groups which are connected respectively to the information inputs of the second and third registers and the signal selector, the output of the signal selector is connected to the control input of the second register, and the outputs of the group are connected to the control inputs of the third register, the outputs of which are connected to the inputs of the display element, the information inputs A string driver is connected to the character storage unit.