JPH0895746A - Display controller - Google Patents

Abstract

PURPOSE: To improve the processing speed by providing a means which transfers a font from a CG(character generator) to a VRAM(memory for display) by a circuit. CONSTITUTION: This display controller is equipped with the character generator(CG) 1C which is stored with the font, the display memory (VRAM) 1D where one dot of display is made to correspond to one dot of the memory, and a control circuit 1E for transferring the data in the VRAM 1D to a display device 1F. An address generating circuit(MCC) 1B outputs select signals for 1C-1E on the basis of an address 1G from a CPU 1A to generate addresses of the CG 1C and VRAM 1D. Then transfer processing for display information is performed on the basis of the start address of a font memory and the transfer destination address of the VRAM 1D. Consequently, data transfer from the CG 1C to the VRAM 1D is performed in a time of single access to eliminate the need for two-time access wherein the CPU 1A reads data out of the CG 1C and writes them in the VRAM 1D by a program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a VRAM used for display.
The present invention relates to a display controller with improved data transfer to and from.

[0002]

2. Description of the Related Art Conventionally, in such a device, there has been an electronic device in which one dot of a display corresponds to one bit of a display memory VRAM for displaying. Character generator C that stores the font when displaying characters
The data for the size of the font from G was transferred to VRAM by software. Further, in a device which displays a raster scan, it is usual to arrange the VRAM so as to increase the address in the raster direction. Therefore, when transferring the font to the VRAM, after transferring the first line of the font, the address of the VRAM had to be calculated to point to the next line.

A description will be given with reference to FIG. The start address of the VRAM for transferring the font is 2A, and the font size is 16 bits × 16 bits. FIG. 3 shows a font to be transferred, which is sequentially transferred to the VRAM from the line 3A to 3B and 3C. The data of 3A was transferred to 2A2B, but the data of the next 3B had to be transferred to 2C. Therefore, a calculation process is required to output the address in the 2C VRAM. If the display is 640 dots horizontally, the address of (2A) +640/8 becomes the address of 2C. Like this, font 3
In order to transfer to the C and 3D rows and the VRAM, the VRAM address calculation processing was required for each row.

[0004]

Therefore, it takes a very long time to transfer the font to the VRAM.

In order to overcome the problem, the CPU clock has been raised or the CPU has been changed to a faster one to deal with it, but these means are costly and therefore unsuitable for small equipment. there were.

[0006]

In view of the above facts, in the present invention, the processing speed is improved by providing means for transferring the font from the CG to the VRAM in the circuit.

The present invention also stores a display memory for storing display information for displaying information, a font memory for storing display information stored in the display memory, and the display information stored in the font memory. The specified start address and a transfer destination address for transferring the display information to the display memory, and display information based on the start address of the font memory and the transfer destination address of the display memory. It is realized by performing transfer processing.

The present invention is realized by the display control device having means for transferring display information from the font memory to the display memory based on the start address of the designating means and the transfer destination address.

According to the present invention, in the display control device, the transfer means has means for calculating and outputting the transfer destination address based on the start address.

The present invention can be realized in the display control device, wherein the transfer means has means for directly outputting from the display font memory to the display memory without going through a CPU.

[0011]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows a system diagram in this embodiment. 1
A is a CPU, which controls the system. 1B is an address generation circuit MCC, which outputs select signals from 1C to 1E based on the address 1G from the CPU, and outputs CG1C,
The address of VRAM1D is generated. 1C is a character generator CG in which a font is stored, 1D is a display memory VRAM in which one display dot is associated with one bit of the memory, and 1E is a control circuit for transferring the data of VRAM 1D to the display device 1F. is there. 1F is a display device, and the display memory 1
It is a device for receiving and displaying the display data 1P from D.

Address generation circuit 1B, character 1C,
1D and 1E are connected to the CPU 1A by a data bus 1H. The address bus 1G from the CPU is connected to the address generation circuit 1B and the control circuit 1E. In addition, the RW signal 1I from the CPU also applies to the address generation circuit 1
B and control circuit 1E. The output 1J from the address generation circuit is a select signal to the character generator 1C, 1K is an address signal to the character generator, and the character generator 1C is an address indicated by the address bus 1K when the select signal 1J is active. Of the data is output to the data bus 1H. In this embodiment, there are 16 data buses. The signals from the address generation circuit 1B to the VRAM 1D are the address bus 1L and the control signal 1M. When the control signal 1M indicates a write, the content of the data bus 1H is written to the address indicated by the address bus 1L, and the control signal 1M is , When indicating read, address bus 1L
The data at the address indicated by is output to the data bus 1H.

A buffer 1S controls the CPU, the character generator, and the data bus of the display memory 1D. 1T is the control signal. In the display memory transfer mode, the character generator
The data bus of the display memory is separated from the CPU.

Reference numeral 10 is a control signal for transmitting display data to the display memory. In response to this signal, data is transmitted from the display memory to the display data 1P. Further, the control circuit transfers the display data 1P to the display device together with the timing signals necessary for another display.

1Q is an oscillator circuit, which generates a clock necessary for operating the present system. The output 1R is
It is connected to the CPU and the address generation circuit.

FIG. 4 shows a circuit of the address generation circuit. Four
A is a circuit for decoding a part of the address "ADR" from the CPU by the decoder. The signal "SEL" that goes "H" in the display memory transfer mode and the output of the timing generation circuit 4J are input, and the output of the circuit 4T that takes the OR is connected to the decoding circuit 4A. When the output of 4T is "H", the decoder 4A makes the output inactive. When the output of 4T is "L", the signals "CG", "VRAM", "R" are generated depending on the data of a part of "ADR".
The signals "1", "R2", and "R3" are activated. Here, it is assumed that "H" is output when active. “CG” is a signal which becomes active when the character generator 1C is accessed, and the OR circuit 4N
Connect to. The output of the OR circuit 4N becomes "H" when the signal "CG" or the signal "SEL" is active. Four
The output of N is 1J and is connected to the character generator 1C.

"VRAM" becomes active when the display memory is accessed and this signal is connected to 40. 40 is the RW signal 1I from the CPU and the signal "VR
It is a circuit in which "AM" and "SEL" are connected and a control signal for the display memory is generated. These 40 outputs are
It becomes a 1M control signal.

"R1" is a select signal of a register for designating the start address of the character generator 1C in the display memory transfer mode, and "R2" is a register for designating the start address of the display memory 1D in the display memory transfer mode. , "R3" is a select signal that triggers the start of the display memory transfer mode.

"R1" is connected to 4Q. R in 4Q
The W signal is also connected, and outputs "H" when both of these signals are "H". When the RW signal is “H”, it is a write, and when it is “L”, it is a read. The output of 4Q is connected to the register 4B, and the register 4B stores data in the register when the output of 4Q is "H". Register 4B
As described above, CG in the display memory transfer mode
Store the start address. This output is connected to the adder circuit 4D. The output of a counter, which will be described later, is connected to the adder circuit 4D, and the output of this counter and the output of the register 4B are added and output. The output of the adder circuit 4D is the selector 4
Connected to E. The selector 4E switches the address "ADR" from the CPU and the output of the adder circuit 4D by the select signal "SEL". That is, "SEL"
Is "H", the output of the adder circuit 4D is output,
When it is "L", the address "ADR" from the CPU is output. The output of the selector 4E is connected to 1K and supplied to CG.

"R2" is connected to the AND circuit 4R.
An RW signal is also connected to the AND circuit 4R, and the output becomes "H" when both signals are "H". The output of 4R is connected to the register 4F. When this signal is "H", the data from the CPU is stored in the register. As described above, this register stores the display memory start address in the display memory transfer mode. The output of the register 4F is the addition circuit 4G.
Connect to. The other input of the adder circuit 4G is the output of the counter 4K described above. The adder circuit 4G has a counter 4K.
And the output of the register 4F are added and output.
In this case, the output of the counter 4K is not added as it is.
That is, the address of the display memory must be increased in the Y direction after one access. In this embodiment, the increment in the Y direction is 128 bytes. In this case, the circuit can be simplified because the counter value can be shifted by 7 bits and then added. The output of the adder circuit 4G is connected to the scrap 4H.
Like the selector 4E, the scrap 4H outputs the output of the adder circuit 4H when the select signal "SEL" is "H", and outputs the address "ADR" from the CPU when "SEL" is "L". Is output. The output of the selector 4H becomes 1L.

4I is a control signal "A" from the CPU.
It is switched by "SEL" in the select circuit of "LE" and "SP" which is a pseudo "ALE" signal in the VRAM transfer mode. The output of 4I is the timing generation circuit 4
Connect to J. The clock signal 1R “CLK” from the oscillation circuit 1Q is connected to the timing generation circuit 4J. The output of the timing generation circuit 4J is connected to the counter 4K. This counter operates when "SEL" is "H". When "R3" and "RW" are "H", "H"
Is connected to the output of 4S, and when this is "H", the value of this counter is set to -1. This counter is an up counter. The value of the counter is incremented each time there is an output from the timing generation circuit 4J. When the value of the counter reaches 16, the output "CY" of the counter becomes "H". In this embodiment, the display memory transfer is 16 accesses. The value of the counter is added to the start address of the character generator and the start address of the display memory and output as the address of the character generator / display memory. Counter output "C
"Y" is connected to the OR circuit 4P. A reset signal "RST" is also input to 4P. (The reset signal is output from a reset circuit (not shown). The power supply voltage is output until it reaches a value at which each circuit operates normally and for a while after reaching that value.) The OR circuit 4P outputs "H" at the time of reset or when the value of the counter reaches 16. Upon receiving the signal, S
It is connected to the reset side of the R flip-flop 4L, and the output "SEL" of the flip-flop 4L is set to "L". When the output of the AND circuit 4S is connected to the set terminal of the RS flip-flop and the output of 4S is "H",
The output “SEL” of L becomes “H”. The 4M circuit is an "SP" generation circuit, which uses the output from the timing generation circuit to output "SP" at the first time when "SEL" becomes "H" and when "SEL" is "H". To generate. "SP"
As described above, "A in the display memory transfer mode
Plays the same role as "LE". In other words, it gives the start timing of access to the character generator and the display memory.

A timing chart is shown in FIG. Two clocks make one access. First access is CPU
Access. “ALE” is the access start timing output from the CPU. "PSO" is created by the timing generation circuit. After "ALE" is latched at the falling edge of the clock, 1.5 clocks later, "H" is output for one clock width. (When "SEL" is "H", "PS" replaces "ALE") "TE"
Is an access enable signal. Access is enabled during the "L" period. The cycle of timing 5-9 is the timing of setting R3. "T
When "E" becomes "L", 4L is set and "SEL" is set.
Becomes "H". At the same time, the counter is set to -1. The counter is "PS" when "SEL" is "H".
Count up at the rising edge of "O". In addition, "SE
When "L" is "H", "PSO" is output to "PS".
At the timing of 6-9, the counter value becomes -1,
At the rising edge of "PSO" at the timing of 9, the counter value becomes 0 and "PS" is output. In the display memory transfer mode, CG reading and access to write the data to the display memory are possible. Begins. For simplicity of explanation, if the counter reaches 16 at the timing of 17, "CY" is output. In response to this, 4L is reset and "SEL" is "L".
Becomes The data of the first address of the CG is written to the first address of the VRAM at the timing of 9-13, and the second data is transferred from the character generator to the display memory at the timing of 13-17.

(Other Embodiments) In this embodiment, 16 * 16
I explained about the transfer of the font of the
If it is configured such that the count number of "Y" can be programmed, 16 * N data can be transferred. Also, the number of horizontal bits is not limited to 16. For example, 8 * 16
This can be achieved by controlling the even-odd bank of the 16-bit data bus (16 bits are divided into 8 bits, and each is divided into even odds).

Also, regarding the modification of the upper line, the underline, etc., when the line is written, the output of the CG select signal is stopped, and instead, the MCC 1B outputs the line data to the data bus 1H. Easy to implement.

If the font size is fixed, the program can set the order of fonts to be transferred (called CG code) when one font is regarded as one data block, instead of the start address of the character generator. This will make the program easier. The circuit can be easily realized by adding a circuit for calculating the start address from the character generator code. In particular, in the case of a 16 * 16 character generator, one font has 32 bytes, and therefore specified data can be obtained by shifting it by 5 bits.

If the transfer area on the display memory has a fixed size of one font, that is, if the display memory has one area.
If it is considered that the mesh is the size of the font, it is possible to specify the transfer destination address of the VRAM with XY. The program will be simple in this case as well. In other words, if the X direction is set to be horizontal, all that is required is to set the value in the X direction register to +1 when displaying characters horizontally. When displaying vertically, all you have to do is set the value incremented by 1 in the Y direction register.

[0028]

As described above, data can be transferred from the character generator to the display memory in one access time, so that when the CPU reads the data of the character generator by the program and writes it to the display memory. As described above, since it is not necessary to access twice, the speed can be doubled.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration example.

FIG. 2 is an explanatory view of a conventional example

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is an explanatory diagram of an MCC circuit.

FIG. 5 is a timing chart.

[Explanation of symbols]

 1C Character Generator 1D Display Memory 1H Data Bus 4B Character Generator Start Address Register 4F Display Memory Start Address Register 4L “SEL” Output Flip Flop

Claims (4)

[Claims] 1. A display memory for storing display information for displaying information, a font memory for storing display information stored in the display memory, and the display information stored in the font memory. Specifying means for designating a start address of the display memory and a transfer destination address for transferring the display information to the display memory, and a transfer process of display information based on the start address of the font memory and the transfer destination address of the display memory. A display control device characterized by performing. 2. The display control device according to claim 1, wherein
A display control device having means for transferring display information from the font memory to the display memory based on a start address of the designating means and the transfer destination address. 3. The display control device according to claim 1,
The display control device, wherein the transfer means has means for calculating and outputting the transfer destination address based on the start address. 4. The display control device according to claim 1,
The display control device, wherein the transfer means includes means for directly outputting from the display font memory to the display memory without going through a CPU.