JPH063431Y2 - Flat panel drive - Google Patents

Description

[Technical Field] The present invention relates to a flat panel driving device, and more particularly to a dot matrix for displaying alphanumeric characters, symbols, etc., which are composed of a dot matrix such as a fluorescent display tube or a plasma display panel. The present invention relates to a driving circuit of a flat display panel of a type.

(Prior Art) Dot matrix for fluorescent display tubes, plasma display panels, etc., especially 5 × 12 60 dots for 1 digit (1 character)
And a device for driving a dot matrix type flat display panel having 60 data electrodes corresponding to each dot and a digit scanning electrode connected to each digit, is capable of storing 60 data for one character display. A shift register for storing and 60 data electrode driving circuits connected to its output, a shift register for transferring data for digit scanning, a digit electrode driving circuit connected to its output, and a buffer memory for receiving external data Alternatively, it comprises a memory (character generator) for generating a character pattern, an address counter for reading the contents of the memory at a display speed, an inverter for generating a driving voltage, and the like.
In this device, data from the outside is normally sent in parallel with 8 bits, and to receive it, two buffer memories are provided with 4-bit data input / output or one with 8-bit data input / output. Data is written to a predetermined address of the memory by a write address signal, a chip select signal or a write signal of the memory which is also used and which is also sent from the outside. If, for example, a static random access memory (RAM) is used as the buffer memory, the same data can always be read by writing the data of each digit, for example, 1 to 40 digits once. When the same address as when writing to the memory is designated by the address counter, data corresponding to each digit is output from the memory and sequentially sent to eight 8-bit shift registers. The data accumulated in the shift register is boosted to a drive voltage by the data electrode drive circuit at a timing when a predetermined digit is selected and sent to the data electrode. On the other hand, the digit scan data is synchronized with the data, input to the shift register, sequentially transferred to 1 to 40 digits by 40 clock signals, and boosted by the digit electrode drive circuit connected thereto. The signal sequentially scans the digit electrodes. By sending data to the selected digit in this way, it is possible to display a predetermined alphanumeric character or symbol at a predetermined digit. However, when driving such a flat display panel composed of 5 × 12 60 dots, if data from the outside is received in 8 bits in parallel, 8 bits for data storage can be obtained.
It has the drawback that the bit shift register plays.

Furthermore, if an IC in which a shift register having an input / output terminal is integrated for every 5 dots of data corresponding to 5 dots of one character on a flat display panel and a data electrode driving circuit is integrated, the ICs for these 5 circuits are Two bits are required for each bit of parallel data, that is, a total of 16 bits are required, and there is a drawback that 20 circuits are played.

Even in this case, if the external data is received serially or in parallel with 2 to 4 bits, there will be no circuit to play.
In the case where each bit data length is 4 bit parallel, it is twice as long as 8 bit parallel, and there is a drawback that the blink generated during data writing increases.

(Object of the Invention) The object of the present invention is to eliminate these drawbacks, to eliminate the play of the drive circuit, at low cost, and to produce a high-quality dot matrix type flat surface with little blinking that occurs when the display is stopped during data writing. An object is to provide a display plate driving device.

(Structure of the Invention) According to the structure of the present invention, the electrodes corresponding to the 60 dots of the flat display plate that constitutes one character by a dot matrix of 60 dots consisting of 5 horizontal × 12 vertical, A character corresponding to the input data of the shift register is displayed when an electrode connected to a drive circuit connected to the output of the time-divisionally driven shift register and facing the 60 dots at a predetermined interval is selected. In the flat panel driving device described above, the shift register is divided into 6 corresponding to the time division, and the number of outputs of each shift register among the 6 divided shift registers is 10.

(Example) Next, this invention is demonstrated in detail, referring drawings.

FIG. 1 is a block diagram showing a 5 × 12 60-dot matrix type flat panel driving apparatus according to an embodiment of the present invention. In the figure, the present driving device is configured by using a data electrode driving IC provided with external 6-bit parallel data and an input / output terminal for every 5 dots of data. To write the 6-bit parallel data a from the outside, the chip select CS is set to "L", the address switching unit 3 is switched to the external address b, the address line c of the RAM 2 is connected, and the write signal WR is set to "L". However, by making three-state buffer 1 through,
External 6-bit parallel data D _{0 to} D ₅ can be written to a predetermined address of AM2. The 6-bit parallel data D _{0 to} D ₅ from the outside each have a data length of 2 digits of 5 dots across one character of the flat display panel, that is, 10 dots. Therefore, 40 bits of data for 60 dots of 6 bits are stored in a location designated by an address described later. Addresses A _{0 to} A ₉ are addresses that can be specified from the outside, of which A _{0 to} A ₃ are 1
An address for 10 dots in which two horizontal lines of 5 characters are consecutive is designated, and A _{4 to} A ₉ are addresses for selecting 1 to 40 digits of the flat display panel. 40
During the period of writing the digit data, the blank signal B
Display is stopped by L for about 5 ms.

When the chip select CS and the write signal WR become “H”, the RAM 2 is automatically set to the read mode, and the address switching unit 3 uses the counter 5 that divides the oscillator 4 having an oscillation frequency of 80 KHz at a cycle of 12.5 μs or 250 μs. The changing internal address d and the address line c of the RAM 2 are connected.

The address that changes every 12.5 μs cycle is also used as the clock signal e of the IC6 that integrates the shift register equipped with the input / output terminal for every 5 dots of data and the data electrode drive circuit, and is the address corresponding to A _{0 to} A _3. 10 dots of data in the RAM 2 are input to 1 to 6 inputs f of the IC ₆ as 6-bit parallel data. Also, 250μ
The address that changes in the s cycle is also used as the scan clock g of 1 to 40 digits, and the data for selecting the first digit is input to the IC 7 in which the shift register and the digit scan electric drive circuit are integrated, and this is sequentially set to 1 Repeat transfer up to 40 digits. The two ICs 6 and 7 boost the voltage to a voltage sufficient to drive the flat panel 8 by the inverter 9, and cause the flat panel 8 to emit light by the digit scan method.

Therefore, according to the embodiment of the present invention, an IC having an input / output terminal for every five circuits is used as an IC for storing and driving data corresponding to 60 of 5 × 12 dots of one character on a flat display panel. 2 are serially connected for every 10 circuits and the data to be input to this is 6, so that the number of drive circuits used is equal to the number of dots 60 for one character of the flat panel.

(Effect of the Invention) According to the present invention, as described above, an effect that a low-cost circuit configuration without an unnecessary circuit can be achieved and the blink period does not increase as compared with the case of receiving external data in 8-bit parallel. Is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a flat panel driving device according to an embodiment of the present invention. In the figure, 1 ... Three-state buffer, 2 ... RAM, 3 ...
Address switching unit, 4 ... Oscillator, 5 ... Address counter, 6 ... IC composed of shift register and data electrode drive circuit, 7 ... IC composed of shift register and digit electrode drive circuit, 8 ... Dot matrix type plane Display board, 9 ... Inverter, a ... 6-bit paradata,
b ... external address, c ... address line, d ... internal address, e ... clock signal, f ... IC input, g ...
… Scan clock, CS… Chip select, WR
...... write signal, _{A 0} to _{A 9} ...... address.

Claims (1)

[Scope of utility model registration request] 1. A shift in which electrodes corresponding to the 60 dots of a flat display panel forming a character with a dot matrix of 60 dots consisting of 5 dots in the horizontal direction and 12 dots in the vertical direction are driven in a time division manner. A flat panel drive device connected to a drive circuit connected to the output of the register, and displaying characters corresponding to the input data of the shift register when electrodes facing the 60 dots at a predetermined interval are selected. 2. The flat panel driving device according to claim 1, wherein the shift register is divided into 6 corresponding to the time division, and the number of outputs of each shift register among the 6 divided shift registers is 10.