JP3331683B2 - Display drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving circuit for a display device.

[0002]

2. Description of the Related Art A display driving circuit of a dot matrix liquid crystal display device generally has a common signal drive for supplying pulse signals (common signals) having different timings to common electrodes of the liquid crystal display device. It comprises a circuit, a display memory for storing display data for one screen, a segment driver circuit for holding a data read from the display memory and supplying a drive signal to a segment electrode of the liquid crystal display device. ing. This driver circuit includes a display buffer capable of storing data for the number of display dots of the liquid crystal display device. The display buffer is composed of a latch circuit or the like provided corresponding to the segment electrode, but the number of output bits of the display memory is
Since the number of segment electrodes in the horizontal direction of the liquid crystal display device is much larger than that of about 16 bits, the latch circuit is divided into a plurality of groups of, for example, 16 pieces, and the data of the display memory is sequentially time-divided. We write in each group.

In a display driving circuit having such a configuration,
If the data displayed on the liquid crystal display device does not change, data for one screen stored in the display memory may be sequentially written to a plurality of groups of display buffers according to a clock signal having a constant period. .

On the other hand, when switching the display contents of the liquid crystal display device, data is supplied to the last display buffer among a plurality of groups of display buffers, and then the data is supplied to the first display buffer. Until the data is supplied, it is necessary to write display data for one screen to be switched next to the display memory. Therefore, conventionally, the frequency of the clock signal of the control system for writing data to the display memory is
The frequency of the load signal to be supplied to the display buffer needs to be extremely high as compared with the frequency of the load signal, so that the current consumption of the circuit increases.

An object of the present invention is to reduce the power consumption of a circuit by lowering the frequency of a clock signal for writing data.

[0006]

Means for Solving the Problems 1) Display on a display device
A display memory for storing data for a screen, and a plurality of display buffers for storing data read from the display memory. The plurality of display buffers are sequentially switched according to a predetermined clock signal and stored in the display memory. The display drive circuit of the present invention controls the writing of the data in sequence into the plurality of display buffers, and the display drive circuit of the present invention includes a first signal having a predetermined frequency and a second signal having a higher frequency than the first signal. In the case of changing the display screen of the display device and the signal generating means to generate, a load signal based on the second signal is sequentially supplied to the plurality of display buffers, and then the data for the next one screen is written to the display memory. Display control means for sequentially supplying a load signal based on the first signal to a plurality of display buffers when the display of the display device is not changed.

[0007]

According to the present invention, when the display of the display device is changed,
Since the second signal having a higher frequency than the first signal is sequentially supplied to a plurality of display buffers as a load signal, data for one screen is written to the display memory. The period from when the load signal is supplied to the last display buffer in the buffer to when the load signal is next supplied to the first display buffer can be made longer than before. Therefore, the frequency of the clock signal for writing data for writing data for the next one screen into the display memory can be made lower than in the conventional case, and the power consumption of the circuit can be reduced.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram of an electronic device such as an electronic organizer provided with a display drive circuit of the present invention.

The electronic organizer referred to here means that data such as a name, an address, a telephone number and the like are entered by key and stored in a memory, and can be selectively displayed on a display device by operating a display switching key or the like. Refers to equipment.

However, in FIG. 1, the first oscillator 1
The second oscillator 2 generates a 3 kHz clock signal (first signal). The second oscillator 2 generates a 45 kHz clock signal (second signal).
Signal). The control unit 3 is a ROM
A central processing unit that detects a key input signal of the key input unit 5, stores input data or a processing result in the RAM 6, writes display data to the display RAM 7, and the like in accordance with the control program stored in the CPU 4. .

The display buffer driver 8 includes a display RAM.
7 and a plurality of driver circuits for supplying a drive voltage to the common electrodes and the segment electrodes of the dot matrix liquid crystal display device 9. Note that the dot matrix liquid crystal display device 9 is configured by a display element of 32 × 64 dots.

The display control unit 10 includes a signal of 3 KHz generated by the first oscillator 1 and a signal of 45 KHz generated by the second oscillator.
This circuit selects one of the Hz signals and supplies it to the display RAM 7 or the display buffer driver 8 as a data write clock signal or a data load signal.

Here, the specific configurations of the display RAM 7 and the display buffer driver 8 will be described with reference to FIG. still,
A drive circuit for supplying a common signal to the common electrode is omitted. However, the display buffer memory 8 has 32
Four groups of latch circuits (16 latch circuits in each group) 11a to 11d and four groups of driver circuits 12a to 12d having the number of output bits corresponding to the number 64 of segment electrodes of the dot matrix liquid crystal display device 9 of x64 dots It is composed of Each of the latch circuits 11a to 11d supplies the data load clock signals CK1 and CK at the timing shown in FIG.
2, CK3 and CK4, and each of the latch circuits 11a to 11d is synchronized with this data load clock signal.
The display data sequentially sent from the display RAM 7 is written and held.

However, the dot matrix liquid crystal display device 9
When the display screen is not changed, the contents of the display RAM 7 do not change, and the data load clock signals CK1, CK2, CK3, and CK4 generated based on the 3 kHz clock signal generated by the first oscillator 1 are used. Each latch circuit 11
a to 11d.

In this state, when the display switching key is operated by the user and the control unit 3 detects the operation signal of the display switching key shown in FIG. The data for the screen is read, and the read data is written to the display RAM 7. That is, the control unit 3 sends the high-level switching signal 1 to the second oscillator 2 and the display control unit 1 as shown in FIG.
Output to 0. When the clock switching signal 1 becomes high level, the second oscillator 2 operates at 45 KHz as shown in FIG.
Of the clock signal starts.

On the other hand, when the clock switching signal 1 output from the control unit 3 goes high, the display control unit 10 outputs a data load clock signal synchronized with the 45 KHz clock signal output from the second oscillator 2 at that time. CK
1, CK2, CK3, CK4 (X1, X2, X
3, X4), and sequentially supplies the data load clock signals to the latch circuits 11a to 11d (FIG.
(d) to (g)). That is, when the display screen is changed, a clock signal having a higher frequency than before not changing the display screen is supplied to each of the latch circuits 11a to 11d as a data load clock signal.
The display data of M7 is written at high speed.

The display control unit 10 includes a fourth latch circuit 1
After supplying the data load signal CK4 (X4) to 1d,
As shown in FIG.
A clock signal of Hz is output as a data write signal W to the display RAM 7 to write data of one screen data to be changed.

When the writing of data for one screen to the display RAM 7 is completed, the control unit 3 switches the clock switching signal 1 to a low level, and stops the oscillation operation of the second oscillator 2. When the clock switching signal 1 becomes low level, the display control unit 10 selects the 3 KHz clock signal output from the first oscillator 1 and the data load clock signals CK1 and C based on the 3 KHz clock signal.
K2, CK3, and CK4 are sequentially supplied to each of the latch circuits 11a to 11d. Thereafter, the display control unit 10 supplies a data load signal based on the 3 KHz clock signal to each of the latch circuits 11a to 11d until the next instruction to switch the display screen is issued.

As described above, in this embodiment, when the display screen of the liquid crystal display device 9 is changed, a signal having a frequency higher than that of a normal data load clock signal (for example, 45 KHz) is used.
) Are sequentially supplied to the latch circuits 11a to 11d, and then data for the next one screen is written to the display RAM 7 in accordance with the 45 KHz signal. As a result, the data load clock signal (X4) is supplied to the fourth latch circuit 11d during the data write period to the display RAM 7, and then the first latch circuit 11d is supplied.
The period until the data load clock signal CK1 is supplied to a becomes longer than that of the conventional driving method, and the data writing time of the display RAM 7 can be made longer than before. Therefore,
The frequency of the clock signal for data writing, which is determined by the time for writing data to the display RAM 7, can be made lower than before, and the power consumption of the circuit can be reduced.

In the above embodiment, four latch circuits 1
Although the case of the display buffer driver 8 including 1a to 11d and four driver circuits 12a to 12d has been described, the configuration of the display buffer driver 8 is not limited to the configuration of the embodiment but can be applied to other configurations. The display drive circuit of the present invention is particularly suitable for an electronic desk calculator, a data bank, a portable small electronic calculator, etc., which is driven by a battery or the like and needs to suppress power consumption, but is suitable for other devices such as a personal computer and a word processor. Is also applicable.

[0021]

According to the present invention, the following memory is stored in the display memory.
Since the frequency of the clock signal for writing data for writing the data for the screen can be lower than that of the related art, the power consumption of the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a display buffer driver.

FIG. 3 is a timing chart illustrating an operation of the display drive circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st oscillator 2 2nd oscillator 7 Display RAM 8 Display buffer driver 9 Dot matrix liquid crystal display device 10 Display control part

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G09G 3/20 631 G09G 5/00

Claims (3)

(57) [Claims] 1. A display memory for storing data for one screen to be displayed on a display device, and a plurality of display buffers for storing data read from the display memory. A display drive circuit for sequentially supplying a load signal and controlling to sequentially write data stored in the display memory to the plurality of display buffers, comprising: a first signal having a predetermined frequency; Signal generating means for generating a second signal having a high level, and when changing a display screen of the display device,
After sequentially supplying a load signal based on the above signal to the plurality of display buffers, writing data for the next one screen into the display memory and not changing the display of the display device, the first signal And a display control circuit for sequentially supplying a load signal based on the control signal to the plurality of display buffers. 2. The display driving circuit according to claim 1, wherein said display device comprises a dot matrix liquid crystal display device. 3. The signal generation means includes first oscillation means for outputting the first signal, and second oscillation means for outputting the second signal, wherein the second oscillation means 2. The display driving circuit according to claim 1, wherein the oscillating operation is started when the display screen of the display device is changed.