KR20060133240A - Oscillator, liquid crystal display having the same, and driving method thereof - Google Patents

Abstract

An oscillator, a liquid crystal display(LCD) having the same, and a method for driving the LCD are provided to reduce current consumption during a sleep mode by changing a resistor and a capacitor according to a mode signal. An LCD device includes an LCD panel, a driver, a controller, and an oscillator(108). The driver drives signal lines of the LCD panel. The controller controls the driver. The oscillator is used to generate a control signal for driving the driver. The oscillator generates an oscillation signal, whose frequency is changed according to start and end timings of a power saving mode. The oscillator includes an oscillating unit and an amplifier(132). The oscillating unit varies at least one of first and second frequency regulators according to the start and end timings of the power saving mode. The amplifier includes first and second series-connected inverters and amplifies the oscillation signal from the oscillating unit.

Description

Oscillator, liquid crystal display having same and driving method thereof {OSCILLATOR, LIQUID CRYSTAL DISPLAY HAVING THE SAME, AND DRIVING METHOD THEREOF}

1 is a waveform diagram illustrating an oscillation instability area generated when a conventional oscillator is turned off and then turned on.

2 is a circuit diagram illustrating an oscillator according to a first embodiment of the present invention.

FIG. 3 is a diagram for describing a relationship between an oscillation frequency generated by the oscillator illustrated in FIG. 2 and a resistance included in the oscillator.

4 is a waveform diagram illustrating an oscillation frequency generated by the oscillator illustrated in FIG. 2.

5 is a circuit diagram illustrating an oscillator according to a second embodiment of the present invention.

6 is a circuit diagram illustrating an oscillator according to a third embodiment of the present invention.

7 is a circuit diagram illustrating an oscillator according to a fourth embodiment of the present invention.

8 is a block diagram illustrating a liquid crystal display having an oscillator according to the first to fourth embodiments of the present invention.

FIG. 9 is a block diagram illustrating an electronic device having the liquid crystal display shown in FIG. 8.

<Description of Symbols for Main Parts of Drawings>

102: data driver 104: gate driver

106: timing controller 108: oscillator

110: liquid crystal display panel 112, 120: resistance group

114,118,122,126: Multiplexer 116,124: Capacitor Group

130: resonator 132: amplifier

150: input line 152, 154: frequency variable part

160: output line 170: common bus

172: microprocessor unit 174: RAM

176: display unit

The present invention relates to an oscillator, and more particularly, to an oscillator capable of reducing power consumption in a sleep mode, a liquid crystal display having the same, and a driving method thereof.

Recently, as the demand for portable digital products that can operate for a long time with a limited battery increases rapidly, efforts have been made to reduce power consumption of portable digital products. One of the biggest power consumption factors of portable digital products is high resolution, which leads to an increase in current consumption as the frequency of the clock signal increases. To reduce current consumption, portable digital products operate in sleep mode and sleep-by-mode when in power saving mode.

In the standby mode, power is applied to each part of the portable digital product so as to be implemented in response to a user's data input.

In the sleep mode, power is applied only to a configuration for minimum control, for example, a memory, an oscillator, etc. in order to minimize power consumption when not in use for a predetermined time or more.

Power action Memory storage Oscillator Behavior Current consumption Standby mode Χ Χ Χ 20㎂ or less Sleep mode Χ O O 100㎂ or less

When implemented in the standby mode, the oscillator does not operate as shown in Table 1, resulting in lower current consumption compared to the sleep mode. However, if the oscillator is turned on after the oscillator is turned off in the standby mode, an unstable region exists as shown in FIG. 1. There is a problem that a predetermined time is required until this unstable region is stabilized, and the operating speed of the oscillator is lowered. In addition, when the standby mode is implemented, since the data stored in the memory is erased and the data must be transferred to the memory, there is a problem in that the driving time is reduced.

In the case of the sleep mode, since the data is stored in the memory, the image can be realized immediately when the power supply is operated. Therefore, the driving time is faster than the standby mode. However, when the sleep mode is implemented, since the oscillator operates, the current consumption is high.

Accordingly, an object of the present invention is to provide an oscillator capable of reducing current consumption in a sleep mode, a liquid crystal display having the same, and a driving method thereof.

In order to achieve the above object, the liquid crystal display device according to the present invention includes a liquid crystal display panel; A driver for driving signal lines of the liquid crystal display panel; A control unit for controlling the driving unit; And an oscillator for generating an oscillation signal necessary for generating a control signal for controlling the driving unit and for generating an oscillation signal whose frequency is adjusted in response to initiation and release of a power saving mode.

Here, the oscillator includes an oscillator for varying at least one of the first and second frequency variable parts in response to the start and release of the power saving mode, and an oscillation signal of the oscillator. It characterized in that it comprises an amplifier for amplifying and outputting.

The output value of at least one of the first and second frequency variable parts increases when the power saving mode is started, and the value of at least one of the first and second frequency variable parts decreases when the power saving mode is released. It features.

In order to achieve the above object, the oscillator according to the present invention is characterized in that it comprises an oscillator for generating an oscillation signal whose frequency is adjusted in response to the start and release of the power saving mode.

Here, the oscillator may include an oscillator including first and second frequency variable parts; And an amplifier configured to amplify and output the oscillation signal of the oscillator, comprising first and second inverters connected in series.

Meanwhile, a first embodiment of the first frequency variable part includes a resistor connected in parallel with the first inverter, and a first embodiment of the second frequency variable part includes a plurality of capacitors connected in parallel with the amplifier. And a selector configured to select one of the capacitor group in response to initiation and release of the power saving mode.

The second embodiment of the first frequency variable part may include a resistor group including a plurality of resistors connected in parallel with the first inverter, and a selector for selecting one of the resistor groups in response to the start and release of the power saving mode. And the second embodiment of the second frequency variable part is a capacitor connected in parallel with the amplifier.

In addition, a third embodiment of the first frequency variable part may include a resistor group including a plurality of resistors connected in parallel with the first inverter, and a selection unit for selecting any one of the resistor groups in response to the start and release of the power saving mode. The third embodiment of the second frequency variable part includes a capacitor group including a plurality of capacitors connected in parallel with the amplifying unit, and selecting one of the capacitor groups in response to initiation and release of the power saving mode. It characterized in that it comprises a selection unit.

In addition, the fourth embodiment of the first frequency variable part is a variable resistor connected in parallel with the first inverter and variable in response to the start and release of the power saving mode, and the fourth embodiment of the second frequency variable part includes: And a variable capacitor connected in parallel with the amplifier and variable in response to initiation and release of the power saving mode.

Meanwhile, when the power saving mode is started, the output value of at least one of the first and second frequency variable parts increases, and when the power saving mode is released, the output value of at least one of the first and second frequency variable parts decreases. It features.

In order to achieve the above object, an oscillator driving method according to the present invention comprises a first step of generating a frequency controlled first oscillation signal in response to a power saving mode start signal; And a second step of changing the changed frequency into a second oscillation signal of the original frequency in response to the power saving mode release signal.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 9.

2 is a circuit diagram illustrating an oscillator according to a first embodiment of the present invention.

Referring to FIG. 2, the oscillator 108 according to the first embodiment of the present invention includes a resonator 130 resonating to a current of a specific frequency and an amplifier 132 continuously supplying a resonant current.

The amplifier 132 includes first and second inverters INV1 and INV2 connected in series to the input line 150 and the output line 160.

The resonator 130 includes a capacitor C connected in parallel with the amplifier 132 and a frequency variable part located between the node n and the input line 150. The resonator 130 determines the frequency by the phase difference by the delay time set by the capacitor C and the frequency variable part.

That is, the frequency generated by the oscillator 108 by the resonator 130 is inversely proportional to the value of the resistor R and the capacitor C as shown in Equations 1 and 3.

, 여기서 χ는 상수이다.

Where χ is a constant.

By adjusting this resistance value or capacitor value, the oscillator frequency is adjusted to lower the current consumption during sleep mode implementation.

To this end, the frequency variable part includes a plurality of resistance groups 112 and a multiplexer 114 connected to the resistance groups 112.

In the resistor group 112, a plurality of resistors R1 to Rk having different resistance values are connected between the node n and an input terminal of the multiplexer 114. The multiplexer 114 selects and outputs a relatively high resistance in response to the sleep mode start signal SS, and selects and outputs a relatively low resistance in response to the sleep mode release signal SC.

As described above, the relatively high resistance is selected by the frequency variable in response to the sleep mode start signal SS, so that the oscillator 108 generates the oscillation signal OSC1 having a relatively low frequency as shown in FIG. 4. do. In addition, since a relatively low resistance is selected in response to the sleep mode release signal SC, the oscillator 108 generates an oscillation signal OSC2 having a relatively high frequency, that is, an oscillation signal required for normal driving.

As described above, the oscillator according to the first embodiment of the present invention generates an oscillation signal having a relatively high frequency in response to the sleep mode release signal SC and generates a relatively low frequency in response to the sleep mode start signal SS. Generates an oscillation signal. The oscillator 108 may reduce the current consumption of at least 30% in the sleep mode as shown in Table 2.

Frequency (R, C change) 240㎑ 200㎑ 160㎑ 120㎑ Current consumption 44.3㎂ 40.0㎂ 35.8㎂ 30.1㎂

As a result, the oscillation stability time, command initialization time, graphic data writing time, etc. of the oscillator during oscillation after the oscillator 108 is turned off can be saved. This reduces the load on the electronic device with the oscillator and assigns it to different program operating times, thus improving design freedom.

5 is a circuit diagram illustrating an oscillator according to a second embodiment of the present invention.

Referring to FIG. 5, the oscillator 108 according to the second embodiment of the present invention includes the same components except for a resonance part having a frequency variable part made of a capacitor whose capacitance is adjusted in comparison with the oscillator shown in FIG. 2. Equipped. Accordingly, detailed description of the same components will be omitted.

The resonator 130 includes a frequency variable unit 130 connected in parallel with the amplifier 132 and a resistor R positioned between the node n and the input line 150.

The frequency variable part 130 includes a plurality of capacitor groups 116 and a multiplexer 118 connected to the capacitor group 116.

In the capacitor group 116, a plurality of capacitors C1 to Ck having different capacitance values are connected between the second node n2 and the input terminal of the multiplexer 114. The multiplexer 114 selects and outputs a capacitor having a relatively high capacitance in response to the sleep mode start signal SS, and selects a capacitor having a relatively low capacitance in response to the sleep mode release signal SC. Output

As described above, the capacitor having a relatively high capacitance value is selected by the frequency variable part in response to the sleep mode start signal SS so that the oscillator 108 has an oscillation signal having a relatively low frequency as shown in FIG. 4. OSC1). In addition, since the capacitor having a relatively low capacitance is selected in response to the sleep mode release signal SC, the oscillator 108 generates an oscillation signal OSC2 having a relatively high frequency, that is, an oscillation signal required for normal driving. .

As described above, the oscillator according to the second embodiment of the present invention generates an oscillation signal having a relatively high frequency in response to the sleep mode release signal and generates an oscillation signal having a relatively low frequency in response to the sleep mode initiation signal. . This oscillator reduces the current consumption of the entire system.

6 is a circuit diagram illustrating an oscillator according to a third embodiment of the present invention.

Referring to FIG. 6, the oscillator 108 according to the third embodiment of the present invention has the same components except for the resonance part having the first and second frequency variable parts as compared to the oscillator shown in FIG. 2. Accordingly, detailed description of the same components will be omitted.

The resonator 130 includes a first frequency variable part 152 positioned between the node n and the input line 150, and a second frequency variable part 154 connected in parallel with the amplifier 132. do.

The first frequency variable part 152 includes a plurality of resistance groups 120 and a first multiplexer 122 connected to the resistance groups 120.

In the resistor group 120, a plurality of resistors R1 to Rk having different resistance values are connected to the input terminal of the node n and the first multiplexer 122. The first multiplexer 122 selects and outputs a relatively high resistance in response to the sleep mode start signal SS, and selects and outputs a relatively low resistance in response to the sleep mode release signal SC.

The second frequency variable part 154 includes a plurality of capacitor groups 124 and a second multiplexer 126 connected to the capacitor group 124.

In the capacitor group 124, a plurality of capacitors C1 to Ck having different capacitance values are connected to input terminals of the second node n2 and the second multiplexer 126. The second multiplexer 126 selects and outputs a capacitor having a relatively high capacitance in response to the sleep mode start signal SS, and outputs a capacitor having a relatively low capacitance in response to the sleep mode release signal SC. Select and print.

As described above, in response to the sleep mode start signal SS, the resistor R and the capacitor C having the relatively high resistance value and the capacitance value are selected by the first and second frequency variable parts 152 and 154 so that the oscillator ( 108 generates an oscillation signal OSC1 having a relatively low frequency. Then, in response to the sleep mode release signal SC, a resistor R and a capacitor C having a relatively low resistance value and a capacitance value are selected, so that the oscillator 108 has an oscillation signal OSC2 having a relatively high frequency. That is, it generates the oscillation signal necessary for normal driving.

As described above, the oscillator according to the third embodiment of the present invention generates an oscillation signal having a relatively high frequency in response to the sleep mode release signal and generates an oscillation signal having a relatively low frequency in response to the sleep mode initiation signal. . This oscillator reduces the current consumption of the entire system.

7 is a circuit diagram illustrating an oscillator according to a fourth embodiment of the present invention.

Referring to FIG. 7, the oscillator 108 according to the fourth exemplary embodiment of the present invention has the same components as the oscillator illustrated in FIG. 2 except for the resonance part having the variable resistor and the variable capacitor. Accordingly, detailed description of the same components will be omitted.

The resonator 130 includes a variable resistor VAR positioned between the node n and the input line 150, and a variable capacitor VAC connected in parallel with the amplifier 132.

The variable resistor VAR is variable to output a relatively high resistance value in response to the sleep mode start signal SS and to output a relatively low resistance value in response to the sleep mode release signal SC.

The variable capacitor VAC is variable to output a relatively high capacitor value in response to the sleep mode start signal SS and to output a relatively low capacitor value in response to the sleep mode release signal SC.

As described above, the oscillator 108 generates an oscillation signal having a relatively low frequency by outputting a relatively high resistance value and a capacitance value to the variable resistor VAR and the variable capacitor VAC in response to the sleep mode start signal SS. OSC1). In response to the sleep mode release signal SC, the oscillator 108 generates an oscillator signal OSC2 having a relatively high frequency, that is, an oscillation signal required for normal driving by outputting a relatively low resistance value and a capacitance value. .

As described above, the oscillator according to the fourth embodiment of the present invention generates an oscillation signal having a relatively high frequency in response to the sleep mode release signal and generates an oscillation signal having a relatively low frequency in response to the sleep mode initiation signal. . This oscillator reduces the current consumption of the entire system.

8 is a block diagram illustrating a liquid crystal display having an oscillator according to the first to fourth embodiments of the present invention.

8 illustrates a data driver 102 for driving the data line DL of the liquid crystal display panel 110 and a gate driver for driving the gate line GL of the liquid crystal display panel 110. 104 and a timing controller 106 for controlling the gate driver 104 and the data driver 102.

The timing controller 106 supplies the pixel data signal Data input from the outside to the data driver 102. In addition, the timing controller 106 controls each of the gate driver 104 and the data driver 102 using the oscillation signal generated by the oscillator 108 shown in FIG. 2, 5, 6, or 7. The gate control signal GCS and the data control signal DCS are generated.

The gate control signals GCS include a gate start pulse GSP, a gate shift clock signal GSC, a gate output enable signal GOE, and the like. The data control signals DCS include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like.

The gate driver 104 sequentially applies the high logic voltage VGH of the gate signal to the gate lines GL1 to GLn every horizontal period H in response to the gate control signals GCS from the timing controller 106. Supply. Accordingly, the gate driver 104 causes the thin film transistor TFT connected to the gate lines GL1 to GLn to be driven in units of the gate line GL.

The data driver 102 generates one horizontal line of pixel data signal Data for each horizontal period H1, H2, ... in response to the data control signals DCS from the timing controller 106. It supplies to (DL1-DLm).

The liquid crystal display panel 110 is formed by bonding a thin film transistor substrate and a color filter substrate to each other with a liquid crystal interposed therebetween. The liquid crystal display panel 110 includes liquid crystal cells Clc independently driven by the thin film transistor TFT in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor TFT supplies a pixel signal from the data line DL to the liquid crystal cell Clc in response to a scan signal from the gate line GL.

FIG. 9 is a block diagram illustrating an electronic device having the liquid crystal display shown in FIG. 8.

The electronic device illustrated in FIG. 9 includes a microprocessor unit (MPU) 172, a random access memory (RAM) 174 connected to the MPU 172 through a bus 170, and a display unit. 176 and other portions 178 are provided. Here, the electronic device will be described by taking a mobile communication terminal as an example.

The MPU 172 performs processing and control for voice call and data communication of the mobile communication terminal and processes an operation for adjusting the sleep period.

The RAM 174 stores temporary data generated during execution of various programs.

The display unit 176 displays status information generated during operation of the mobile communication terminal, characters such as numbers, moving images, and still images. The display unit 176 mainly uses a liquid crystal display (LCD).

The guitar unit 178 is connected to the MPU 172 through a common bus 170, for example a peripheral device such as a camera, a keypad.

The electronic device cuts off the power provided in the remaining components except for the minimum control portion during the sleep period to minimize power consumption.

As described above, the oscillator according to the present invention, the liquid crystal display device having the same, and the driving method of the liquid crystal display device can reduce the current consumption in the sleep mode by changing the resistance and the capacitor in response to the mode signal.

In addition, the oscillator according to the present invention, the liquid crystal display device having the same, and the driving method of the liquid crystal display device are also applicable to the sub-operation of one set of eight color modes in which the display characteristics are not significantly reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (15)

A liquid crystal display panel; A driver for driving signal lines of the liquid crystal display panel; A control unit for controlling the driving unit; And an oscillator which is used to generate a control signal for controlling the driver and generates an oscillation signal whose frequency is adjusted in response to initiation and release of a power saving mode. The method of claim 1, The oscillator An oscillator for varying at least one of the first and second frequency variable parts in response to initiation and release of the power saving mode; And an amplifier comprising a first inverter and a second inverter connected in series to amplify and output the oscillation signal of the oscillator. The method of claim 2, The output value of at least one of the first and second frequency variable parts increases when the power saving mode is started, and the value of at least one of the first and second frequency variable parts decreases when the power saving mode is released. Liquid crystal display. And an oscillator for generating an oscillation signal whose frequency is adjusted in response to initiation and release of the power saving mode. The method of claim 4, wherein The oscillator An oscillator including first and second frequency variable parts; And an amplifier comprising a first inverter and a second inverter connected in series to amplify and output the oscillation signal of the oscillator. The method of claim 5, The first frequency variable part And a resistor connected in parallel with the first inverter, The second frequency variable part And a capacitor group including a plurality of capacitors connected in parallel with the amplifying unit, and a selection unit for selecting any one of the capacitor groups in response to initiation and release of the power saving mode. The method of claim 5, The first frequency variable part A resistor group comprising a plurality of resistors connected in parallel with the first inverter, and a selection unit for selecting any one of the resistor groups in response to the start and release of the power saving mode; The second frequency variable part An oscillator, characterized in that the capacitor is connected in parallel with the amplifier. The method of claim 5, The first frequency variable part A resistor group comprising a plurality of resistors connected in parallel with the first inverter, and a selection unit for selecting any one of the resistor groups in response to the start and release of the power saving mode; The second frequency variable part And a capacitor group including a plurality of capacitors connected in parallel with the amplifying unit, and a selection unit for selecting any one of the capacitor groups in response to initiation and release of the power saving mode. The method of claim 5, The first frequency variable part A variable resistor connected in parallel with the first inverter and variable in response to initiation and release of the power saving mode; The second frequency variable part And a variable capacitor connected in parallel with the amplifier and variable in response to initiation and release of the power saving mode. The method of claim 5, The output value of at least one of the first and second frequency variable parts increases when the power saving mode is started, and the output value of at least one of the first and second frequency variable parts decreases when the power saving mode is released. Oscillator. A first step of generating a frequency controlled first oscillation signal in response to the power saving mode start signal; And a second step of changing the changed frequency into a second oscillation signal of the original frequency in response to the power saving mode release signal. The method of claim 11, The first step is a step of selecting a capacitor having a relatively high capacitance value of the capacitor group consisting of a plurality of capacitors included in the oscillator in response to the power saving mode start signal, The second step is a step of selecting a capacitor having a relatively low capacitance value of the capacitor group consisting of a plurality of capacitors included in the oscillator in response to the power saving mode release signal. The method of claim 11, The first step is a step of selecting a resistor having a relatively high resistance value of the resistance group consisting of a plurality of resistors included in the oscillator in response to the power saving mode start signal, The second step is a step of selecting a resistor having a relatively low capacitance value of the resistor group consisting of a plurality of resistors included in the oscillator in response to the power saving mode release signal. The method of claim 11, The first step may include selecting at least one resistor or capacitor having a relatively high value from a resistor group including a plurality of resistors and a capacitor group including a plurality of capacitors in response to the power saving mode start signal. Wow; The second step may be a step of selecting a resistor or a capacitor having a relatively low value among a resistor group consisting of a plurality of resistors and a capacitor group consisting of a plurality of capacitors in response to the power saving mode release signal. Oscillator drive method. The method of claim 11, The first step is to change at least one of the variable resistor and the variable capacitor included in the oscillator to have a relatively high value in response to the power saving mode start signal, And the second step of varying at least one of a variable resistor and a variable capacitor included in the oscillator to have a relatively low value in response to the power saving mode release signal.

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