KR100893854B1 - A liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of reducing size and reducing power consumption, comprising: a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines crossing each other; A gate driver for driving the gate lines; DRAM for storing data for the image to be displayed on the liquid crystal panel (DRAM: Dynamic Random Access Memory); A data driver receiving data from the DRAM and supplying a predetermined pixel voltage to the data lines according to the data; An oscillator that is turned on or off in response to a plurality of power saving mode signals supplied from the outside, and outputs a reference signal when turned on; And a controller configured to divide the reference signal from the oscillator to generate a control signal for controlling the gate driver and the data driver and a refresh signal for refreshing the DRAM.

LCD, DRAM, Oscillator, Power Saving Mode

Description

Liquid crystal display device

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

2 is a diagram illustrating a reference signal output unit according to a first embodiment of the present invention.

3 is a diagram illustrating a power saving state of a liquid crystal display according to first to third power saving mode signals supplied to FIG. 2;

FIG. 4 is a view illustrating another power saving state of the liquid crystal display according to the first to third power saving mode signals supplied to FIG. 2.

5 is a diagram illustrating a reference signal output unit according to a second exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a power saving state of a liquid crystal display according to the first to fourth power saving mode signals supplied to FIG. 5.

* Explanation of symbols on the main parts of the drawings

DR: DRAM TC: Timing Controller

DD: data driver GD: gate driver

GL: Gate Line DL: Data Line

100: liquid crystal panel Clc: liquid crystal capacitor

Cst: auxiliary capacitor Vcom: common voltage

TFT: Thin Film Transistor

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that can reduce the size and power consumption.

The liquid crystal display displays an image by adjusting light transmittance of pixel cells according to a video signal. In an active matrix liquid crystal display, switching elements are formed in each pixel cell, which is advantageous for displaying a moving image. As the switching device, a thin film transistor (hereinafter referred to as "TFT") is mainly used.

Such a liquid crystal display includes a plurality of gate lines and a plurality of data lines arranged to cross each other.

A conventional liquid crystal display device displays an image by supplying data stored in a memory onto a liquid crystal panel. In the related art, a conventional random random memory (SRAM) is used as the memory.

However, such an SRAM has a disadvantage of implementing a high resolution liquid crystal display because of the large memory area.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device that can reduce the size by using a DRAM instead of a conventional SRAM.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines crossing each other; A gate driver for driving the gate lines; DRAM for storing data for the image to be displayed on the liquid crystal panel (DRAM: Dynamic Random Access Memory); A data driver receiving data from the DRAM and supplying a predetermined pixel voltage to the data lines according to the data; An oscillator that is turned on or off in response to a plurality of power saving mode signals supplied from the outside, and outputs a reference signal when turned on; And a controller configured to divide the reference signal from the oscillator to generate a control signal for controlling the gate driver and the data driver and a refresh signal for refreshing the DRAM.

In addition, a liquid crystal display according to the present invention for achieving the above object, the liquid crystal panel having a plurality of pixels defined by a plurality of gate lines and a plurality of data lines that cross each other; A gate driver for driving the gate lines; DRAM for storing data for the image to be displayed on the liquid crystal panel (DRAM: Dynamic Random Access Memory); A data driver receiving data from the DRAM and supplying a predetermined pixel voltage to the data lines according to the data; A reference signal output unit which selects and outputs any one of a plurality of reference signals having different frequencies according to an external power saving mode signal; And a controller configured to divide the reference signal from the reference signal output unit to generate a control signal for controlling the gate driver and the data driver and to generate a refresh signal for refreshing the DRAM. do.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal panel 100 in which a plurality of pixel cells (not shown) are formed for displaying an image, and the liquid crystal panel 100. Has a gate driver GD and a data driver DD.

In the liquid crystal panel 100, a plurality of gate lines GL and a plurality of data lines DL are formed to cross each other, and the pixels defined by crossing the gate lines GL and the data lines DL are defined. The pixel cell is formed in an area.

The pixel cell may include a thin film transistor TFT for switching a gray voltage from a data line in response to a scan pulse from a gate line, and a pixel electrode for displaying an image by receiving a gray voltage from the thin film transistor TFT. And a common electrode positioned to face the pixel electrode and supplied with the common voltage Vcom, and a liquid crystal layer formed between the pixel electrode and the common electrode.

In addition, the pixel cell includes a liquid crystal capacitor Clc and a storage capacitor Cst.

The gate driver GD outputs a scan pulse for driving the gate lines GL, and the data driver DD supplies data necessary for pixel cells to the data lines DL.

In practice, the data driver DD is supplied with data for one line (data to be supplied to pixel cells arranged in one pixel row) every horizontal period, and for each of the data for one line Select the preset gradation voltage. Then, the grayscale voltages of the selected one horizontal line are supplied to each data line DL.

The data is stored in a dynamic random access memory (DRAM). That is, data corresponding to an image of every frame is stored in the DRAM DR. The data driver DD latches data corresponding to one horizontal line from the DRAM DR. After selecting a gray voltage corresponding to each data corresponding to minutes, the predetermined gray voltages are simultaneously supplied to the data lines.

The timing controller TC divides a reference signal to generate a control signal for controlling the gate driver GD and the data driver DD and a refresh signal for refreshing the DRAM DR.

That is, in the present invention, the DRAM DR is used instead of the existing SRAM. In order to store data in the DRAM DR, the DRAM DR needs to be periodically refreshed. To this end, the timing controller TC generates a refresh signal and supplies the refresh signal to the DRAM DR so that the DRAM DR can store data.

In addition, the liquid crystal display according to the present invention further includes logic power for generating a logic power required to drive the oscillator OSC, the gate driver, the data driver DD, and the timing controller TC.

The timing controller TC divides a reference signal to generate a plurality of control signals and a refresh signal. The reference signal is output from a reference signal output unit.

2 is a diagram illustrating a reference signal output unit according to a first embodiment of the present invention. As shown in the figure, the reference signal output unit 200 includes an oscillator OSC.

The oscillator OSC is turned on or off in response to power saving mode signals from the outside, and outputs a reference signal to the timing controller TC when the oscillator OSC is turned on.

The power saving mode signal may include a first power saving mode signal pd1 for turning off the screen of the liquid crystal panel 100; A second power saving mode signal pd2 for turning off the screen of the liquid crystal panel 100 and the oscillator; And a third power saving mode signal pd3 for turning off the screen, the oscillator, and the logic power of the liquid crystal panel 100.

3 is a diagram illustrating a power saving state of a liquid crystal display according to the first to third power saving mode signals supplied to FIG. 2.

As shown in FIG. 3, in the normal mode, the display (ie, the screen of the liquid crystal panel 100), the oscillator OSC, and the logic power are all on.

In the first power saving mode, only the display is off and the oscillator and logic power are on.

In the second power save mode, the display and oscillator are off and only logic power is on.

In the third power saving mode, the display, oscillator, and logic power are all off.

FIG. 4 is a view illustrating another power saving state of the liquid crystal display according to the first to third power saving mode signals supplied to FIG. 2.

As shown in FIG. 4, in the normal mode, the display (that is, the screen of the liquid crystal panel 100), the oscillator OSC, and the logic power are all on.

In the first power saving mode, only the display is off and the oscillator (OSC) and logic power are on.

In the second power saving mode, only the display is off and the oscillator and logic power are on.

In the third power saving mode, the display, oscillator (OSC), and logic power are all off.

5 is a diagram illustrating a reference signal output unit according to a second exemplary embodiment of the present invention, and FIG. 6 is a diagram illustrating a power saving state of a liquid crystal display according to the first to fourth power saving mode signals supplied to FIG. 5.

As shown in FIG. 5, the reference signal output unit 500 according to an embodiment of the present invention may be controlled according to a plurality of power saving mode signals to output a first reference signal f1 and an oscillator OSC1. ; A second oscillator OSC2 controlled according to one of the power saving mode signals and outputting a second reference signal f2 having a frequency different from that of the first reference signal f1; And a selector MUX controlled by a power saving mode signal for controlling the second reference signal f2 to select and output any one of the first and second reference signals f1 and f2. .

Here, the frequency of the second reference signal f2 is lower than the frequency of the first reference signal f1.

The reference signal output unit according to the second embodiment of the present invention may reduce power consumption by selecting one of two reference signals according to a power saving mode signal from the outside.

In other words, a reference signal is required to refresh the DRAM DR. The refresh signal required to refresh the DRAM DR may be generated using a reference signal having a relatively low frequency. The power consumption can be reduced by using the second reference signal f2 having a relatively lower frequency than the first reference signal f1 without using (f1).

In the power saving mode, as shown in FIG. 6, in the normal mode, the display (that is, the screen of the liquid crystal panel 100), the first oscillator OSC1, and the logic power are on, and the second oscillator ( OSC2) is off.

In the first power saving mode, the display and the second oscillator OSC2 are in an off state, and the first oscillator OSC1 and the logic power are in an on state.

In the second power saving mode, the display and the first oscillator OSC1 are in an off state, and the second oscillator OSC2 and the logic power are in an on state.

In the third power saving mode, the display, the first oscillator OSC1, and the second oscillator OSC2 are in an off state, and only the logic power is in an on state.

In the fourth power saving mode, the display, the first oscillator OSC1, the second oscillator OSC2, and the logic power are all turned off.

In order to perform these four power saving modes, first to fourth power saving mode signals pd1 to pd4 are supplied to the first and second oscillators OSC1 and OSC2.

That is, the power saving mode signal includes: a first power saving mode signal pd1 for turning off the screen of the liquid crystal panel 100 and the second oscillator OSC2; A second power saving mode signal pd2 for turning off the screen of the liquid crystal panel 100 and the first oscillator OSC1; A third power saving mode signal pd3 for turning off the screen, the first oscillator OSC1, and the second oscillator OSC2 of the liquid crystal panel 100; The screen of the liquid crystal panel 100 includes a first oscillator OSC1, a second oscillator OSC2, and a fourth power saving mode signal pd4 for turning off logic power.

The first oscillator OSC1 is maintained in an on state when the first power saving mode signal pd1 is in an active state, for example, a high state, and outputs a first reference signal f1, and the remaining second to fourth power savings are performed. Any one of the mode signals pd2 to pd4 is kept in an off state when in an active state, for example, a high state, and no longer outputs the first reference signal.

The second oscillator OSC2 is maintained in an on state when the second power save mode signal pd2 is in an active state, for example, a high state, and outputs a second reference signal f2. ) Is turned off when it is in an inactive state, for example, a low state, and no longer outputs the second reference signal f2.

The selector MUX receives the first reference signal f1 from the first oscillator OSC1 and the second reference signal f2 from the second oscillator OSC2, and receives a second power saving mode signal from the outside. The second reference signal f2 is output when pd2 is high.

Herein, the operation of the liquid crystal display in each power saving mode will be described.

When the user selects the first power save mode, only the first power save mode signal pd1 remains high and the remaining second to fourth power save mode signals pd2 to pd4 go low. Then, the first oscillator OSC1 is turned on by the first power saving mode signal pd1 in the high state, and the second oscillator OSC2 is turned off. Accordingly, the first reference signal f1 is output from the first oscillator OSC1 and supplied to the selector MUX.

At this time, since the second power save mode signal pd2 is in a low state, the selector MUX supplied with the second power save mode signal pd2 outputs the first reference signal f1.

The first reference signal f1 output from the selector MUX is supplied to the timing controller TC. Then, the timing controller TC divides the first reference signal f1 to generate a plurality of control signals and refresh signals.

The control signal is supplied to the gate driver GD and the data driver DD driving the liquid crystal panel 100 so that a screen is displayed on the liquid crystal panel 100. The refresh signal is supplied to the DRAM DR to refresh the DRAM DR so that data stored in the DRAM DR is maintained.

On the other hand, the control signal generated in the first power saving mode stops the operation of the gate driver GD and the data driver DD so that the screen is not displayed on the liquid crystal panel 100.

The liquid crystal display includes a booster (not shown) for boosting power from an external source to generate power for the gate driver GD and the data driver DD. The booster provided in the mobile phone boosts the voltage from the battery and supplies it to the gate driver GD and the data driver DD.

When the boosted power is supplied, the gate driver GD and the data driver DD can operate. In the normal mode and the first power saving mode, the booster maintains the operating state. However, since the gate driver and the data driver do not operate in the first power saving mode, the screen is turned off. That is, the reason why the screen is turned off in the first power saving mode is not related to whether the booster is operated or not, and whether the gate driver and the data driver are operated.

When the user selects the second power save mode, only the second power save mode signal pd2 remains high, and the remaining first, third, and fourth power save mode signals pd1, pd3, and pd4 go low. . Then, the first oscillator OSC1 is turned off by the first power save mode signal pd1 in the low state, and the second oscillator OSC2 is turned on by the second power save mode signal pd2 in the high state. Accordingly, the second reference signal f2 is output from the second oscillator OSC2 and supplied to the selector MUX.

At this time, since the second power save mode signal pd2 is in a high state, the selector MUX supplied with the second power save mode signal pd2 outputs the second reference signal f2.

The second reference signal f2 output from the selector MUX is supplied to the timing controller TC. Then, the timing controller TC generates a refresh signal using the second reference signal f2, but does not generate a control signal. That is, in order for the timing controller TC to generate a control signal, a first reference signal f1 having a relatively high frequency is required. In the second power saving mode, the second reference signal having the relatively low frequency ( Since f2) is supplied, only the refresh signal is generated without generating the control signal.

Accordingly, in the second power saving mode, the gate driver GD and the data driver DD do not operate, and thus the screen of the liquid crystal panel 100 is turned off.

In the second power saving mode, since the second reference signal f2 having a relatively low frequency is used, power consumption can be reduced.

When the user selects the third power save mode, only the third power save mode signal pd3 remains high and the remaining first, second, and fourth power save mode signals pd1, pd2, and pd4 go low. . As a result, the first and second oscillators OSC1 and OSC2 are turned off, and the first and second reference signals f1 and f2 are not output from the first and second oscillators OSC1 and OSC2.

Accordingly, the timing controller TC does not generate the control signal and the refresh signal.

Accordingly, in the third power saving mode, the gate driver GD and the data driver DD do not operate, and thus the screen of the liquid crystal panel 100 is turned off.

When the user selects the fourth power saving mode, only the fourth power saving mode signal pd4 remains high, and the remaining first to third power saving mode signals pd1 to pd3 go low. As a result, the first and second oscillators OSC1 and OSC2 are turned off, and the first and second reference signals f1 and f2 are not output from the first and second oscillators OSC1 and OSC2.

On the other hand, since the logic power is turned off in this fourth power saving mode, the liquid crystal display device enters the maximum power saving mode.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The liquid crystal display according to the present invention as described above has the following effects.

In the present invention, by using a DRAM instead of the existing SRAM, the size of the liquid crystal display device can be reduced.

In this case, a refresh signal is required to maintain the data stored in the DRAM, and the power consumption can be reduced by generating the refresh signal using a second reference signal having a relatively low frequency.

Claims (13)

A liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines crossing each other; A gate driver for driving the gate lines; DRAM for storing data for the image to be displayed on the liquid crystal panel (DRAM: Dynamic Random Access Memory); A data driver receiving data from the DRAM and supplying a predetermined gray scale voltage to the data lines according to the data; An oscillator that is turned on or off in response to a plurality of power saving mode signals supplied from the outside, and outputs a reference signal when turned on; A controller configured to divide the reference signal from the oscillator to generate a control signal for controlling the gate driver and the data driver and a refresh signal for refreshing the DRAM; And A logic power for generating a logic power source for driving the oscillator, gate driver, data driver, and control unit; The power saving mode signals, A first power saving mode signal for turning off the screen of the liquid crystal panel; A second power saving mode signal for turning off the screen of the liquid crystal panel and the oscillator; And, And a third power saving mode signal for turning off the screen, the oscillator, and the logic power of the liquid crystal panel. delete delete A liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and a plurality of data lines crossing each other; A gate driver for driving the gate lines; DRAM for storing data for the image to be displayed on the liquid crystal panel (DRAM: Dynamic Random Access Memory); A data driver receiving data from the DRAM and supplying a predetermined gray scale voltage to the data lines according to the data; An oscillator that is turned on or off in response to a plurality of power saving mode signals supplied from the outside, and outputs a reference signal when turned on; A controller configured to divide the reference signal from the oscillator to generate a control signal for controlling the gate driver and the data driver and a refresh signal for refreshing the DRAM; And A logic power for generating a logic power source for driving the oscillator, gate driver, data driver, and control unit; The power saving mode signals, A first power saving mode signal for turning off the screen of the liquid crystal panel; And a second power saving mode signal for turning off the screen, the oscillator, and the logic power of the liquid crystal panel. The method according to claim 1 or 4, Wherein each of the power saving mode signals turns off the gate driver and the data driver to turn off the screen of the liquid crystal panel. A liquid crystal panel having a plurality of pixels defined by a plurality of gate lines and a plurality of data lines crossing each other; A gate driver for driving the gate lines; DRAM for storing data for the image to be displayed on the liquid crystal panel (DRAM: Dynamic Random Access Memory); A data driver receiving data from the DRAM and supplying a predetermined gray scale voltage to the data lines according to the data; A reference signal output unit which selects and outputs any one of a plurality of reference signals having different frequencies according to an external power saving mode signal; And, A control unit for dividing the reference signal from the reference signal output unit to generate a control signal for controlling the gate driver and the data driver, and a refresh signal for refreshing the DRAM; The reference signal output unit, A first oscillator controlled according to a plurality of power saving mode signals and outputting a first reference signal; And a second oscillator controlled according to any one of the power saving mode signals and outputting a second reference signal having a frequency different from that of the first reference signal. delete The method of claim 6, The reference signal output unit, And a selection unit which is controlled by a power saving mode signal for controlling the reference signal output unit and selects and outputs any one of the first and second reference signals. The method of claim 6, And a frequency of the second reference signal is lower than a frequency of the first reference signal. The method of claim 6, And a logic power for generating logic power required to drive the reference signal output unit, the gate driver, the data driver, and the controller. The method of claim 10, The power saving mode signals, A first power saving mode signal for turning off the screen of the liquid crystal panel; A second power saving mode signal for turning off the screen and the first oscillator of the liquid crystal panel; A third power saving mode signal for turning off the screen, the first oscillator, and the second oscillator of the liquid crystal panel; And, And a fourth power saving mode signal for turning off the screen, the first oscillator, the second oscillator, and the logic power of the liquid crystal panel. The method of claim 11, And a first power saving mode signal is supplied to the first oscillator, and a second power saving mode signal is supplied to the second oscillator. The method of claim 12, And the first to fourth power save mode signals indicate an inactive state when one signal indicates an active state.

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