JP2007286237A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device that can decrease consumed power without decreasing an aperture ratio. <P>SOLUTION: The device includes a pixel memory circuit 58 as a memory circuit that can retain one-bit data in each pixel unit comprising three sub-pixels for R, G, B. When the device is switched from normal display to memory driving, binarized data for image display during a memory driving period are stored in the pixel memory circuit 58. A first supply voltage VAL and a second supply voltage VBL are applied to the pixel memory circuit 58, wherein these voltages are varied by a duty ratio. During memory driving, a common voltage is applied to liquid crystal capacitors 51R, 51G, 51B based on the first supply voltage VAL or the second supply voltage VBL according to the data stored in the pixel memory circuit 58 to display an image. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a display device incorporating a pixel circuit having a memory function.

2. Description of the Related Art Conventionally, liquid crystal display devices are required to reduce power consumption. In order to reduce power consumption, for example, when displaying a screen with little image change such as time display on a mobile phone, the cycle of writing a video signal in the liquid crystal capacitor in the pixel formation unit for displaying pixels is lengthened. Things have been done. However, if the writing period of the video signal to the liquid crystal capacitor is increased, the applied voltage must be held for a long time in the liquid crystal capacitor. For this reason, in the liquid crystal display device as described above, a circuit having a memory function (hereinafter referred to as “pixel memory circuit”) is provided in each pixel formation portion so that the voltage applied to the liquid crystal capacitance is maintained. It has been.
JP 2004-86153 A

  By the way, when a circuit such as a pixel memory circuit is formed in the pixel region, the aperture ratio decreases according to the area of the circuit. In a general color liquid crystal display device, one pixel is formed by three sub-pixels for R (Red: red), G (Green: green), and B (Blue: blue). As schematically shown in FIG. 11, pixel memory circuits 58R, 58G, and 58B are provided for each of the sub-pixels 5R, 5G, and 5B. For this reason, in the liquid crystal display device including the pixel memory circuit, the aperture ratio is remarkably lowered.

  Therefore, an object of the present invention is to provide a display device that can reduce power consumption without reducing the aperture ratio.

The first invention provides a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals. A display device comprising a plurality of pixel forming portions each including three types of pixel forming portions arranged in a matrix corresponding to intersections of lines and the plurality of scanning signal lines and displaying predetermined three primary colors. ,
Provided for each pixel unit that includes the three types of pixel forming portions as a set, and binarized data based on a video signal transmitted by a video signal line corresponding to one of the three types of pixel forming portions is captured. A memory circuit for storing,
In the predetermined display mode, the pixel values of the three types of pixel forming units included in each pixel unit are in accordance with the value of the binarized data stored in the storage circuit provided in each pixel unit. It is characterized by being set to a common value.

According to a second invention, in the first invention,
Having a first display mode and a second display mode;
For each pixel unit, it is provided with a switching circuit for causing the three types of pixel forming portions to take in pixel values according to the display mode,
The switching circuit is
In the first display mode, the three types of pixel formation units are caused to capture the values of the video signals transmitted by the video signal lines corresponding to the three types of pixel formation units as pixel values,
In the case of the second display mode, the three types of the pixel values that are set according to the value of the binarized data stored in the storage circuit provided in the corresponding pixel unit are used as the common pixel values. It is characterized by being taken into the pixel formation portion.

According to a third invention, in the second invention,
A duty ratio setting circuit for setting a first duty ratio and a second duty ratio according to the image to be displayed;
A supply voltage generation circuit for generating a first supply voltage having a pulse width based on the first duty ratio and a second supply voltage having a pulse width based on the second duty ratio;
A plurality of first voltage supply lines provided corresponding to the plurality of scanning signal lines, respectively, for supplying the first supply voltage;
A plurality of second voltage supply lines provided corresponding to the plurality of scanning signal lines, respectively, for supplying the second supply voltage;
In the second display mode, the switching circuit has the three types of pixel forming units according to the value of the binarized data stored in the storage circuit provided in the corresponding pixel unit. Corresponding to each of the first supply voltage or the three types of pixel forming portions supplied by the first voltage supply line provided corresponding to the scanning signal line passing through the corresponding intersection. Any of the second supply voltages supplied from the second voltage supply line provided corresponding to the scanning signal line passing through the intersection may be used as a common pixel value for the three types of pixel forming units. It is made to take in.

According to a fourth invention, in the third invention,
The duty ratio setting circuit temporally changes the first duty ratio and the second duty ratio according to the image to be displayed.

  According to the first aspect of the invention, the storage circuit that takes in and stores the binarized data is provided for each pixel unit. In the predetermined display mode, the pixel values of the three types of pixel forming units included in each pixel unit are set in common according to the value of the binarized data stored in the storage circuit. For this reason, it is not necessary to supply a video signal to the pixel formation portion in the predetermined display mode. This eliminates the need for a high-frequency video signal and reduces the power consumed in the display device. In addition, the memory circuit that is conventionally provided for each sub-pixel is provided for each pixel unit. For this reason, the area occupied by the circuit in the pixel region is reduced as compared with the prior art. Thus, power consumption can be reduced while suppressing a decrease in aperture ratio due to provision of a circuit having a memory function in the pixel region.

  According to the second aspect of the invention, switching between the first display mode and the second display mode is performed. In the first display mode, the values of the video signals transmitted through the corresponding video signal lines are taken in as the pixel values of the three types of pixel forming portions. On the other hand, in the second display mode, a value set in accordance with the binarized data is captured as a common pixel value of the three types of pixel forming units. This makes it possible to switch between normal color display and monochrome display with low power consumption.

  According to the third aspect, the first voltage supply line for supplying the first supply voltage having the pulse width based on the first duty ratio and the second supply voltage having the pulse width based on the second duty ratio are provided. A second voltage supply line for supplying is provided. In the second display mode, the voltage supplied by either the first voltage supply line or the second voltage supply line is changed to three types of pixel formation according to the value of the binarized data. Are taken in as common pixel values. Here, by setting the first duty ratio and the second duty ratio to various values, the voltage value of the first supply voltage and the voltage value of the second supply voltage become various values. Therefore, it is possible to display a multi-tone image without increasing the number of voltage supply lines. As a result, multi-tone image display is realized without complicating the circuit configuration.

  According to the fourth aspect, the first duty ratio and the second duty ratio are temporally changed according to the image to be displayed. For this reason, the voltage value of the first supply voltage and the voltage value of the second supply voltage change with time, and multi-tone image display is possible with time.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

<1. Overall Configuration and Operation of Liquid Crystal Display Device>
FIG. 2 is a block diagram showing the overall configuration of the liquid crystal display device according to one embodiment of the present invention. This liquid crystal display device includes a liquid crystal display panel 100 and a display control circuit 200. The liquid crystal display panel 100 includes a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a display unit 500, and a memory driving driver 600 as a supply voltage generation circuit. . The display control circuit 200 includes a memory drive control unit 20 as a duty ratio setting circuit. The display unit 500 includes a source bus line (video signal line), a gate bus line (scanning signal line), a memory drive selection line, a first voltage supply line, a second voltage supply line, and a first power line. , And a second power line. The source bus line is connected to the source driver 300, the gate bus line and the memory drive selection line are connected to the gate driver 400, and the first voltage supply line and the second voltage supply line are connected to the memory drive driver 600. Has been. The display unit 500 also includes a plurality of pixel formation units provided corresponding to the intersections of the gate bus lines and the source bus lines. Each pixel forming portion includes a pixel electrode for applying a voltage according to an image to be displayed to a liquid crystal capacitor described later, a common electrode that is a common electrode provided in the plurality of pixel forming portions, and It consists of a liquid crystal layer that is commonly provided in a plurality of pixel formation portions and is sandwiched between the pixel electrode and the common electrode, and, if necessary, assists in parallel with the liquid crystal capacitance formed by the pixel electrode and the common electrode Capacity is added. In addition, 1-bit data for each pixel (hereinafter referred to as “pixel unit”) including three sub-pixels for R (Red: red), G (Green: green), and B (Blue: blue). A pixel memory circuit is provided as a storage circuit capable of holding the data. Note that the liquid crystal display device according to the present embodiment will be described as a normally white type.

  In the liquid crystal display device according to the present embodiment, the driving method can be switched between “normal driving” and “memory driving”. Here, “normal driving” is a driving method generally performed in a liquid crystal display device, and writing to a liquid crystal capacitor (application of voltage) based on a video signal applied to each source bus line. It is a method to do. On the other hand, “memory driving” is a method of performing writing to the liquid crystal capacitor based on data held in the pixel memory circuit. In the following, the display state during normal driving is referred to as “first display mode”, and the display state during memory driving is referred to as “second display mode”.

  The display control circuit 200 receives image data DAT and a display mode instruction signal M sent from the outside, receives a digital video signal DV, a source start pulse signal SSP and a source clock signal SCK for controlling image display on the display unit 500. The latch strobe signal LS, the gate start pulse signal GSP, the gate clock signal GCK, the first supply voltage control signal SAL, the second supply voltage control signal SBL, and the memory drive control signal SSEL are output.

  The source driver 300 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 200, and applies a driving video signal to each source bus line. .

  During normal driving, the gate driver 400 is activated based on the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 200 in order to sequentially select each gate bus line by one horizontal scanning period. The application of a scanning signal to each gate bus line is repeated with one vertical scanning period as a cycle. When switching from the normal drive to the memory drive, the gate driver 400 selects the gate bus pulse signal GSP and the gate clock signal output from the display control circuit 200 in order to sequentially select each gate bus line by one horizontal scanning period. Based on GCK, an active scanning signal is sequentially applied to each gate bus line, and the memory drive output from the display control circuit 200 is selected in order to sequentially select each memory drive selection line by one horizontal scanning period. An active signal is sequentially applied to each memory drive selection line based on the control signal SSEL and the gate clock signal GCK. When the memory is driven, the gate driver 400 stops the application of the active scanning signal to each gate bus line, and applies the active signal to all the memory driving selection lines SEL1 to SELm.

  Based on the first supply voltage control signal SAL and the second supply voltage control signal SBL output from the display control circuit 200, the memory driving driver 600 applies the first voltage supply line and the second voltage supply line. Apply a voltage signal.

<2. Configuration of pixel unit circuit>
FIG. 1 is an equivalent circuit diagram showing a configuration of a circuit (hereinafter referred to as “pixel unit circuit”) formed in a pixel region of a pixel unit including three sub-pixels for R, G, and B. . This pixel unit circuit includes common portions 50R, 50G, and 50B having a configuration common to the three sub-pixels, a pixel memory circuit 58 as a memory circuit, and a switch SWR4 realized by an N-type TFT. . As for the switch SWR4, the gate terminal is connected to the memory drive selection line SEL, the source terminal is connected to the common unit 50R, and the drain terminal is connected to the pixel memory circuit 58. The source terminals of the switches SWR3, SWG3, and SWB3 in the common units 50R, 50G, and 50B are connected to the pixel memory circuit 58.

  The configuration of the common portions 50R, 50G, and 50B will be described by taking the configuration of the common portion 50R of the R subpixel as an example. The common unit 50R includes switches SWR1 and SWR3 realized by N-type TFTs, a switch SWR2 realized by P-type TFTs, a liquid crystal capacitor 51R, and an auxiliary capacitor 53R. One ends of the liquid crystal capacitor 51R and the auxiliary capacitor 53R are connected to the pixel electrode 55R. The other end of the liquid crystal capacitor 51R is connected to the common electrode 52, and the other end of the auxiliary capacitor 53R is connected to the auxiliary capacitor electrode 54.

  Regarding the switch SWR1 in the common unit 50R, the gate terminal is connected to the gate bus line GL, the source terminal is connected to the source bus line SLR, and the drain terminal is connected to the source terminal of the switch SWR2 and the source terminal of the switch SWR4. ing. As for the switches SWR2 and SWR3, the gate terminal is connected to the memory drive selection line SEL, and the drain terminal is connected to the pixel electrode 55R. The source terminal of the switch SWR3 is connected to the pixel memory circuit 58. With this configuration, a switch circuit is realized by the switch SWR2 and the switch SWR3. That is, the switch SWR2 and the switch SWR3 are a voltage signal applied to the pixel electrode 55R, a voltage signal (video signal) applied from the source bus line SLR via the switch SWR1, and a voltage signal applied from the pixel memory circuit 58. Switch between.

<3. Configuration of Pixel Memory Circuit>
Next, a detailed configuration of the pixel memory circuit 58 will be described. FIG. 3 is an equivalent circuit diagram showing a detailed configuration of the pixel memory circuit 58. The pixel memory circuit 58 includes CMOS switches SWM1 and SWM2 composed of P-type TFTs and N-type TFTs, switches SWM4 and SWM6 realized by N-type TFTs, switches SWM3 and SWM5 realized by P-type TFTs, and SWM7.

  The source terminals of the switches SWM3 and SWM5 are connected to the first power supply line VLCH. On the other hand, the source terminals of the switches SWM4 and SWM6 are connected to the second power supply line VLCL. The gate terminal of the switch SWM7 is connected to the gate bus line GL. A circuit composed of the switches SWM3 and SWM4 and a circuit composed of the switches SWM5 and SWM6 function as an inverter circuit, and the switch SWM7 functions as a transfer gate. With the configuration as described above, the circuit including the switches SWM3, SWM4, SWM5, SWM6, and SWM7 functions as a data holding circuit 59 that holds 1-bit data.

  The switch SWM1 has an input terminal connected to the first voltage supply line AL, and an output terminal connected to the source terminals of the switches SWR3, SWG3, and SWB3 (FIG. 1) and the output terminal of the switch SWM2. The switch SWM2 has an input terminal connected to the second voltage supply line BL, and an output terminal connected to the source terminals of the switches SWR3, SWG3, and SWB3 (FIG. 1) and the output terminal of the switch SWM1.

  The gate terminal of the N-type TFT of the switch SWM1 is connected to the drain terminal of the switch SWR4 and the data holding circuit 59. The gate terminal of the P-type TFT of the switch SWM1 is connected to the gate terminal of the N-type TFT of the switch SWM2 and the data holding circuit 59. The gate terminal of the N-type TFT of the switch SWM2 is connected to the gate terminal of the P-type TFT of the switch SWM1 and the data holding circuit 59. The gate terminal of the P-type TFT of the switch SWM2 is connected to the data holding circuit 59.

<4. Driving method>
Next, the driving method in the present embodiment will be described with reference to FIGS. 1, 3, and 4. Note that the liquid crystal display device according to the present embodiment will be described as being provided with m gate bus lines. FIG. 4 shows the first, second, third, and m-th gate bus lines GL1, GL2, GL3, and GLm, and the first, second, third, and m-th memory drives. It is a signal waveform diagram of selection lines SEL1, SEL2, SEL3, SELm. In the present embodiment, as described above, switching between normal driving for the first display mode and memory driving for the second display mode is performed. This switching is performed based on a display mode instruction signal M sent to the display control circuit 200 from the outside. Hereinafter, a driving method during normal driving, a driving method when switching from normal driving to memory driving, and a driving method during memory driving will be described in order.

<4.1 Driving method during normal driving>
In FIG. 4, normal driving is performed from time t0 to time t1. During normal driving, as shown in FIGS. 4A to 4D, active signals are sequentially given to the respective gate bus lines GL1 to GLm for a predetermined period. On the other hand, during normal driving, no active signal is applied to the memory drive selection lines SEL1 to SELm.

  Here, paying attention to a certain pixel unit, when an active signal is applied to the gate bus line GL provided corresponding to the pixel unit, the switches SWR1, SWG1, and SWB1 are turned on. Since no active signal is applied to the memory drive selection line SEL during normal driving, the switches SWR2, SWG2, and SWB2 are turned on, and the switches SWR3, SWG3, SWB3, and SWR4 are turned off. Thus, writing to the liquid crystal capacitors 51R, 51G, and 51B is performed based on the video signals applied to the source bus lines SLR, SLG, and SLB, respectively. In this manner, video signals are written into the liquid crystal capacitors 51R, 51G, and 51B for all the pixel units within one frame period, and a desired image is displayed on the display unit 500.

<4.2 Driving method when switching from normal driving to memory driving>
In FIG. 4, during the period from time t1 to time t2, driving for switching from normal driving to memory driving is performed. During this period, as shown in FIGS. 4A to 4D, active signals are sequentially given to the gate bus lines GL1 to GLm for a predetermined period, and FIGS. 4E to 4H. As shown in FIG. 4, active signals are sequentially given to the respective memory drive selection lines SEL1 to SELm for a predetermined period.

  Here, paying attention to a certain pixel unit, an active signal is applied to the gate bus line GL provided corresponding to the pixel unit, and the memory drive selection provided corresponding to the pixel unit. When an active signal is applied to the line SEL, the switches SWR1, SWG1, and SWB1 are turned on, the switches SWR2, SWG2, and SWB2 are turned off, and the switches SWR3, SWG3, and SWB3 are turned on. Further, the switch SWR4 is turned on. Thereby, the video signal applied to the source bus line SLR is given to the pixel memory circuit 58, and the video signal is stored in the data holding circuit 59 in the pixel memory circuit 58 as in-memory data MD.

  In this way, the in-memory data MD is stored in the pixel memory circuit 58 for all the pixel units during the period from the time point t1 to the time point t2. In the following, when the video signal is binarized (when the logic level is divided into high level data and low level data), if the logic level is high, the in-memory data In the following description, it is assumed that “1” is stored in the pixel memory circuit 58 as MD and “0” is stored in the pixel memory circuit 58 as in-memory data MD if the logical level is low.

<4.3 Driving method for memory driving>
In FIG. 4, memory driving is performed from time t2 to time t3. When the memory is driven, as shown in FIGS. 4A to 4D, no active signal is applied to the gate bus lines GL1 to GLm. Therefore, during this period, the switch SWR1 is always off. Thus, since the switch SWR1 is turned off, the value of the in-memory data MD is not affected by the video signal supplied by the source bus line SLR during the period in which the memory is driven.

  On the other hand, during this period, as shown in FIGS. 4E to 4H, active signals are given to all the memory drive selection lines SEL1 to SELm. For this reason, the switches SWR2, SWG2, and SWB2 are always in the off state and the switches SWR3, SWG3, and SWB3 are always in the on state during the memory driving period. Thus, writing to the liquid crystal capacitors 51R, 51G, and 51B is performed based on the voltage signal output from the output terminal of the switch SWM1 or the output terminal of the switch SWM2 in the pixel memory circuit 58. Thus, when the memory is driven, writing is performed on the liquid crystal capacitors 51R, 51G, and 51B based on the common voltage signal. For this reason, monochrome display is performed when the memory is driven. Hereinafter, the memory driving will be described in detail with an example.

  FIG. 5 is a signal waveform diagram in the case where black display is performed for the pixel unit whose value of the in-memory data MD is “1”. By the way, in order to prevent the deterioration of the liquid crystal due to the application of the DC voltage, the common electrode 52 is inverted and driven during both normal driving and memory driving. That is, the potential Vcont of the common electrode 52 is switched between a high potential and a low potential at a predetermined interval.

  Focusing on the on / off states of the switches SWM3 to SWM7 in the data holding circuit 59, when the in-memory data MD is “1”, the switch SWM3 is turned off and the switch SWM4 is turned on. For this reason, a low-potential power supply voltage is applied from the second power supply line VLCL to the data holding circuit 59 via the switch SWM4. As a result, the switch SWM5 is turned on and the switch SWM6 is turned off. As a result, a high power supply voltage is applied from the first power supply line VLCH to the data holding circuit 59 via the switch SWM5. Further, as described above, an active signal is not given to the gate bus line GL when the memory is driven, so that the switch SWM7 is in an ON state regardless of the value of the in-memory data MD. For this reason, the value of the in-memory data MD is held during the period in which the memory is driven.

  As described above, since a low-potential power supply voltage is applied to the data holding circuit 59 via the switch SWM4, the P-type TFT of the switch SWM1 is turned on and the N-type TFT of the switch SWM2 is turned off. On the other hand, since a high-potential power supply voltage is applied to the data holding circuit 59 via the switch SWM5 and the switch SWM7 is on, the N-type TFT of the switch SWM1 is on and the P of the switch SWM2 is on. The type TFT is turned off. As a result, the switch SWM1 is turned on and the switch SWM2 is turned off. As a result, a voltage (hereinafter referred to as “first supply voltage”) VAL applied from the first voltage supply line AL is applied to the pixel electrodes 55R, 55G, and 55B of each sub-pixel.

  In the present embodiment, as shown in FIGS. 5B and 5C, when the potential Vcont of the common electrode 52 is set to the high potential side (period T11), the potential of the first supply voltage VAL is set. Is set on the low potential side, and when the potential Vcont of the common electrode 52 is set on the low potential side (period T12), the potential of the first supply voltage VAL is set on the high potential side. Therefore, a high voltage is always applied to the liquid crystal capacitors 51R, 51G, and 51B, and black display is performed for the pixel units including the liquid crystal capacitors 51R, 51G, and 51B.

  FIG. 6 is a signal waveform diagram in the case where white display is performed for a pixel whose value of the in-memory data MD is “0”. Focusing on the on / off states of the switches SWM3 to SWM7 in the data holding circuit 59, when the in-memory data MD is “0”, the switch SWM3 is turned on and the switch SWM4 is turned off. Therefore, a high-potential power supply voltage is applied from the first power supply line VLCH to the data holding circuit 59 via the switch SWM3. As a result, the switch SWM5 is turned off and the switch SWM6 is turned on. As a result, a low-potential power supply voltage is applied from the second power supply line VLCL to the data holding circuit 59 via the switch SWM6. Note that the switch SWM7 is in an ON state as in the case where the value of the in-memory data MD is “1”. For this reason, the value of the in-memory data MD is held during the period in which the memory is driven.

  As described above, since a high-potential power supply voltage is applied to the data holding circuit 59 via the switch SWM3, the P-type TFT of the switch SWM1 is turned off and the N-type TFT of the switch SWM2 is turned on. On the other hand, since a low-potential power supply voltage is applied to the data holding circuit 59 via the switch SWM6 and the switch SWM7 is turned on, the N-type TFT of the switch SWM1 is turned off, and the switch SWM2 P The type TFT is turned on. As a result, the switch SWM1 is turned off and the switch SWM2 is turned on. As a result, a voltage signal (hereinafter referred to as “second supply voltage”) supplied from the second voltage supply line BL is applied to the pixel electrodes 55R, 55G, and 55B of each sub-pixel.

  In this embodiment, as shown in FIGS. 6B and 6D, when the potential Vcont of the common electrode 52 is set to the high potential side (period T21), the potential of the second supply voltage VBL is set. Is set on the high potential side, and when the potential Vcont of the common electrode 52 is set on the low potential side (period T22), the potential of the second supply voltage VBL is set on the low potential side. Therefore, a low voltage is always applied to the liquid crystal capacitors 51R, 51G, and 51B, and white display is performed for the pixel units including the liquid crystal capacitors 51R, 51G, and 51B.

  FIG. 7 is a signal waveform diagram for explaining the halftone display in the present embodiment. As described above, when the potential of the first supply voltage VAL and the potential of the second supply voltage VBL are switched in synchronization with the timing at which the potential Vcont of the common electrode 52 is inverted, white display or black display is performed. In the present embodiment, intermediate gradation display is performed by changing the duty ratio (first duty ratio) for the first supply voltage VAL and the duty ratio (second duty ratio) for the second supply voltage VBL. Is done. Note that the duty ratio in this description refers to a ratio of a period during which a high potential is applied to a predetermined period when two potentials, a high potential and a low potential, are applied.

  For example, when the high potential side potential of the first supply voltage VAL is 5 V and the low potential side potential is 1 V, the duty ratio for the first supply voltage VAL is set to 75%. The potential of the supply voltage VAL of 1 changes as shown in FIG. 7, and the average potential Vave becomes 4V.

  In the present embodiment, the duty ratio for the first supply voltage VAL is set by the memory drive control unit 20 in the display control circuit 200. Similarly, the duty ratio for the second supply voltage VBL is also set by the memory drive control unit 20 in the display control circuit 200. Based on these duty ratios, the memory drive controller 20 provides the memory driver 600 with the first supply voltage control signal SAL and the second supply voltage control signal SBL. Then, based on the first supply voltage control signal SAL and the second supply voltage control signal SBL, the memory driver 600 supplies the first supply voltage VAL and the second supply voltage VBL to the display unit 500. The

  FIG. 8 is a signal waveform diagram showing an example when intermediate gradation display is performed. In this example, the potential Vcont of the common electrode 52 is switched between 0V and 6V every predetermined period. The potential of the first supply voltage VAL and the potential of the second supply voltage VBL are switched between 1V and 5V. Further, the duty ratio for the first supply voltage VAL in the period (period T31) in which the potential Vcont of the common electrode 52 is set to 6 V is 75%, and the duty ratio for the second supply voltage VBL in the period is 25%. Set to percent. Note that the duty ratio for the first supply voltage VAL during the period (period T31) in which the potential Vcont of the common electrode 52 is set to 6 V and the period in which the potential Vcont of the common electrode 52 is set to 0 V (period T32). The sum of the first supply voltage VAL and the duty ratio is set to 100%. The same applies to the second supply voltage VBL.

  As described above, the first supply voltage VAL is applied to the pixel electrodes 55R, 55G, and 55B of each sub-pixel for the pixel unit whose in-memory data MD is “1”. In the period T31, the average potential of the first supply voltage VAL is 4V, and the potential Vcont of the common electrode 52 is set to 6V. Accordingly, in the period T31, a voltage of 2V is applied to the liquid crystal capacitors 51R, 51G, and 51B included in the pixel unit. In the period T32, the average potential of the first supply voltage VAL is 2V, and the potential Vcont of the common electrode 52 is set to 0V. Accordingly, a voltage of 2 V is applied to the liquid crystal capacitors 51R, 51G, and 51B included in the pixel unit also during the period T32.

  On the other hand, for the pixel unit whose value of the in-memory data MD is “0”, the second supply voltage VBL is applied to the pixel electrodes 55R, 55G, and 55B of each sub-pixel. In the period T31, the average potential of the second supply voltage VBL is 2V, and the potential Vcont of the common electrode 52 is set to 6V. Therefore, in the period T31, a voltage of 4V is applied to the liquid crystal capacitors 51R, 51G, and 51B included in the pixel unit. In the period T32, the average potential of the second supply voltage VBL is 4V, and the potential Vcont of the common electrode 52 is set to 0V. Therefore, a voltage of 4 V is applied to the liquid crystal capacitors 51R, 51G, and 51B included in the pixel unit also during the period T32.

  FIG. 9 is a signal waveform diagram showing another example when halftone display is performed. In this example, the potential Vcont of the common electrode 52 is switched between 0V and 6V every predetermined period. The potential of the first supply voltage VAL and the potential of the second supply voltage VBL are switched between 1V and 5V. Further, the duty ratio for the first supply voltage VAL in the period (period T41) in which the potential Vcont of the common electrode 52 is set to 0 V is 50%, and the duty ratio for the second supply voltage VBL in the period is 0%. Set to percent.

  As described above, the first supply voltage VAL is applied to the pixel electrodes 55R, 55G, and 55B of each sub-pixel for the pixel unit whose in-memory data MD is “1”. In the period T41, the average potential of the first supply voltage VAL is 3V, and the potential Vcont of the common electrode 52 is set to 6V. Accordingly, in the period T41, a voltage of 3V is applied to the liquid crystal capacitors 51R, 51G, and 51B included in the pixel unit. In the period T42, the average potential of the first supply voltage VAL is 3V, and the potential Vcont of the common electrode 52 is set to 0V. Therefore, a voltage of 3 V is applied to the liquid crystal capacitors 51R, 51G, and 51B included in the pixel unit also during the period T42.

  On the other hand, for the pixel unit whose value of the in-memory data MD is “0”, the second supply voltage VBL is applied to the pixel electrodes 55R, 55G, and 55B of each sub-pixel. In the period T41, the average potential of the second supply voltage VBL is 1V, and the potential Vcont of the common electrode 52 is set to 6V. Therefore, in the period T41, a voltage of 5 V is applied to the liquid crystal capacitors 51R, 51G, and 51B included in the pixel unit. In the period T42, the average potential of the second supply voltage VBL is 5V, and the potential Vcont of the common electrode 52 is set to 0V. Therefore, a voltage of 5 V is applied to the liquid crystal capacitors 51R, 51G, and 51B included in the pixel unit also during the period T42.

  As described above, the duty ratio for the first supply voltage VAL and the second supply voltage VBL is set to various values. Meanwhile, the memory drive control unit 20 can also change the duty ratio during a period in which the memory drive is performed. For this reason, multi-gradation display can be performed temporally for each pixel unit.

<5. Effect>
Conventionally, the pixel memory circuit 58 is provided for each of the sub-pixels 5R, 5G, and 5B as shown in FIG. On the other hand, according to the present embodiment, the pixel memory circuit 58 is provided for each pixel unit including three sub-pixels for R, G, and B. For this reason, as shown in FIG. 10, the area occupied by the circuit in the pixel region is reduced as compared with the prior art. In such a configuration including the pixel memory circuit 58, data for image display during memory driving is stored in the pixel memory circuit 58 before switching from normal driving to memory driving. The pixel memory circuit 58 is supplied with the first supply voltage VAL and the second supply voltage VBL. When the memory is driven, the first supply voltage VAL or the second supply voltage is selected according to the value of the in-memory data MD. One of the voltages VBL is applied to the pixel electrodes 55R, 55G, and 55B of each subpixel. For this reason, it is not necessary to supply the video signal SL to the pixel formation portion when driving the memory. Thus, for example, by displaying an image with little change such as a standby screen of a mobile phone, a time display, and a battery remaining amount display by driving a memory, it is not necessary to supply a video signal SL having a high frequency, and power consumption is reduced. Further, since the area occupied by the circuit in the pixel region is reduced as compared with the conventional case as described above, it is possible to reduce the power consumption while suppressing the decrease in the aperture ratio due to the provision of the circuit having the memory function in the pixel region. Can be realized.

  Further, according to the present embodiment, the voltage value of the first supply voltage VAL and the voltage value of the second supply voltage VBL can be set to various values by setting the duty ratio to various values. For this reason, the number of gradations of the display image can be increased without increasing the number of voltage supply lines. Therefore, the circuit configuration is not complicated in order to realize multi-gradation display. Further, the duty ratio can be changed during the memory driving period. For this reason, it is possible to perform multi-tone image display in terms of time.

<6. Other>
In the above embodiment, the description has been made on the assumption that a normally white liquid crystal display device is used. However, the present invention is not limited to this, and can be applied to a normally black liquid crystal display device. In addition, although a liquid crystal display device is described as an example of the display device, the present invention is not limited to this, and the present invention can be applied to other display devices.

  Furthermore, in the above embodiment, the video signal applied to the R source bus line SLR is supplied to the pixel memory circuit 58 and held as in-memory data MD. It is not limited to. The video signal supplied to the pixel memory circuit 58 may be a video signal applied to the G source bus line SLG or a video signal applied to the B source bus line SLB. good.

  Furthermore, in the above embodiment, the first voltage supply line AL and the second voltage supply line BL in the display unit 500 are connected to the memory driving driver 600, but the present invention is not limited to this. For example, it may be connected to the source driver 300, or may be connected to the display control circuit 200 if the present invention is applied only to a part of the area in the display unit 500.

FIG. 3 is an equivalent circuit diagram illustrating a configuration of a pixel unit circuit for one subpixel in the liquid crystal display device according to the embodiment of the present invention. In the said embodiment, it is a block diagram which shows the whole structure of a liquid crystal display device. FIG. 3 is an equivalent circuit diagram illustrating a detailed configuration of a pixel memory circuit in the embodiment. It is a signal waveform diagram for demonstrating the drive method in the said embodiment. In the said embodiment, it is a signal waveform diagram when black display is performed at the time of memory drive. In the said embodiment, it is a signal waveform diagram when white display is performed at the time of memory drive. In the said embodiment, it is a signal waveform diagram for demonstrating halftone display. In the said embodiment, it is a signal waveform diagram which shows an example when intermediate gradation display is performed. In the said embodiment, it is a signal waveform diagram which shows another example when intermediate gradation display is performed. It is a figure for demonstrating the effect in the said embodiment. It is a figure for demonstrating the pixel memory circuit in a prior art example.

Explanation of symbols

5R, 5G, 5B: Sub-pixel 20: Memory drive control unit 51R, 51G, 51B ... Liquid crystal capacitance 52 ... Common electrode 55R, 55G, 55B ... Pixel electrode 58 ... Pixel memory circuit 59 ... Data holding circuit 100 ... Liquid crystal display panel 200 ... display control circuit 300 ... source driver 400 ... gate driver 500 ... display unit 600 ... memory driving driver AL ... first voltage supply line BL ... second voltage supply line GL ... gate bus line MD ... data in memory SAL ... First supply voltage control signal SBL ... Second supply voltage control signal SEL ... Memory drive selection line SLR, SLG, SLB ... Source bus line SWR1-SWR4, SWG1-SWG3, SWB1-SWB3 ... Switch SWM1-SWM7 ... Switch VLCH ... 1st power line VLCL ... 1st Power line

Claims (4)

A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A display device including a plurality of pixel formation units each including three types of pixel formation units arranged in a matrix corresponding to intersections with signal lines and displaying predetermined three primary colors;
Provided for each pixel unit that includes the three types of pixel forming portions as a set, and binarized data based on a video signal transmitted by a video signal line corresponding to one of the three types of pixel forming portions is captured. A memory circuit for storing,
In the predetermined display mode, the pixel values of the three types of pixel forming units included in each pixel unit are in accordance with the value of the binarized data stored in the storage circuit provided in each pixel unit. A display device characterized by being set to a common value. Having a first display mode and a second display mode;
For each pixel unit, it is provided with a switching circuit for causing the three types of pixel forming portions to take in pixel values according to the display mode,
The switching circuit is
In the first display mode, the three types of pixel formation units are caused to capture the values of the video signals transmitted by the video signal lines corresponding to the three types of pixel formation units as pixel values,
In the case of the second display mode, the three types of the pixel values that are set according to the value of the binarized data stored in the storage circuit provided in the corresponding pixel unit are used as the common pixel values. The display device according to claim 1, wherein the display device is incorporated into a pixel formation portion. A duty ratio setting circuit for setting a first duty ratio and a second duty ratio according to the image to be displayed;
A supply voltage generation circuit for generating a first supply voltage having a pulse width based on the first duty ratio and a second supply voltage having a pulse width based on the second duty ratio;
A plurality of first voltage supply lines provided corresponding to the plurality of scanning signal lines, respectively, for supplying the first supply voltage;
A plurality of second voltage supply lines provided corresponding to the plurality of scanning signal lines, respectively, for supplying the second supply voltage;
In the second display mode, the switching circuit has the three types of pixel forming units according to the value of the binarized data stored in the storage circuit provided in the corresponding pixel unit. Corresponding to each of the first supply voltage or the three types of pixel forming portions supplied by the first voltage supply line provided corresponding to the scanning signal line passing through the corresponding intersection. Any of the second supply voltages supplied from the second voltage supply line provided corresponding to the scanning signal line passing through the intersection may be used as a common pixel value for the three types of pixel forming units. The display device according to claim 2, wherein the display device is incorporated into the display device. The display device according to claim 3, wherein the duty ratio setting circuit temporally changes the first duty ratio and the second duty ratio according to the image to be displayed.

Images