JP4975322B2 - Active matrix liquid crystal display device and control method thereof - Google Patents

Active matrix liquid crystal display device and control method thereof Download PDF

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JP4975322B2
JP4975322B2 JP2005380396A JP2005380396A JP4975322B2 JP 4975322 B2 JP4975322 B2 JP 4975322B2 JP 2005380396 A JP2005380396 A JP 2005380396A JP 2005380396 A JP2005380396 A JP 2005380396A JP 4975322 B2 JP4975322 B2 JP 4975322B2
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gate
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liquid crystal
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JP2007178952A (en
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居 勝 安
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ティーピーオー、ホンコン、ホールディング、リミテッドTpo Hong Kong Holding Limited
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  The present invention relates to an active matrix liquid crystal display device.

  In an active matrix liquid crystal display device, an image is displayed in units of frames. In this case, a voltage is applied to each pixel in a frame unit by a thin film transistor (hereinafter referred to as TFT) circuit, which is a switching element between the pixel electrode and the counter electrode, according to the brightness and hue of the display image.

  The charge written to the pixel according to the video signal is held until the next frame data is written by the TFT. During the charge retention period of the pixel, the TFT gate voltage is maintained at a sufficiently low potential, and the TFT is turned off.

  However, when the screen becomes high definition and large, a TFT with a large writing capability is required to write in a short time, and at that time, a large leakage current is generated in conjunction with this, and the pixel charge holding capability is reduced. I will lose. In such a case, it is necessary to optimize the non-conduction potential with the least TFT leakage and apply it to the gate to keep the pixel charge sufficiently stable.

  On the other hand, in order to improve display quality, an active matrix liquid crystal display device that performs AC drive control that reverses the voltage applied to the liquid crystal for each frame performs image display in units of frames. In this case, a voltage is applied to each pixel in a frame unit between the pixel electrode and the counter electrode by a thin film transistor circuit according to the brightness and color tone of the display image. AC drive control for inverting the applied voltage is performed.

  This is because an insulating film used in a liquid crystal display device contains ionic impurities and moves when a voltage is applied to drive the liquid crystal. In order to cope with the problem of degrading the image quality, the control method is such that the charge is not moved by alternating the driving polarity of the liquid crystal.

  Various types of AC drive control have been proposed in the past, such as inter-frame AC that inverts the polarity of the entire frame for each frame, inter-row AC or inter-column AC that inverts for each row or column, and a staggered unit. Inter-matrix alternating (dot inversion) etc.

  These inversions can be realized by applying a DC potential to the common electrode and applying a drive voltage alternating between positive polarity and negative polarity as a source signal. However, since the signal dynamic range is wide, the withstand voltage of the drive circuit is required. In addition, power consumption is large.

  For this reason, conventionally, the potential of the common electrode is changed to add an alternating amplitude component to the pixel potential, or an auxiliary capacitance line is provided, and the auxiliary capacitance line is changed to add the alternating component to the pixel potential. Alternatively, power consumption can be reduced by installing an auxiliary capacitor on an adjacent gate line, changing the potential of the adjacent gate line, and supplying an alternating component added to the pixel potential.

An example in which an auxiliary capacitance line is provided is disclosed in Japanese Patent Application Laid-Open No. 2003-15080 (Patent Document 1). In particular, the active matrix display device shown in FIG. .
JP 2003-15080 A

  By the way, regarding the leak characteristics of a thin film transistor (TFT) responsible for charging a pixel and maintaining its charge, there is a gate bias that gives a minimum leak. FIG. 1 shows a schematic relationship between such a gate bias and leakage current, where the horizontal axis indicates the gate voltage and the vertical axis indicates the leakage current. Referring to FIG. 1, it can be seen that there is a gate bias that gives the minimum leakage. As described above, regarding the leakage current, a leakage curve having a bottom peak is generally used.

  In this case, if only one bias is applied to one TFT as in the conventional case, minimizing high potential leakage will increase low potential leakage, conversely minimizing low potential leakage. Then, there is a problem that leakage at a high potential increases.

  On the other hand, as shown in FIG. 2, if driving is performed so as to always realize the minimum leak bias, sufficient amplitude cannot be obtained between the positive polarity and the negative polarity. In order to solve this problem, in order to ensure a sufficient amplitude in both cases of positive polarity and negative polarity, as shown in FIG. 3, depending on the case of holding a high level charge and the case of holding a low level charge. It is desirable to provide different optimum charge holding gate bias potentials.

  However, if this is to be achieved, the gate drive signal requires a large amplitude and is driven at a high voltage, so that the leakage current increases and power consumption increases, and the influence of the leakage current on the image quality is avoided. I can't.

  The present invention has been made to solve such a problem. In particular, the present invention relates to an active matrix liquid crystal display device and an active matrix liquid crystal display device with low leakage current, low power consumption, and good image quality. An object is to provide a control method.

According to the active matrix liquid crystal display device of the present invention,
A pixel array including a plurality of pixel portions each having a liquid crystal element arranged in a matrix and having a pixel capacity;
First and second gate lines provided in a plurality of row units of the pixel array and controlled independently;
Provided in a plurality of column units of the pixel array, and a source line to which signals of positive and negative polarities are supplied according to positive and negative writing,
The pixel portion is a plurality of transistors that selectively connect a pixel electrode and the source line, and each gate is connected to the first and second gate lines, and are connected in series. A first transistor group having a gate connected to the first gate line; and a second transistor group having a gate connected to the second gate line;
Different transistor non-conducting selection potentials are supplied to the first gate line and the second gate line,
The first gate line is supplied with a potential in the vicinity of a potential that causes a minimum leakage of pixel charges when the pixel electrode potential is held positive, and the pixel electrode potential is negative in the second gate line. In the vicinity of the potential that causes the minimum leakage of pixel charge when
Each gate is connected to the pixel capacitor and the first and second gate lines, and a gate connected to the gate of the transistor closest to the liquid crystal element among the first and second transistors connected in series. A kickback capacitive element connected between the line and the liquid crystal element and having an auxiliary capacitor having a predetermined proportional relationship with the pixel capacitance, and using kickback due to charges accumulated in the kickback capacitive element. Thus, reverse polarity writing is performed.

  According to the active matrix type liquid crystal display device and the control method thereof according to the present invention, the liquid crystal driving circuit includes the first and second gate lines, and the liquid crystal driving circuit includes the first and second gates connected in series. 1st and 2nd transistor, the 1st signal drives the positive polarity with the minimum leakage current with the 1st signal which is supplied with the 1st gate line, the 2nd which is supplied with the 2nd gate line With this signal, control is performed so that the second transistor performs negative polarity driving with the minimum leakage current, so that the leakage current can always be minimized.

  Further, according to the active matrix liquid crystal display device of the present invention, a plurality of transistors connected to a plurality of gate lines and connected in series, and a transistor closest to the liquid crystal element among the plurality of transistors. Since it has a gate line connected to the gate and a capacitive element for kickback connected between the liquid crystal, reverse polarity writing is performed using kickback due to the charge accumulated in the kickback capacitive element. ing. Therefore, the fluctuation range of the voltage can be reduced, and the leakage current can be reduced by appropriately selecting the gate bias.

  If this leakage current is small, it takes a long time to hold a certain image state, conversely, the change in luminance is reduced and flicker is reduced, so that the image quality can be improved. In particular, since inter-matrix exchange can be easily performed, flicker can be further suppressed.

  Further, the holding capacity Cs for holding the state can be reduced, and the writing time can be shortened.

  In particular, in future multi-row high-definition panels, it is expected that it will be difficult to control leaks, so a panel with less leaks is desired, but the present invention meets this requirement.

  Hereinafter, some embodiments of the active matrix type liquid crystal display device according to the present invention will be described in detail.

  FIG. 4 is a circuit diagram showing a schematic configuration of the active matrix liquid crystal display device according to the first embodiment of the present invention.

  In this circuit, two liquid crystal element gate lines, Ga and Gb, are arranged in parallel in the row direction, a source line S is arranged orthogonally to this, and a liquid crystal element LC is provided at the intersection of these lines. It has been. Two n-channel transistors Ta and Tb are connected in series between one end (drain) of the liquid crystal element LC and the source line S. The gate of the transistor Ta is connected to the gate line Ga and the gate of the transistor Tb is connected to the gate line Gb. Are connected to each. Accordingly, the transistor Tb on the pixel side is combined with the transistor Ta on the source line side in series, and thus functions as an AND gate when controlling source data writing to the pixel. The other end of the liquid crystal element LC is connected to the common electrode CM. The liquid crystal element LC has a pixel capacitance Cpx.

  FIG. 5 is a waveform diagram showing waveforms of gate signals applied to the gate lines Ga and Gb. As shown in the figure, the positive polarity drive and the negative polarity drive are performed with the same amplitude from the reference level, but the voltage waveform supplied to the gate line Ga for performing the positive polarity drive has a low potential value at the reference level. The voltage waveform supplied to the gate line Gb for performing negative polarity driving is lower than the minimum value of negative polarity driving. The value is low by an amount corresponding to the leak gate bias.

  In this way, the low potential of each gate signal is set in the vicinity of the potential that can minimize the leakage of the TFT in both cases of positive polarity driving and negative polarity movement of the charge held in the pixel. .

  In order to realize this, it is necessary to set two types of optimum values of the low potential of the gate. Therefore, as shown in FIG. 4, two TFTs are connected in series, and each TFT has a low-order pixel. A drive waveform that biases to the gate bias potential that can best hold the potential and the higher pixel potential, that is, the bottom potential of a different gate, is supplied.

  As a result, it is possible to hold charges with minimum leakage in both cases of high potential and low potential.

  FIG. 6 is a circuit diagram showing a configuration of one pixel of an active matrix liquid crystal display device according to another embodiment of the present invention.

  As is apparent from FIG. 6, two liquid crystal element gate lines, Ga and Gb, are arranged in parallel to the row direction, and a source line S is arranged orthogonally to the liquid crystal element gate lines. An element LC is provided. Two n-channel transistors Ta and Tb are connected in series between one end (drain) of the liquid crystal element LC and the source line S. The gate of the transistor Ta is connected to the gate line Ga and the gate of the transistor Tb is connected to the gate line Gb. Are connected to each. Accordingly, the transistor Tb on the pixel side is combined with the transistor Ta on the source line side in series, and thus functions as an AND gate when controlling source data writing to the pixel. The other end of the liquid crystal element LC is connected to the common electrode CM.

  The liquid crystal element LC has a pixel capacitance Cpx, which is the sum of the pure liquid crystal capacitance Clc and the other capacitance Cs. A capacitor Cgd that is an auxiliary capacitor and exhibits a kickback effect is connected between the drain terminal and the gate line Gb.

  The transistors Ta and Tb used here are a-Si type TFTs or LTPS type TFTs. The relationship between the gate-source voltage of these transistors and the drain current is shown in FIG. 1 as described above. Thus, since these transistors generally have a specific gate-source potential that supplies a minimum leakage current, different non-conducting bias voltages are applied to the respective gates of the transistors Ta and Tb. For example, when positive polarity data is written in the pixel, Ta is given a non-conducting bias potential that minimizes the leakage with respect to those potentials. For example, Tb has a negative polarity in the pixel. When data is written, a non-conducting bias potential is applied so as to minimize leakage with respect to those potentials.

  In the above configuration, the transistor Ta performs an operation of selectively writing data on the source / bus bus to the pixel by performing normal scan driving. As described above, the low level applied to the gate of the transistor Ta is an optimum potential that can most effectively hold the average level of the positive polarity data of the pixel.

  On the other hand, the transistor Tb performs a kickback function of shifting the pixel electrode potential downward through the capacitor Cgd to superimpose an alternating amplitude component. Furthermore, the low level applied to the gate of the transistor Tb is an optimum potential that can most effectively hold the average level of the negative polarity data of the pixel.

  Next, the operation of this circuit will be described with reference to FIG. FIG. 7 is a graph showing changes in main potentials in this configuration. In order to facilitate understanding, a plurality of lines are overlapped with the time axis and level aligned.

  A signal of positive and negative polarity is given to the source line as a reverse polarity direction signal within the same dynamic range.

The levels of the gate lines Ga and Gb are almost the same, but the minimum values are both lower than the center level of the inversion of the liquid crystal, and the relationship between the minimum level Vgab of the gate line Ga and the minimum level Vgbb of the gate line Gb. Is
Vgab> Vgbb
It is.

  At the time of positive writing, first, the source line data Vp is in the range from the lowest value Vpb to the highest value Vpt, and the gate line voltage Vgb and the other gate line voltage Vga are raised so that the highest levels Vgat and Vgbt exist simultaneously. To do. As a result, the two transistors are turned on and become conductive, and the source line data is written into the liquid crystal element. The transistor Tb is kept at a high level until the next negative polarity data is written even after this writing is completed.

  By the above operation, the positive data voltage on the source line is written in the drain level. FIG. 2 shows a case where the data to be written is the most positive and has a high level Vpt. Since the potential of the gate line Ga drops after a predetermined time so that the Vgat becomes a pulse shape, the drain voltage slightly decreases at this fall, but the level is maintained as the pixel drain positive polarity level Vdt.

  Next, at the time of negative polarity writing, source line data is supplied in the range from the negative maximum value Vnt to the minimum value Vnb, and the level Vga of the gate line Ga is raised in a pulse form from Vgab to the maximum value Vgat. Data is written, then lowered after the writing is completed, and then the level of the gate line Gb is lowered from Vgbt to Vgbb with a delay. Although negative polarity data is written at the drain level, the pixel potential is greatly shifted in the negative direction due to the kickback effect by the gate signal Gb through the capacitor Cgd at the same time or slightly after the end of the writing of the negative polarity data, It is automatically set to the negative drive level Vdb. FIG. 7 shows the case where the data to be written is the lowest negative voltage level Vnb.

  As described above, by appropriately performing the level control of the two gate lines Ga and Gb and the timing of supplying the source data, the drain voltage can be driven in an inverted manner without increasing the voltage applied to the source line. .

  Here, the value of the kickback capacity should be considered. For simplification, it is assumed that the pixel capacitance Cpx is only the liquid crystal capacitance Clc. The level change under this assumption is shown in FIG. 8, and compared with FIG. 7, the fine change in the drain voltage of the small kickback effect due to the gate signal Ga is ignored, but the stabilized voltage is almost the same. ing.

First, since the voltage of the gate Gb needs to maintain the transistor Tb in a leak-free state,
Vgbb ≦ Vdb−Vth (1)
Need to be. Here, Vth is a margin from the drain potential to the optimum off state of the transistor.

Next, since the voltage fluctuation at the gate of the transistor Vb must optimize the drain level shift, the following relationship is established.
(Vgbt-Vgbb) cgd / (Cgd + Cpx) = Vnb-Vdb (2)

In addition, the drain level fluctuation needs to satisfy optical requirements in terms of the design of the liquid crystal cell. This shake is
Vdt-Vdb = Vdpp (3)
Is defined.

In addition, since the transistor Tb needs to have a sufficiently high voltage to write data to the pixel,
Vgbt> Vpt + Vth '(4)
It is necessary to satisfy the relationship. Here, Vth ′ is a margin for the ON state of the transistor.

Here, the following specific numerical values are assumed.
Vdc = 0 (V)
Vpt = Vnt = 4 (V)
Vpb = Vnb = 0 (V)
Vth = 3 (V), Vth '= 3 (V)
given that,
Vgat = Vgbt = 7 (V)
Vgab =-3 (V)
Vdpp = 8 (V)
Vgbb =-7 (V)
Therefore, when applied to equation (2),
14Cgd / (Cgd + Cpx) = +4 (V)
Cgd / (Cgd + Cpx) = 4/14 = 4 / (4 + 10)
And
Cgd: Cpx = 4: 10 = 2: 5
The relationship is obtained. Therefore, it is understood that the capacity for kickback should be 2/5 of the liquid crystal capacity, and the auxiliary capacity Cgd should be designed to such a value.

  In the above example, the description has been made on the assumption that only the pixel capacitance Cpx is considered and no other second auxiliary capacitance is provided. However, the second auxiliary capacitance Cs may be further provided.

  As a driving method using an auxiliary capacitor, a CC (Capacitor-Coupling) driving method is known.

  In this case, there are two types of forms for connecting and connecting the auxiliary capacitance, one of which is a method of forming a dedicated Cs line parallel to the gate line and creating Cs on that line, and the other is This is a method of creating Cs on the gate line itself.

  Furthermore, there are two types of methods to create on the gate line. There are known methods of making it on the gate line of the next row and making it on the gate line of the previous row, and using such Cs Therefore, even if the source amplitude does not have sufficient amplitudes of the positive electrode and the negative electrode, alternating current can be achieved.

  Furthermore, this auxiliary capacitor can be formed on the gate line of the pixel itself.

  This eliminates the need for a dedicated area for the auxiliary capacity, and improves the aperture ratio.

  When an auxiliary capacitor is provided, the low level of the gate voltage of the transistor Ta for normal scanning can be made relatively high, and the scan amplitude of the gate is small, so that the design of the scan transistor becomes easy and low power consumption. Can be realized.

  In addition, the gate line of the transistor Ta in the next row can be used as the counter electrode of the auxiliary capacitor Cs, whereby the aperture ratio of the pixel can be increased.

  In this case, the auxiliary capacitor for charge retention functions as a combined capacitor of two auxiliary capacitors Cgd and Cs. However, since only Cgd is involved as the capacitor for kickback, the mutual values are shared. A relatively free auxiliary capacitance value Cgd can be designed.

  In addition, the gate line of the transistor Ta in the next row can be used as the counter electrode of the second auxiliary capacitor Cs, whereby the aperture ratio of the pixel can be increased.

  As described above, in the liquid crystal display device according to this embodiment, the negative electrode drive level of the pixel is held at a low leak by the low level of the gate of the transistor Tb. That is, the positive drive level is held at the low level of the gate of the transistor Ta. This means that the bias potential that gives the minimum leakage can be distributed according to the polarity potential of the drain in order to avoid the leakage current increase problem of the negative potential over bias peculiar to the TFT.

  In addition, with this method, the source data can be reduced to half of the normal drive voltage amplitude without inverting the common electrode, so that power consumption can be reduced. Similarly, the source driving circuit is low voltage and low cost.

  Further, since the formation of a special auxiliary capacitor Cs, auxiliary capacitor wiring, auxiliary capacitor inversion power source and the like are not required, the circuit scale can be reduced and the cost can be reduced.

  Further, although the gate line of the transistor Tb is driven with a larger amplitude than usual, it is a cycle of one period in two frames, and Ta is driven with a smaller amplitude than usual. Compared with the installed drive, power consumption does not increase.

  Thus, a reduction in leakage current and a reduction in power consumption can be realized.

  FIG. 9 is a schematic circuit diagram showing a configuration for performing inter-row AC control using the configuration shown in FIG.

  In this embodiment, four pixels from PXmn to PX (m + 1) (n + 1) are shown, but each pixel has the pixel configuration shown in FIG.

  In this embodiment, alternating current between rows can be realized by performing positive polarity writing and negative polarity writing in units of rows. That is, in a certain frame, the pixels PXmn and PX (m + 1) n perform the first half operation of FIG. 2 to perform positive polarity writing, and the pixels PXm (n + 1) and PX (m + 1) (n + 1) in the next row have FIG. The reverse operation is performed by performing the latter half of the operation, and the reverse operation is performed in the next frame.

  FIG. 10 is a schematic circuit diagram showing a configuration for realizing inter-matrix alternating current (dot inversion). The embodiment shown in FIG. 9 is different from the embodiment shown in FIG. It differs in that it is connected.

  That is, paying attention to the n row, in the pixel PXmn of the m column and the n row, the gate of the first transistor Ta is the first gate line Gan and the gate of the second transistor Tb is the second gate as in the case of FIG. Although connected to the gate line Gbn, in the pixel PX (m + 1) n in the (m + 1) column n row of the adjacent column, the gate of the first transistor Tc is connected to the first gate line Gan + 1 in the adjacent row, The gate of the transistor Td is connected to the second gate line Gbn + 1 in the adjacent row, and the capacitor for kickback is also connected to the gate line Gbn + 1. Thereafter, the same connection is repeated throughout.

  According to this configuration, the pixels in the adjacent columns are connected to the gate line in the next row. When viewed in the row direction, positive polarity writing and negative polarity writing are alternately performed pixel by pixel. At this time, the positive polarity writing and the negative polarity writing are reversed in the next row.

  Since these polarities are completely reversed in the next frame, inter-matrix alternating current can be realized with a simple configuration.

  FIG. 11 is a schematic circuit diagram showing a configuration in which a set of three gate lines.

  Referring to FIG. 11, for the n rows of pixels, the gates of all the transistors Ta are connected to the first gate line Gan, but the gates of the second transistors Tb and the other ends of the kickback capacitors are column. The second gate line Gbn and the third gate line Gcn are alternately connected to each other.

  In the next (n + 1) row, the connection relation for each column is reversed, and when viewed in the same column, the second row after the row where the gate of the second transistor Tb is connected to the second gate line Gbn The gate of the second transistor Tb is connected to the third gate line Gcn, and the same connection is made throughout.

  Therefore, inter-matrix alternating current can be realized by appropriately controlling the three gate lines.

  The embodiments described above should not be construed as limiting, and any embodiment conceivable with ordinary knowledge of those skilled in the art is also construed as the practice of the present invention.

It is a graph showing the relationship between gate bias and leakage current. It is explanatory drawing which shows the case where positive / negative bipolar drive is performed within a fixed amplitude. It is explanatory drawing which shows the control method which changes a gate level by positive polarity drive and negative polarity drive. 1 is a circuit diagram showing a configuration for one pixel of an active matrix liquid crystal display device according to a first embodiment of the present invention; FIG. 5 is a waveform diagram showing a gate signal waveform supplied to the apparatus shown in FIG. 4. It is a circuit diagram which shows the structure for one pixel of 2nd Embodiment of the active matrix type liquid crystal display device concerning this invention. It is a graph which shows the change of the main electric potential in the structure of FIG. The pixel capacitance Cpx is a graph showing a change in main potential when assuming only the liquid crystal capacitance Clc. It is a schematic circuit diagram which shows the structure which performs row | line | column alternating current control using the structure shown in FIG. It is a schematic circuit diagram which shows the structure which implement | achieves the alternating current between matrices (dot inversion). It is a schematic circuit diagram which shows the structure at the time of using three gate lines.

Explanation of symbols

Cgd Gate-drain capacitance Clc Liquid crystal capacitance Cpx Pixel capacitance Ga, Gb Gate line PX Pixel portion S Source line Ta, Tb Transistor

Claims (5)

  1. A pixel array including a plurality of pixel portions each having a liquid crystal element arranged in a matrix and having a pixel capacity;
    First and second gate lines provided in a plurality of row units of the pixel array and controlled independently;
    Provided in a plurality of column units of the pixel array, and a source line to which signals of positive and negative polarities are supplied according to positive and negative writing,
    The pixel portion is a plurality of transistors that selectively connect a pixel electrode and the source line, and each gate is connected to the first and second gate lines, and are connected in series. A first transistor group having a gate connected to the first gate line; and a second transistor group having a gate connected to the second gate line;
    Different transistor non-conducting selection potentials are supplied to the first gate line and the second gate line,
    The first gate line is supplied with a potential in the vicinity of a potential that causes a minimum leakage of pixel charges when the pixel electrode potential is held positive, and the pixel electrode potential is negative in the second gate line. In the vicinity of the potential that causes the minimum leakage of pixel charge when
    Each gate is connected to the pixel capacitor and the first and second gate lines, and a gate connected to the gate of the transistor closest to the liquid crystal element among the first and second transistors connected in series. A kickback capacitive element connected between the line and the liquid crystal element and having an auxiliary capacitor having a predetermined proportional relationship with the pixel capacitance, and using kickback due to charges accumulated in the kickback capacitive element. An active matrix liquid crystal display device, wherein reverse polarity writing is performed .
  2. 2. The active matrix liquid crystal display device according to claim 1 , wherein the auxiliary capacitor is formed on the first and second gate lines provided for the pixel.
  3.   2. The first transistor according to claim 1, wherein the first transistor is biased by the first gate line during positive polarity writing, and the second transistor is biased by the second gate line during reverse polarity writing. Active matrix type liquid crystal display device.
  4.   The kickback capacitance element is set such that the pixel electrode potential provides a polarity reversal amplitude for alternating current when the drop amplitude of the second gate voltage is transmitted to the pixel electrode potential. The active matrix liquid crystal display device according to claim 1, wherein:
  5.   The data supplied to the source line is set so that the low level at the time of positive polarity writing and the high level at the time of negative polarity writing, the high level at the time of positive polarity writing and the low level at the time of negative polarity writing are set substantially equal. The active matrix liquid crystal display device according to claim 1, wherein the liquid crystal display device is an active matrix liquid crystal display device.
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