WO2012147662A1 - Liquid crystal display device and driving method therefor - Google Patents

Abstract

A liquid crystal display device is provided with a liquid crystal display panel for displaying an image and a backlight for applying light to the liquid crystal display panel. The brightness of the backlight is increased so as to compensate for a decrease in the display brightness of the liquid crystal display panel due to the discharge of electric charge retained in a pixel. Consequently, flicker in the display of the liquid crystal display panel can be suppressed without an increase in power consumption.

Description

Liquid crystal display device and driving method thereof

The present invention relates to a liquid crystal display device and a driving method thereof.

In recent years, a liquid crystal display device (hereinafter referred to as a memory-type liquid crystal display device) that performs display by holding image data written in a pixel in a memory circuit in the pixel has been proposed as a liquid crystal display device (Patent Literature). 1). In a normal operation for displaying a multi-gradation moving image, a new image data is rewritten on a pixel-by-frame basis through a data signal line for display. On the other hand, in a memory operation for displaying a still image, a rewrite image is displayed. Display is performed using image data held in the memory circuit without supplying data.

Therefore, in the memory operation, the operation of the drive circuit that drives the scanning signal line and the data signal line can be stopped, so that power consumption can be greatly reduced. Therefore, the memory operation is often used for image display that is strongly demanded to reduce power consumption, such as a standby screen display of a mobile phone.

In the liquid crystal display device of Patent Document 1, one memory circuit (DM18 in FIG. 19) is provided for each pixel, and a still image display is performed using image data held in each memory circuit. .

Japanese Patent Publication “JP 2002-229532 A (published on August 16, 2002)”

In such a memory type liquid crystal display device, the frame frequency (frame rate) is generally set low in order to realize low power consumption. However, when the frame frequency is low, as shown in FIG. 8, the pixel charge amount (pixel potential) of the data in the memory circuit held in the memory circuit gradually decreases due to natural discharge (leakage), and the liquid crystal display panel Leading to a decrease in the transmittance. Then, the transmittance decreased in the N frame returns to the original transmittance as the pixel charge amount increases (charges) by the writing operation in the next N + 1 frame. By repeating such a decrease and increase in the transmittance, the luminance (display luminance, surface luminance) on the display screen changes periodically, causing a problem that flicker is visually recognized.

Therefore, it is conceivable to increase the frame frequency in order to prevent a decrease in the pixel charge amount. However, this method increases power consumption and loses the original advantages of the memory type liquid crystal display device. Such a flicker problem may also occur in a normal liquid crystal display device that does not include a memory circuit.

The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a liquid crystal display device and a driving method thereof that can suppress display flicker in a liquid crystal display panel without increasing power consumption. It is in.

In order to solve the above problems, a liquid crystal display device and a driving method thereof according to the present invention are provided.
A liquid crystal display panel for displaying an image, and a backlight for irradiating the liquid crystal display panel with light;
The luminance of the backlight is increased so as to compensate for a decrease in display luminance in the liquid crystal display panel due to discharge of charges held in the pixels.

Since the display luminance (surface luminance) of the liquid crystal display panel changes according to the pixel charge amount and the backlight luminance, the display luminance decrease due to the decrease in the pixel charge amount is displayed by the increase in the backlight luminance. By compensating for the increase in luminance, the display luminance of the liquid crystal display panel can be maintained constant. Thereby, flicker can be suppressed. In addition, since it is not necessary to increase the frame frequency, an increase in power consumption can be prevented.

As described above, in the liquid crystal display device and the driving method thereof according to the present invention, the liquid crystal display panel that displays an image, and the backlight that irradiates the liquid crystal display panel with light, and discharge of charges held in the pixels. In this configuration, the luminance of the backlight is increased so as to compensate for a decrease in display luminance in the liquid crystal display panel due to the above. Accordingly, display flicker in the liquid crystal display panel can be suppressed without increasing power consumption.

1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to Embodiment 1. FIG. FIG. 2 is a cross-sectional view illustrating a schematic configuration of a liquid crystal display panel and a backlight in the liquid crystal display device of FIG. 1. It is an equivalent circuit diagram showing a configuration of a circuit formed in a pixel region of a display pixel composed of three pixels of an R pixel, a G pixel, and a B pixel. FIG. 2 is an equivalent circuit diagram illustrating a detailed configuration of a memory circuit in the liquid crystal display device of FIG. 1. (A) to (h) are the first, second, third, and mth gate bus lines GL1, GL2, GL3, and GLm, and the first, second, third, and m lines. It is a signal waveform diagram of the memory drive selection lines SEL1, SEL2, SEL3, and SELm in the row. FIG. 5 is a signal waveform diagram in the case where black display is performed for a display pixel whose value of in-memory data MD is “1” in the memory circuit of FIG. 4. FIG. 5 is a signal waveform diagram when white display is performed for a display pixel in which the value of in-memory data MD is “0” in the memory circuit of FIG. 4. It is a figure which shows typically the change of the pixel charge amount of the data in the memory hold | maintained at the memory circuit in the conventional memory type liquid crystal display device, and the fall of the transmittance | permeability of the liquid crystal display panel at this time. FIG. 3 is a diagram schematically showing changes in pixel charge amount and backlight luminance of the liquid crystal display device according to the first embodiment. FIG. 2 is a block diagram showing a relationship between a liquid crystal display panel and a backlight in the liquid crystal display device shown in FIG. 1. It is the figure which added the PWM signal to FIG. FIG. 11 is a block diagram illustrating an overall configuration of a liquid crystal display device according to Modification Example 1. FIG. 13 is a block diagram illustrating a relationship between a liquid crystal display panel and a backlight in the liquid crystal display device illustrated in FIG. 12. FIG. 6 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a second embodiment. FIG. 15 is an equivalent circuit diagram illustrating a detailed configuration of a memory circuit in the liquid crystal display device of FIG. 14. FIG. 15 is a block diagram schematically showing a configuration of a memory circuit in the liquid crystal display device of FIG. 14. 15 is a timing chart showing a writing operation of a memory circuit in the liquid crystal display device of FIG. 15 is a timing chart showing a writing operation of a memory circuit in the liquid crystal display device of FIG. It is the equivalent circuit schematic of the pixel in the conventional liquid crystal display device.

[Embodiment 1]
An embodiment of the present invention will be described with reference to the drawings. Hereinafter, a liquid crystal display device (hereinafter, simply referred to as “liquid crystal display device”) including a memory circuit (in particular, SRAM type) will be described as an example. However, the liquid crystal display device of the present invention is not limited to this. However, a normal liquid crystal display device that does not include a memory circuit is also included.

The liquid crystal display device according to this embodiment holds image data written in a pixel in a memory circuit in the pixel and performs display using the image data held in the memory circuit during a data holding period. For example, a multi-color (multi-gradation) display mode (normal operation mode) used for screen display during operation of a mobile phone, and a memory operation mode used for screen display during standby of a mobile phone, etc. Switch to operate. The present liquid crystal display device also includes a liquid crystal display device that performs display only in the memory operation mode.

In addition, the present liquid crystal display device makes the display luminance (surface luminance) of the liquid crystal display panel uniform by adjusting the luminance (backlight luminance) of the light source (backlight) provided on the back side of the liquid crystal display panel. , The flicker is reduced.

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device 1 according to the present embodiment. The liquid crystal display device 1 includes a liquid crystal display panel 10, a display control circuit 20, and a backlight 70 (see FIG. 2). The liquid crystal display panel 10 includes a source driver 30 (data signal line driving circuit), a gate driver 40 (scanning signal line driving circuit), a display unit 50, and a memory driving driver 60 as a supply voltage generation circuit. Yes.

The display control circuit 20 includes a memory drive control unit 21 and a PWM signal generation unit 22 (see FIGS. 1 and 10).

The display unit 50 includes a source bus line (data signal line) SL, a gate bus line (scanning signal line) GL, a memory drive selection line SEL described later, a first voltage supply line AL, a second voltage supply line BL, A first power supply line VLCH and a second power supply line VLCL are included (see FIG. 3). The source bus line SL is connected to the source driver 30, the gate bus line GL and the memory drive selection line SEL are connected to the gate driver 40, and the first voltage supply line AL and the second voltage supply line BL are memory driven. Connected to the driver 60.

The display unit 50 includes a plurality of pixels provided corresponding to the intersections of the gate bus line GL and the source bus line SL. Each pixel includes a pixel electrode for applying a voltage corresponding to an image to be displayed to a liquid crystal capacitor described later, a common electrode that is a common electrode provided in common to the plurality of pixels, a pixel electrode, and a common electrode And a liquid crystal layer sandwiched between them. Further, if necessary, a storage capacitor is added in parallel with the liquid crystal capacitor formed by the pixel electrode and the common electrode.

In addition, the display unit 50 includes one bit for each display pixel including three pixels (R pixel, G pixel, and B pixel) for R (red), G (green), and B (blue). A memory circuit MR is provided as a memory circuit capable of holding data. The display pixel further includes a W pixel, a Y pixel, and the like, and may be composed of four or more pixels.

Here, the liquid crystal display device 1 will be described as a normally white type. In the liquid crystal display device 1, the driving method can be switched between the “normal operation mode” and the “memory operation mode”.

The display control circuit 20 receives image data DAT and an operation mode selection signal M sent from the outside, receives a digital video signal DV, a source start pulse signal SSP for controlling image display on the display unit 50, and a source clock signal SCK. The latch strobe signal LS, the gate start pulse signal GSP, the gate clock signal GCK, the first supply voltage control signal SAL, the second supply voltage control signal SBL, and the memory drive control signal SSEL are output. Further, the display control circuit 20 supplies a PWM (pulse width modulation) signal (driving signal) generated by the PWM signal generator 22 to the backlight 70. Details of the PWM signal generation unit 22 will be described later with reference to FIG.

The backlight 70 is composed of, for example, an LED (Light Emitting Diode), and is provided on the back side of the liquid crystal display panel 10.

The source driver 30 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS output from the display control circuit 20, and supplies a driving video signal (data) to each source bus line SL. Signal).

During normal operation, the gate driver 40 sequentially selects all the m gate bus lines GL one horizontal scanning period at a time in order to select the gate start pulse signal GSP and the gate clock signal GCK output from the display control circuit 20. The application of the active scanning signal (gate signal) to each gate bus line GL is repeated with one vertical scanning period (one frame) as a cycle.

When switching from the normal operation to the memory operation, the gate driver 40 selects the gate start pulse signal GSP output from the display control circuit 20 and the gate clock in order to sequentially select the gate bus lines GL one horizontal scanning period at a time. Based on the signal GCK, an active scanning signal is sequentially applied to each gate bus line GL and output from the display control circuit 20 in order to sequentially select each memory drive selection line SEL by one horizontal scanning period. An active signal is sequentially applied to each memory drive selection line SEL based on the memory drive control signal SSEL and the gate clock signal GCK.

During the memory operation, the gate driver 40 stops the application of the active scanning signal to each gate bus line GL, and applies the active signal to all (m) memory drive selection lines SEL1 to SELm.

Based on the first supply voltage control signal SAL and the second supply voltage control signal SBL output from the display control circuit 20, the memory driving driver 60 uses the first voltage supply line AL and the second voltage supply line. A voltage signal is applied to BL.

(Circuit configuration of display pixel)
FIG. 2 is a cross-sectional view showing a schematic configuration of the liquid crystal display panel 10 and the backlight 70. In FIG. 2, each signal line is omitted for convenience.

As shown in FIG. 2, the liquid crystal display panel 10 includes an active matrix substrate 11 and a counter substrate 12 which are arranged to face each other, and a liquid crystal layer 13 provided between the substrates 11 and 12. . The backlight 70 is provided on the back side of the liquid crystal display panel 10 and irradiates the liquid crystal display panel 10 with light.

The active matrix substrate 11 is provided on the glass substrate 14 so as to extend in parallel to each other in a direction orthogonal to the gate bus lines GL, and a plurality (m) of gate bus lines GL provided to extend in parallel to each other. And a plurality of source bus lines SL, and switching element transistor TFTs (not shown) provided at intersections of the gate bus lines GL and the source bus lines SL. An interlayer insulating film 15 is laminated so as to cover the transistor TFT, and a pixel electrode 16 is provided on the interlayer insulating film 15.

In the counter substrate 12, a black matrix (not shown) and a color filter 18 are formed on a glass substrate 17, a common electrode 19 (com, counter electrode) is formed thereon, and an alignment film (cover) (Not shown) is formed.

FIG. 3 is an equivalent circuit diagram showing a configuration of a circuit (hereinafter referred to as “display pixel circuit”) formed in a pixel region of a display pixel composed of three pixels of an R pixel, a G pixel, and a B pixel. This display pixel circuit includes common portions 50R, 50G, and 50B having a configuration common to the three pixels, and memory circuits MR, MG, and MB as memory circuits.

The configuration of the common units 50R, 50G, and 50B will be described by taking the configuration of the common unit 50R of the R pixel for R color as an example. The common unit 50R includes switches SWR1, SWR3, and SWR4 realized by N-type TFTs, a switch SWR2 realized by P-type TFTs, a liquid crystal capacitor 51R, and a holding capacitor 53R. One ends of the liquid crystal capacitor 51R and the holding capacitor 53R are connected to the pixel electrode 55R (corresponding to reference numeral 16 in FIG. 2). The other end of the liquid crystal capacitor 51R is connected to the common electrode 52 (corresponding to reference numeral 19 in FIG. 2), and the other end of the storage capacitor 53R is connected to the storage capacitor electrode.

Regarding the switch SWR1 in the common unit 50R, the gate terminal is connected to the gate bus line GL, the source terminal is connected to the source bus line SLR, and the drain terminal is connected to the source terminal of the switch SWR2 and the source terminal of the switch SWR4. Yes. As for the switches SWR2 and SWR3, the gate terminal is connected to the memory drive selection line SEL, and the drain terminal is connected to the pixel electrode 55R. The source terminal of the switch SWR3 is connected to the memory circuit MR.

With the above configuration, a switching circuit is realized by the switch SWR2 and the switch SWR3. That is, the switch SWR2 and the switch SWR3 (switching circuit) are a voltage signal given to the pixel electrode 55R, a voltage signal (video signal) given from the source bus line SLR via the switch SWR1, and a voltage given from the memory circuit MR. Switch between signals.

(Circuit configuration of memory circuit)
Next, a detailed configuration of the memory circuit MR will be described. FIG. 4 is an equivalent circuit diagram showing a detailed configuration of the memory circuit MR. This memory circuit MR includes CMOS switches SWM1 and SWM2 composed of P-type TFTs and N-type TFTs, switches SWM4 and SWM6 realized by N-type TFTs, and switches SWM3, SWM5 and SWM7 realized by P-type TFTs. It has.

The source terminals of the switches SWM3 and SWM5 are connected to the first power supply line VLCH. On the other hand, the source terminals of the switches SWM4 and SWM6 are connected to the second power supply line VLCL. The gate terminal of the switch SWM7 is connected to the gate bus line GL. A circuit composed of the switches SWM3 and SWM4 and a circuit composed of the switches SWM5 and SWM6 function as an inverter circuit, and the switch SWM7 functions as a transfer gate.

With the above configuration, the circuit composed of the switches SWM3, SWM4, SWM5, SWM6, and SWM7 functions as a data holding circuit 59 that holds 1-bit data.

Regarding the switch SWM1, the input terminal is connected to the first voltage supply line AL, and the output terminal is connected to the source terminal of the switch SWR3 and the output terminal of the switch SWM2. The switch SWM2 has an input terminal connected to the second voltage supply line BL, and an output terminal connected to the source terminal of the switch SWR3 and the output terminal of the switch SWM1.

The gate terminal of the N-type TFT of the switch SWM1 is connected to the drain terminal of the switch SWR4 and the data holding circuit 59. The gate terminal of the P-type TFT of the switch SWM1 is connected to the gate terminal of the N-type TFT of the switch SWM2 and the data holding circuit 59. The gate terminal of the N-type TFT of the switch SWM2 is connected to the gate terminal of the P-type TFT of the switch SWM1 and the data holding circuit 59. The gate terminal of the P-type TFT of the switch SWM2 is connected to the data holding circuit 59.

The above configuration is configured not only in the source bus line SLR but also in the source bus lines SLG and SLB, and RGB data is stored in the memory circuits MR, MG, and MB.

(Driving method)
Next, a method for driving the liquid crystal display device 1 will be described with reference to FIGS. 3, 4, and 5. In the following description, it is assumed that the liquid crystal display device 1 is provided with m gate bus lines. FIG. 5 shows the first, second, third, and m-th gate bus lines GL1, GL2, GL3, and GLm, and the first, second, third, and m-th memory drives. It is a signal waveform diagram of selection lines SEL1, SEL2, SEL3, SELm. In the present embodiment, as described above, switching between the normal operation mode and the memory operation mode is performed. This switching is performed based on an operation mode selection signal M sent from the outside to the display control circuit 20. Hereinafter, a driving method during normal operation, a driving method when switching from normal operation to memory operation, and a driving method during memory operation will be described in order.

(Driving method during normal operation)
In FIG. 5, the normal operation is performed from time t0 to time t1. During normal operation, as shown in FIGS. 5A to 5D, active scanning signals are given to the gate bus lines GL1 to GLm in order for a predetermined period. On the other hand, during normal operation, no active signal is applied to the memory drive selection lines SEL1 to SELm.

Here, focusing on a certain display pixel, when an active scanning signal is applied to the gate bus line GL provided corresponding to the display pixel, the switches SWR1, SWG1, and SWB1 are turned on. Since no active signal is applied to the memory drive selection line SEL during normal operation, the switches SWR2, SWG2, and SWB2 are turned on, and the switches SWR3, SWG3, SWB3, and SWR4, SWG4, SWB4 are turned off. Thus, writing to the liquid crystal capacitors 51R, 51G, and 51B is performed based on the video signals applied to the source bus lines SLR, SLG, and SLB, respectively. In this manner, video signals are written to the liquid crystal capacitors 51R, 51G, and 51B for all the display pixels within one frame period, and a desired image is displayed on the display unit 50.

(Driving method when switching from normal operation to memory operation)
In FIG. 5, during the period from time t1 to time t2, driving for switching from normal operation to memory operation is performed. During this period, as shown in FIGS. 5A to 5D, an active scanning signal is given to each of the gate bus lines GL1 to GLm in order for a predetermined period, and FIGS. As shown in h), an active signal is given to each of the memory drive selection lines SEL1 to SELm in order for a predetermined period.

Here, focusing on a certain display pixel, an active scanning signal is applied to the gate bus line GL provided corresponding to the display pixel, and a memory drive selection provided corresponding to the display pixel. When an active signal is applied to the line SEL, the switches SWR1, SWG1, and SWB1 are turned on, the switches SWR2, SWG2, and SWB2 are turned off, and the switches SWR3, SWG3, and SWB3 are turned on. Also, the switches SWR4, SWG4, and SWB4 are turned on. Thereby, the video signals applied to the source bus lines SLR, SLG, and SLB are given to the respective memory circuits MR, MG, and MB, and the video signals are stored in the memory circuits MR, MG, and MB as in-memory data MD. Is stored in the data holding circuit 59.

In this way, the in-memory data MD is stored in the memory circuits MR, MG, and MG for all the display pixels during the period from the time point t1 to the time point t2. In the following, when the video signal is binarized (when the logic level is divided into high level data and low level data), if the logic level is high level, it is stored in the memory. It is assumed that “1” is stored in the memory circuits MR, MG, and MB as the data MD, and “0” is stored in the memory circuits MR, MG, and MB as the in-memory data MD if the logic level is low. To do.

(Driving method during memory operation)
In FIG. 5, the memory operation is performed from time t2 to time t3. During memory operation, as shown in FIGS. 5A to 5D, active scanning signals are not applied to the gate bus lines GL1 to GLm. Therefore, during this period, the switches SWR1, SWG1, and SWB1 are always off. In this way, since the switches SWR1, SWG1, and SWB1 are turned off, the value of the in-memory data MD is the value of the video signal supplied by the source bus lines SLR, SLG, and SLB during the memory operation period. It will not be affected.

On the other hand, during this period, as shown in (e) to (h) of FIG. 5, active signals are given to all the memory drive selection lines SEL1 to SELm. Therefore, during the period when the memory operation is performed, the switches SWR2, SWG2, and SWB2 are always in the off state, and the switches SWR3, SWG3, and SWB3 are always in the on state. Thus, writing to the liquid crystal capacitors 51R, 51G, and 51B is performed based on the voltage signal output from the output terminal of the switch SWM1 or the output terminal of the switch SWM2 in the memory circuits MR, MG, and MB. Thus, during the memory operation, writing is performed in the liquid crystal capacitors 51R, 51G, and 51B based on the voltage signals of the respective memory circuits MR, MG, and MB. For this reason, monochrome display is performed during the memory operation. Hereinafter, the memory operation will be described in detail with an example.

FIG. 6 is a signal waveform diagram when black display is performed for a display pixel whose value of the data MD in the memory is “1”. By the way, in order to prevent the deterioration of the liquid crystal due to the application of the DC voltage, the common electrode 52 is inverted and driven during both the normal operation and the memory operation. That is, the potential Vcont of the common electrode 52 is switched between a high potential and a low potential at a predetermined interval.

Focusing on the on / off states of the switches SWM3 to SWM7 in the data holding circuit 59, when the in-memory data MD is “1”, the switch SWM3 is turned off and the switch SWM4 is turned on. For this reason, a low-potential power supply voltage is applied from the second power supply line VLCL to the data holding circuit 59 via the switch SWM4. As a result, the switch SWM5 is turned on and the switch SWM6 is turned off. As a result, a high power supply voltage is applied from the first power supply line VLCH to the data holding circuit 59 via the switch SWM5. As described above, since no active signal is applied to the gate bus line GL during the memory operation, the switch SWM7 is in the on state regardless of the value of the in-memory data MD. For this reason, the value of the in-memory data MD is held during the period in which the memory operation is performed.

As described above, since a low-potential power supply voltage is applied to the data holding circuit 59 via the switch SWM4, the P-type TFT of the switch SWM1 is turned on and the N-type TFT of the switch SWM2 is turned off. On the other hand, since a high-potential power supply voltage is applied to the data holding circuit 59 via the switch SWM5 and the switch SWM7 is on, the N-type TFT of the switch SWM1 is on and the P of the switch SWM2 is on. The type TFT is turned off. As a result, the switch SWM1 is turned on and the switch SWM2 is turned off. As a result, a voltage (hereinafter referred to as “first supply voltage”) VAL supplied from the first voltage supply line AL is applied to the pixel electrodes 55R, 55G, and 55B of the pixels.

In the present embodiment, as shown in FIGS. 6B and 6C, when the potential Vcont of the common electrode 52 is set to the high potential side (period T11), the first supply voltage VAL is used. Is set on the low potential side, and when the potential Vcont of the common electrode 52 is set on the low potential side (period T12), the potential of the first supply voltage VAL is set on the high potential side. Therefore, a high voltage is always applied to the liquid crystal capacitors 51R, 51G, and 51B, and black display is performed for the display pixels including the liquid crystal capacitors 51R, 51G, and 51B. That is, a negative (−) black display is displayed in the period T11, and a positive (+) black display is displayed in the period T12.

FIG. 7 is a signal waveform diagram when white display is performed for the display pixel whose value of the data MD in the memory is “0”. Focusing on the on / off states of the switches SWM3 to SWM7 in the data holding circuit 59, when the in-memory data MD is “0”, the switch SWM3 is on and the switch SWM4 is off. Therefore, a high-potential power supply voltage is applied from the first power supply line VLCH to the data holding circuit 59 via the switch SWM3. As a result, the switch SWM5 is turned off and the switch SWM6 is turned on. As a result, a low-potential power supply voltage is applied from the second power supply line VLCL to the data holding circuit 59 via the switch SWM6. Note that the switch SWM7 is in an ON state as in the case where the value of the in-memory data MD is “1”. For this reason, the value of the in-memory data MD is held during the period in which the memory operation is performed.

As described above, since a high-potential power supply voltage is applied to the data holding circuit 59 via the switch SWM3, the P-type TFT of the switch SWM1 is turned off and the N-type TFT of the switch SWM2 is turned on. On the other hand, since a low-potential power supply voltage is applied to the data holding circuit 59 via the switch SWM6 and the switch SWM7 is on, the N-type TFT of the switch SWM1 is off and the P of the switch SWM2 is turned on. The type TFT is turned on. As a result, the switch SWM1 is turned off and the switch SWM2 is turned on. As a result, a voltage signal (hereinafter referred to as “second supply voltage”) applied from the second voltage supply line BL is applied to the pixel electrodes 55R, 55G, and 55B of the pixels.

In the present embodiment, as shown in FIGS. 7B and 7D, when the potential Vcont of the common electrode 52 is set to the high potential side (period T21), the second supply voltage VBL Is set on the high potential side, and when the potential Vcont of the common electrode 52 is set on the low potential side (period T22), the potential of the second supply voltage VBL is set on the low potential side. Therefore, a low voltage is always applied to the liquid crystal capacitors 51R, 51G, and 51B, and white display is performed on the display pixels including the liquid crystal capacitors 51R, 51G, and 51B. That is, positive (+) white display is obtained in the period T21 and negative (−) white display is obtained in the period T22.

In this embodiment, one display pixel is composed of three pixels (R pixel, G pixel, and B pixel). However, the present invention is not limited to this, and a W pixel, a Y pixel, and the like are further included. Including four or more pixels.

In this embodiment, the memory circuit is provided in each of the three pixels (R pixel, G pixel, and B pixel), but the present invention is not limited to this, and one pixel (R pixel, G pixel, or (B pixel) may be provided only.

By using the above configuration and driving method, monochrome display can be performed during memory operation.

Here, in the memory type liquid crystal display device, as shown in FIG. 8, the pixel charge amount (pixel potential) of the in-memory data MD held in the memory circuit gradually decreases due to natural discharge (leakage). The transmittance of the liquid crystal display panel 10 is reduced. The transmittance decreased in the N frame returns to the original transmittance when the pixel charge amount is increased (charged) by the writing operation in the next N + 1 frame. By repeating such a decrease and increase in transmittance, the luminance (display luminance) on the display screen changes periodically, causing a problem that flicker is visually recognized.

Therefore, the liquid crystal display device 1 according to the present embodiment has a configuration that compensates for the decrease in transmittance due to the discharge by increasing the backlight luminance.

FIG. 9 is a diagram schematically showing how the pixel charge amount (pixel potential) and the backlight luminance of the liquid crystal display device 1 change. 9A shows a change in display luminance of the liquid crystal display panel 10, FIG. 9B shows a change in pixel charge amount, and FIG. 9C shows a change in backlight luminance.

Since the display luminance of the liquid crystal display panel 10 changes in accordance with the pixel charge amount and the backlight luminance, as shown in FIG. 9, the display luminance decrease due to the decrease in the pixel charge amount is increased as the backlight luminance increases. By compensating for the increase in display brightness caused by the above, the display brightness of the liquid crystal display panel 10 can be kept constant. Thereby, flicker can be suppressed. In addition, since it is not necessary to increase the frame frequency, an increase in power consumption can be prevented.

Next, a configuration for adjusting the backlight luminance as shown in FIG. 9C will be described.

FIG. 10 is a block diagram showing the relationship between the liquid crystal display panel 10 and the backlight 70 in the liquid crystal display device 1 shown in FIG.

The display control circuit 20 includes a PWM signal generator 22 as shown in FIG.

The PWM signal generation unit 22 generates a PWM signal for displaying the target luminance based on the amount of change (decrease amount) in the luminance of the liquid crystal display panel 10 caused by natural discharge. Here, since the amount of decrease in the luminance of the liquid crystal display panel 10 can be calculated in advance based on the frame frequency, a desired PWM signal corresponding to the calculated amount of decrease in luminance can be generated. For example, it can be realized by a configuration in which the frame frequency set in the liquid crystal display panel 10 and the pulse width (or duty ratio) of the PWM signal are associated with a table in advance. The PWM signal generation unit 22 supplies the generated PWM signal to the backlight 70 in synchronization with the timing of the frame period.

FIG. 11D shows a change in the PWM signal generated by the PWM signal generation unit 22. As shown in the figure, it can be seen that the pulse width of the PWM signal increases as the pixel charge amount decreases, thereby increasing the luminance of the backlight. By supplying such a PWM signal to the backlight 70, it is possible to compensate and equalize the decrease in display luminance of the liquid crystal display panel 10 (see FIG. 8) (see FIG. 11A).

Here, in the configuration of the liquid crystal display device 1 described above, an operation of inverting the polarity at a predetermined period is performed in one frame period. However, the liquid crystal display device of the present invention is not limited to this, and the frame frequency and the polarity The inversion period may be the same.

Further, when the in-memory data MD of the memory circuit MR is refreshed at the time of polarity inversion in one frame period, the pulse width of the PWM signal may be set based on the polarity inversion period.

(Modification 1)
FIG. 12 is a block diagram illustrating an overall configuration of a liquid crystal display device 1a according to the first modification. FIG. 13 is a block diagram showing the relationship between the liquid crystal display panel 10 and the backlight 70 in the liquid crystal display device 1a shown in FIG.

In the liquid crystal display device 1a according to the modified example 1, the charge amount detection unit 10a is added to the liquid crystal display panel 10 as compared with the liquid crystal display device 1 described above.

The charge amount detection unit 10 a detects the pixel charge amount in the in-memory data MD held in the memory circuit MR, and gives the detection result to the PWM signal generation unit 22 of the display control circuit 20. For example, the charge amount detection unit 10a detects the amount of decrease in charge with respect to the amount of charge at the time of data writing in the memory circuit MR.

The PWM signal generation unit 22 determines the pulse width of the PWM signal based on the detection result (charge reduction amount) acquired from the charge amount detection unit 10a.

As described above, by feeding back the pixel charge amount (charge decrease amount) detected in the memory circuit MR, a more accurate correction value (backlight luminance increase amount) can be calculated. Therefore, the display brightness of the liquid crystal display panel 10 can be made more uniform.

In the present liquid crystal display device 1a, since the backlight luminance can be adjusted based on the pixel charge amount of the memory circuit MR, the frame frequency can be set regardless of the backlight luminance. For example, the frame frequency may be set lower than in the past, or may be changed without being a constant value. Thereby, power consumption can be further reduced.

[Embodiment 2]
Next, another embodiment of the present invention will be described with reference to the drawings. The configuration of a liquid crystal display device (hereinafter simply referred to as “liquid crystal display device”) including a DRAM type memory circuit will be described below. For convenience of explanation, the terms defined in the first embodiment are used in accordance with the definitions in the second embodiment unless otherwise specified.

FIG. 14 is a block diagram showing an overall configuration of the liquid crystal display device 2 according to the present embodiment. The liquid crystal display device 2 includes a liquid crystal display panel 10b, a display control circuit 20, and a backlight 70 (see FIG. 2). The liquid crystal display panel 10b includes a gate driver / CS driver 80 (scanning signal line driving circuit / holding capacity wiring driving circuit), a control signal buffer circuit 90, a driving signal generation circuit / video signal generation circuit 100, a demultiplexer 110, and A display unit 120 is included.

The display unit 120 includes a source bus line (data signal line) SL, a gate bus line (scanning signal line) GL, a CS line (holding capacitor line) CSL, a data transfer control line (data transfer line) DT, and a refresh output control line. (Refresh line) RC and output signal line vd are included. The source bus line SL is connected to the demultiplexer 110, the gate bus line GL and the CS line CSL are connected to the gate driver / CS driver 80, and the data transfer control line DT and the refresh output control line RC are controlled signal buffer circuits. 90.

The display unit 120 includes a plurality of pixels provided corresponding to the intersections of the gate bus line GL and the source bus line SL. Each pixel includes a pixel electrode for applying a voltage corresponding to an image to be displayed to the liquid crystal capacitor, a common electrode that is a common electrode provided in common to the plurality of pixels, and a gap between the pixel electrode and the common electrode. And a liquid crystal layer sandwiched between the two. In addition, a storage capacitor is added in parallel with the liquid crystal capacitor formed by the pixel electrode and the common electrode.

In addition, the display unit 120 includes one bit for each display pixel including three pixels (R pixel, G pixel, and B pixel) for R (red), G (green), and B (blue). A memory circuit MR is provided as a memory circuit capable of holding data. The display pixel further includes a W pixel, a Y pixel, and the like, and may be composed of four or more pixels.

Here, it is assumed that the liquid crystal display device 2 is a normally white type. In the liquid crystal display device 2, the driving method can be switched between the “normal operation mode” and the “memory operation mode”.

The display control circuit 20 receives image data DAT and an operation mode selection signal M sent from the outside, receives a digital video signal DV, a source start pulse signal SSP and a source clock signal SCK for controlling image display on the display unit 120. And a latch strobe signal LS. In addition, the display control circuit 20 supplies the PWM signal (drive signal) generated by the PWM signal generation unit 22 to the backlight 70.

The backlight 70 is composed of, for example, an LED (Light Emitting Diode), and is provided on the back side of the liquid crystal display panel 10b.

The drive signal generation circuit / video signal generation circuit 100 is a control drive circuit for performing image display (normal operation) and memory operation, and not only the timing used for the memory operation but also the source start pulse signal used for the normal operation. It can also serve as a circuit for generating timings such as SSP, source clock signal SCK, latch strobe signal LS, gate start pulse signal GSP, and gate clock signal GCK.

The drive signal generation circuit / video signal generation circuit 100 outputs a multi-grayscale video signal from the video output terminal in the normal operation mode (memory circuit non-operation), and the source bus line SL via the output signal line vd and the demultiplexer 110. Drive. The drive signal generation circuit / video signal generation circuit 100 simultaneously outputs a signal s1 for driving and controlling the gate driver / CS driver 80. As a result, image data is written to each pixel, and multi-gradation display is performed.

The drive signal generation circuit / video signal generation circuit 100 sends image data held in the pixel from the video output terminal to the source bus line SL via the output signal line vd and the demultiplexer 110 during the memory operation. At the same time, a signal s2 for driving and controlling the gate driver / CS driver 80 and a signal s3 for driving and controlling the control signal buffer circuit 90 are output. As a result, the image data is written to the pixel and displayed and held, or the image data held in the pixel is read out.

However, since the image data written in the pixel and held in the memory circuit MR may be used only for display, the reading operation from the pixel is not necessarily performed. Image data output from the video output terminal to the output signal line vd (k) by the drive signal generation circuit / video signal generation circuit 100 in the memory operation mode is represented by a first potential level and a second potential level. It is a binary level.

The display control circuit 20 may be included in the drive signal generation circuit / video signal generation circuit 100.

The demultiplexer 110 distributes the image data output to the output signal line vd to the corresponding source bus line SL for output.

The drive signal generation circuit / video signal generation circuit 100 and the demultiplexer 110 also have a function as a general source driver (data signal line drive circuit). Hereinafter, it is also referred to as a source driver as necessary.

The above operation is a driving method commonly called CS driving, and a liquid crystal capacitor formed by a pixel electrode for realizing liquid crystal display and a common electrode (COM) facing the liquid crystal via the liquid crystal, and a pixel In this method, a storage capacitor (auxiliary capacitor) formed by a pixel electrode and a CS line (storage capacitor line) CSL is driven independently. On the other hand, as another general driving method, a driving method in which the voltage of the common electrode COM connected to the liquid crystal capacitor and the voltage of the CS line CSL connected to the storage capacitor changes in synchronization, or the common electrode COM and CS There are a driving method in which the line CSL has the same potential and the changing timing is the same, and a driving method in which the common electrode COM and the CS line CSL have different potentials but the changing timing is the same.

(Driving method during memory operation)
Next, the memory operation of the liquid crystal display device 2 having the memory circuit MR will be described together with the configuration of the memory circuit MR. In the memory operation, the data signal potential (image data) written in the pixel is held by the memory circuit MR, and display is performed while performing the refresh operation in the data holding period.

FIG. 15 is an equivalent circuit diagram showing a configuration of the memory circuit MR according to the liquid crystal display device 2.

The memory circuit MR includes a switch circuit SW, a first data holding unit DS1, a data transfer unit TS, a second data holding unit DS2, and a refresh output control unit RS.

The switch circuit SW includes a transistor N1 (first transistor) that is an N-channel TFT. The first data holding unit DS1 includes a capacitor Ca (first holding capacitor). The data transfer unit TS includes a transistor N2 (second transistor) which is an N-channel TFT as a transfer element. The second data holding unit DS2 includes a capacitor Cb (second holding capacitor). The refresh output control unit RS includes a transistor N3 (fourth transistor) that is an N-channel TFT and a transistor N4 (third transistor) that is an N-channel TFT. The capacitance Ca is set so that the capacitance value is larger than the capacitance Cb.

In the memory circuit MR of FIG. 15, all transistors are N-channel TFTs (field effect transistors).

Also, the above-described gate bus line GL, data transfer control line DT, refresh output control line RC, source bus line SL, and CS line CSL are provided as signal lines for driving each memory circuit MR.

The gate terminal (control terminal) of the transistor N1 is connected to the gate bus line GL, the source terminal of the transistor N1 is connected to the source bus line SL, and the drain terminal of the transistor N1 is a node PIX (holding node) that is one end of the capacitor Ca. It is connected to the. The other end of the capacitor Ca is connected to the CS line CSL. When the transistor N1 is in the ON state, the switch circuit SW is in the conductive state, and when the transistor N1 is in the OFF state, the switch circuit SW is in the cutoff state.

The gate terminal of the transistor N2 is connected to the data transfer control line DT, the source terminal of the transistor N2 is connected to the node PIX, and the drain terminal of the transistor N2 is connected to a node MRY (holding node) that is one end of the capacitor Cb. . The other end of the capacitor Cb is connected to the CS line CSL. When the transistor N2 is in an ON state, the data transfer unit TS is in a state for performing a transfer operation, and when the transistor N2 is in an OFF state, the data transfer unit TS is in a state for performing a non-transfer operation.

The gate terminal of the transistor N3 is connected to the node MRY as the input terminal IN of the refresh output control unit RS, the source terminal of the transistor N3 is connected to the data transfer control line DT, and the drain terminal of the transistor N3 is connected to the source terminal of the transistor N4. Has been. The gate terminal of the transistor N4 is connected to the refresh output control line RC, and the drain terminal of the transistor N4 is connected to the node PIX as the output terminal OUT of the refresh output control unit RS. That is, the transistor N3 and the transistor N4 are connected in series so that the transistor N3 is arranged on the input side of the refresh output control unit RS between the input of the refresh output control unit RS and the output of the refresh output control unit RS. It is connected to the. Note that the connection positions of the transistors N3 and N4 may be interchanged, and the transistors N3 and N4 are connected in series between the input of the refresh output control unit RS and the output of the refresh output control unit RS. It only has to be connected to.

When the transistor N4 is in the ON state, the refresh output control unit RS is controlled to perform the first operation, and when the transistor N4 is in the OFF state, the refresh output control unit RS performs the second operation. Controlled. Since the transistor N3 is an N-channel type, when the refresh output control unit RS performs the first operation, the control information that is in the active state, that is, the active level is High, and the control information that is in the inactive state, that is, inactive The level is Low.

The first operation is performed to the refresh output control unit RS in accordance with control information indicating whether the binary level held in the second data holding unit DS2 is the first potential level or the second potential level. This is an operation to select whether to enter an active state in which the first data holding unit DS1 is supplied as an output of the refresh output control unit RS or to be in an inactive state in which the output of the refresh output control unit RS is stopped .

The second operation is an operation to stop the output of the refresh output control unit RS regardless of the control information.

Note that a liquid crystal capacitor Clc is connected between the node PIX and the counter electrode (common electrode) COM.

FIG. 16 is a block diagram schematically showing the configuration of the memory circuit MR.

The memory circuit MR includes a switch circuit SW, a first data holding unit DS, a data transfer unit TS, a second data holding unit DS2, a refresh output control unit RS, and a supply source VS.

The memory circuit MR is also provided with a data input line IN corresponding to the source bus line SL, a switch control line SC corresponding to the gate bus line GL, a data transfer control line DT, and a refresh output control line RC. .

The switch circuit SW is selectively turned on and off between the data input line IN and the first data holding unit DS1 by being driven by the gate driver / CS driver 80 via the switch control line SC.

The first data holding unit DS1 holds a binary level input to the first data holding unit DS1.

The data transfer unit TS is driven by the control signal buffer circuit 90 via the data transfer control line DT, whereby the first data holding unit DS1 holds the binary level held in the first data holding unit DS1. The transfer operation for transferring to the second data holding unit DS2 as it is and the non-transfer operation for not performing the transfer operation are selectively performed. Since the signal supplied to the data transfer control line DT is common to all the memory circuits MR, the data transfer control line DT is not necessarily provided for each row and driven by the control signal buffer circuit 90. It may be driven by the signal generation circuit / video signal generation circuit 100 or others.

The second data holding unit DS2 holds the binary level input to the second data holding unit DS2.

The refresh output control unit RS is selectively controlled to be in a state of performing the first operation or a state of performing the second operation by being driven by the control signal buffer circuit 90 via the refresh output control line RC. Since the signal supplied to the refresh output control line RC is common to all the memory circuits MR, the refresh output control line RC is not necessarily provided for each row and driven by the control signal buffer circuit 90. It may be driven by the signal generation circuit / video signal generation circuit 100 or others.

The supply source VS supplies a set potential to the input of the refresh output control unit RS.

(Operation of memory circuit MR)
Next, the operation of the memory circuit MR having the above configuration will be specifically described with reference to a timing chart. Here, since the basic operation of the memory circuit MR is mainly described, the potential fluctuation caused by the parasitic capacitance is not considered.

17 and 18 show the data write operation of the memory circuit MR. In the present embodiment, each row of the display unit 120 is driven (scanned) in a line sequential manner. Therefore, the writing period T1 is determined for each row, and the writing period T1 for i rows is denoted as T1i. FIG. 17 shows a case where “1” = High is written as the first data in the writing period T1i, and FIG. 18 shows a case where “0” = Low is written as the second data in the writing period T1i. Yes.

In FIG. 17, the gate signal line GL (i), the data transfer control line DT (i), and the refresh output control line RC (i) are sent from the control signal buffer circuit 90 to High (active level) and Low (non-active). A binary level potential consisting of (active level) is applied. The binary level High potential and Low potential may be set individually for each of the above lines. The source bus line SL (j) has a binary level consisting of High and Low lower than the High potential of the gate bus line GL (i) from the drive signal generation circuit / video signal generation circuit 100 via the demultiplexer 110. Is output. The high potential of the data transfer control line DT (i) is equal to either the high potential of the source bus line SL (j) or the high potential of the gate bus line GL (i), and the data transfer control line DT (i) Is equal to the low potential of the binary level. The potential (CS potential) supplied by the CS line CSL (i) is constant. Note that i and j are integers of 1 or more.

For the data write operation, a write period T1i (normal operation mode) and a refresh period T2 (memory operation mode) are provided. The writing period T1i starts from a time twi determined for each row. The refresh period T2 is started simultaneously from the time tr for all the rows after the data writing to the memory circuits MR for all the rows is completed. The writing period T1i is a period in which data to be held in the memory circuit MR is written, and is composed of a period t1i and a period t2i that are successively arranged. The refresh period T2 is a period in which data written in the memory circuit MR is held while being refreshed, and has a period t3 to a period t14 that are successively arranged.

In the writing period T1i, in the period t1i, the potentials of the gate bus line GL (i) and the data transfer control line DT (i) are both High. The potential of the refresh output control line RC (i) is Low. As a result, the transistors N1 and N2 are turned on, so that the switch circuit SW is in a conductive state, the data transfer unit TS is in a transfer operation state, and the first potential level supplied to the source bus line SL (j) at the node PIX. (Here, “High”) is written. In the period t2i, the potential of the gate bus line GL (i) becomes Low, while the potential of the data transfer control line DT (i) remains High. The potential of the refresh output control line RC (i) is Low. As a result, the transistor N1 is turned off, so that the switch circuit SW is turned off. In addition, since the transistor N2 is kept in the ON state, the data transfer unit TS maintains the transfer operation state. Accordingly, the first potential level is transferred from the node PIX to the node MRY, and the nodes PIX and MRY are disconnected from the source bus line SL (j).

Next, the refresh period T2 starts. In the refresh period T2, the potential of the source bus line SL (j) is set to High, which is the first potential level. The gate bus line GL (i), the data transfer control line DT (i), and the refresh output control line RC (i) are driven as described below for all rows. In other words, all memory circuits MR are refreshed all at once (hereinafter, this may be referred to as “all refresh operation”).

In the refresh period T2, in the period t3, the potential of the gate bus line GL (i) becomes Low, the potential of the data transfer control line DT (i) becomes Low, and the potential of the refresh output control line RC (i) becomes Low. . As a result, the transistor N2 is turned off, so that the data transfer unit TS performs a non-transfer operation, and the node PIX and the node MRY are separated from each other. Both the node PIX and the node MRY hold High.

In the period t4, the potential of the gate bus line GL (i) becomes High, the potential of the data transfer control line DT (i) continues to be Low, and the potential of the refresh output control line RC (i) continues to be Low. Accordingly, since the transistor N1 is turned on, the switch circuit SW is turned on, and the high potential is again written from the source bus line SL (j) to the node PIX.

In a period t5, the potential of the gate bus line GL (i) becomes Low, the potential of the data transfer control line DT (i) continues Low, and the potential of the refresh output control line RC (i) continues Low. Accordingly, since the transistor N1 is turned off, the switch circuit SW is turned off, and the node PIX is disconnected from the source bus line SL (j) and holds High.

In the period t6, the potential of the gate bus line GL (i) is kept low, the potential of the data transfer control line DT (i) is kept low, and the potential of the refresh output control line RC (i) becomes High. Thereby, the transistor N4 is turned on, and the refresh output control unit RS performs the first operation. Further, since the potential of the node MRY is High, the transistor N3 is in the ON state, so that the refresh output control unit RS is in the active state, and the data transfer control line DT (i) is connected to the node PIX via the transistors N3 and N4. A low potential is supplied.

In period t7, the potential of the gate bus line GL (i) is kept low, the potential of the data transfer control line DT (i) is kept low, and the potential of the refresh output control line RC (i) is low. As a result, the transistor N4 is turned off, so that the refresh output control unit RS is in a state of performing the second operation, and the node PIX is disconnected from the data transfer control line DT (i) and holds Low.

In a period t8, the potential of the gate bus line GL (i) is kept low, the potential of the data transfer control line DT (i) is high, and the potential of the refresh output control line RC (i) is kept low. As a result, the transistor N2 is turned on, so that the data transfer unit TS is in a transfer operation state. At this time, charge movement occurs between the capacitor Ca and the capacitor Cb, and the potentials of both the node PIX and the node MRY become Low. The potential of the node PIX rises by a slight voltage ΔVx due to the transfer of positive charges from the capacitor Cb to the capacitor Ca via the transistor N2, but is within the low potential range.

This period t8 is a period in which the refreshed binary data is held by both the first data holding unit DS1 and the second data holding unit DS2 connected to each other via the data transfer unit TS, and is set to be long. Is possible.

In the period t9, the potential of the gate bus line GL (i) is kept low, the potential of the data transfer control line DT (i) is low, and the potential of the refresh output control line RC (i) is kept low. As a result, the transistor N2 is turned off, so that the data transfer unit TS performs a non-transfer operation, and the node PIX and the node MRY are separated from each other. Both the node PIX and the node MRY hold Low.

In period t10, the potential of the gate bus line GL (i) becomes High, the potential of the data transfer control line DT (i) continues to be Low, and the potential of the refresh output control line RC (i) continues to be Low. Accordingly, since the transistor N1 is turned on, the switch circuit SW is turned on, and the high potential is written to the node PIX from the source bus line SL (j) again.

In the period t11, the potential of the gate bus line GL (i) becomes Low, the potential of the data transfer control line DT (i) continues Low, and the potential of the refresh output control line RC (i) continues Low. Accordingly, since the transistor N1 is turned off, the switch circuit SW is turned off, and the node PIX is disconnected from the source bus line SL (j) and holds High.

In the period t12, the potential of the gate bus line GL (i) is kept low, the potential of the data transfer control line DT (i) is kept low, and the potential of the refresh output control line RC (i) becomes High. Thereby, since the transistor N4 is turned on, the refresh output control unit RS is in a state of performing the first operation. Since the transistor N3 is in the OFF state because the potential of the node MRY is Low, the refresh output control unit RS is in an inactive state and the output is stopped. Therefore, the node PIX remains holding High.

In the period t13, the potential of the gate bus line GL (i) is kept low, the potential of the data transfer control line DT (i) is kept low, and the potential of the refresh output control line RC (i) is low. As a result, the transistor N4 is turned off, so that the refresh output control unit RS is in a state of performing the second operation, and the node PIX holds High.

In the period t14, the potential of the gate bus line GL (i) is kept low, the potential of the data transfer control line DT (i) is high, and the potential of the refresh output control unit RS is kept low. As a result, the transistor N2 is turned on, so that the data transfer unit TS is in a transfer operation state. At this time, charge movement occurs between the capacitor Ca and the capacitor Cb, and the potentials of both the node PIX and the node MRY become High. The potential of the node PIX decreases by a slight voltage ΔVy due to the transfer of positive charge from the capacitor Ca to the capacitor Cb through the transistor N2, but is within the High potential range.

This period t14 is a period in which the refreshed binary data is held by both the first data holding unit DS1 and the second data holding unit DS2 connected to each other via the data transfer unit TS, and is set to be long. Is possible.

Through the above operation, the potential of the node PIX is High in the periods t1i to t5 and the periods t10 to t14, and is Low in the periods t6 to t9. The potential of the node MRY is High in the periods t1i to t7 and t14. , And becomes Low during the period t8 to the period t13.

Thereafter, when the refresh period T2 is continued, the operation from the period t3 to the period t14 is repeated. When writing new data, the refresh period T2 ends and the all-refresh operation mode is released.

The above is the description of FIG.

Note that a command for all refresh operations may be generated not by an external signal but by a clock generated internally by an oscillator or the like. By doing so, there is an advantage that it is not necessary for the external system to input a refresh command at regular intervals, and a flexible system can be constructed. In a dynamic memory circuit using the memory circuit MR, it is not necessary to perform all refresh operations by scanning each gate bus line GL (i), and can be performed collectively on the entire array. In the dynamic memory circuit, it is possible to reduce peripheral circuits necessary for refreshing while destructively reading the potential of the source bus line SL (j).

Next, a description will be given of FIG.

In FIG. 18, Low as the second potential level is written in the memory circuit MR in the writing period T1i. The gate bus in each period is the same except that the potential of the source bus line SL (j) is Low in the writing period T1i. The potential changes of the line GL (i), the data transfer control line DT (i), and the refresh output control line RC (i) are the same as those in FIG.

Accordingly, the potential of the node PIX is Low in the periods t1i to t3 and the periods t12 to t14, and is High in the periods t4 to t11, and the potential of the node MRY is Low in the periods t1i to t7 and the period t14. It becomes High from t8 to period t13.

Here, the liquid crystal capacitance Clc in FIG. 15 is a capacitance in which a liquid crystal layer is disposed between the node PIX and the common electrode COM. That is, the node PIX is connected to the pixel electrode. At this time, the capacitor Ca also functions as a pixel holding capacitor. The transistor N1 constituting the switch circuit SW also functions as a pixel selection element. The common electrode (counter electrode) COM is provided on the counter substrate facing the matrix substrate on which the circuits constituting the memory circuit MR of FIG. 15 are formed. However, the common electrode COM may be on the same substrate as the matrix substrate.

In the multi-grayscale display mode, in the memory circuit MR, a state in which the data signal having the number of potential levels higher than the binary level is supplied to the pixel so that the refresh operation control unit RS does not perform the first operation to be in the active state. The display can be done with. In the multi-gradation display mode, only the capacitor Ca may function as a storage capacitor by fixing the potential of the data transfer control line DT (i) to Low, or the potential of the data transfer control line DT (i) is set to High. The capacitor Ca and the capacitor Cb may be combined to function as a storage capacitor.

Further, the potential of the refresh output control line RC (i) is fixed to Low and the transistor N4 is held in the OFF state, or the potential of the data transfer control line DT (i) is set to be in the OFF state. By setting it to a high value, the potential of the data transfer control line DT (i) can be prevented from affecting the display gradation of the liquid crystal capacitor Clc determined by the charge accumulated in the first data holding section DS1. The same display performance as that of a liquid crystal display device having no memory function can be realized.

On the other hand, in the memory operation mode, display according to the potential of the first data holding unit DS1 can be performed. If the polarity of the liquid crystal is not reversed in an AC manner, it will cause burn-in and deterioration of the liquid crystal. Therefore, both when the liquid crystal is on (white display) and when the liquid crystal is off (black display) It is necessary to reverse the polarity while keeping the absolute value of the voltage applied to the liquid crystal the same. Therefore, the potential Vcom of the counter electrode COM is set so that the potential difference between the pixel potential during positive polarity driving and the counter potential Vcom is equal to the potential difference between the pixel potential during negative polarity driving and the counter potential Vcom ( Optimal counter potential).

In FIGS. 17 and 18, the potential of the common electrode COM is driven so as to invert between High and Low every time the transistor N1 is turned on. Here, when the high potential of the common electrode COM is equal to the high potential of the binary level and the low potential of the common electrode COM is equal to the low potential of the binary level, the potential of the common electrode COM is low. If the potential of the node PIX is low, the black display is positive, and if the potential of the node PIX is high, the white display is positive. If the potential of the common electrode COM is high and the potential of the node PIX is low, If the negative white display, and the potential of the node PIX is High, the black display is negative.

Accordingly, every time the potential of the node PIX is refreshed, the liquid crystal is driven so that the direction of the liquid crystal applied voltage is reversed while maintaining the display gradation substantially, and the effective value of the liquid crystal applied voltage is constant positive and negative. The AC driving of the liquid crystal becomes possible. Further, the potential (binary value) of the common electrode COM can be configured to be larger than the minimum value of the data signal potential and smaller than the maximum value of the data signal potential. Further, the potential of the common electrode COM may be set to a constant value.

As described above, according to the present embodiment, the liquid crystal display device 2 can have both functions of the multi-color gradation display mode and the monochrome gradation display (halftone display) mode. In addition, during memory operation, by displaying an image with little time change such as a still image, a circuit such as an amplifier for displaying a multi-tone image in the video signal generation circuit and a data supply operation can be stopped. Low power consumption can be realized. Further, since the potential (pixel potential) can be refreshed in the pixel during the memory operation, it is not necessary to rewrite the pixel data while charging and discharging the source bus line SL again, so that power consumption can be reduced. . In addition, since the data polarity can be inverted within the pixel, it is not necessary to rewrite the data while charging / discharging the inverted data in the source bus line SL, so that power consumption can be reduced.

Here, in the memory type liquid crystal display device, as shown in FIG. 8, the pixel charge amount (pixel potential) of the in-memory data MD held in the memory circuit gradually decreases due to natural discharge (leakage). The transmittance of the liquid crystal display panel 10b is lowered. The transmittance decreased in the N frame returns to the original transmittance when the pixel charge amount is increased (charged) by the writing operation in the next N + 1 frame. By repeating such a decrease and increase in transmittance, there is a problem that the luminance on the display screen changes periodically and flicker is visually recognized. This problem is the same in the present liquid crystal display device 2 that performs the refresh operation, and is particularly noticeable when the cycle of the refresh operation is long.

Therefore, the liquid crystal display device 2 according to the present embodiment has a configuration that compensates for the decrease in transmittance due to the discharge by increasing the backlight luminance, as in the liquid crystal display device 1 according to the first embodiment. is doing.

That is, since the display luminance of the liquid crystal display panel 10b changes according to the pixel charge amount and the backlight luminance, as shown in FIG. 9, the display luminance decrease due to the decrease in the pixel charge amount is reduced to the backlight luminance. The display brightness of the liquid crystal display panel 10b is kept constant by compensating for the increase in display brightness caused by the increase in the display brightness. Thereby, flicker can be suppressed. In addition, since it is not necessary to increase the frame frequency, an increase in power consumption can be prevented. A specific configuration will be described below.

The display control circuit 20 includes a PWM signal generation unit 22 as shown in FIG.

The PWM signal generation unit 22 generates a PWM signal for displaying the target luminance based on the amount of change (decrease amount) in the luminance of the liquid crystal display panel 10b due to natural discharge. Here, since the amount of decrease in the luminance of the liquid crystal display panel 10b can be calculated in advance based on the frame frequency, a desired PWM signal corresponding to the calculated amount of decrease in luminance can be generated. For example, it can be realized by a configuration in which the frame frequency set in the liquid crystal display panel 10b and the pulse width (or duty ratio) of the PWM signal are associated with a table in advance. The PWM signal generation unit 22 supplies the generated PWM signal to the backlight 70 in synchronization with the timing of the frame period.

FIG. 11D shows a change in the PWM signal generated by the PWM signal generation unit 22. As shown in the figure, it can be seen that the pulse width of the PWM signal increases as the pixel charge amount decreases, thereby increasing the luminance of the backlight. By supplying such a PWM signal to the backlight 70, it is possible to compensate and equalize the decrease in display luminance (see FIG. 8) of the liquid crystal display panel 10b (see FIG. 11 (a)).

Note that the PWM signal generation unit 22 of the present liquid crystal display device 2 may be configured to calculate the amount of decrease in luminance of the liquid crystal display panel 10b based on the period of the refresh operation. Thereby, a desired PWM signal can be generated according to the calculated amount of decrease in luminance. For example, it can be realized by a configuration in which the refresh operation cycle set in the liquid crystal display panel 10b and the pulse width (or duty ratio) of the PWM signal are associated with a table in advance. The PWM signal generation unit 22 supplies the generated PWM signal to the backlight 70 in synchronization with the timing of the refresh operation cycle.

Note that the charge amount detection unit 10a (see FIG. 13) shown in the first modification may be added to the liquid crystal display device 2.

In the liquid crystal display device according to the embodiment of the present invention, the luminance of the backlight can be increased by widening the pulse width of the drive signal for driving the backlight. Thereby, backlight brightness can be adjusted with a simple configuration.

In the liquid crystal display device according to the embodiment of the present invention, the pulse width of the drive signal may be set based on the frame frequency.

In the liquid crystal display device according to the embodiment of the present invention, the drive signal is preferably a PWM signal.

In the liquid crystal display device according to the embodiment of the present invention,
A charge amount detection unit for detecting the amount of charge held in the pixel;
The pulse width of the drive signal may be determined based on the charge amount detected by the charge amount detection unit.

According to the above configuration, it is possible to generate a drive signal in accordance with the amount of charge detected by the charge amount detection unit, so that it is possible to calculate a more accurate correction value (amount of increase in backlight luminance). Therefore, display flicker in the liquid crystal display panel can be reliably suppressed.

In the above configuration, since the backlight luminance can be adjusted based on the amount of charge of the pixel, the frame frequency can be set regardless of the backlight luminance. For example, the frame frequency may be set lower than in the past, or may be changed without being a constant value. Thereby, power consumption can be further reduced.

In the liquid crystal display device according to the embodiment of the present invention, the drive signal is a PWM signal, and the PWM signal has a pulse width that increases as the amount of charge held in the pixel decreases. It can also be.

In the liquid crystal display device according to the embodiment of the present invention, each pixel is provided with a memory circuit that holds image data, and an image is displayed based on the image data held in the memory circuit. You can also

The above configuration can be applied to a memory type liquid crystal display device.

The liquid crystal display device according to the embodiment of the present invention may be configured to perform a refresh operation during a data holding period after writing image data.

The liquid crystal display device according to the embodiment of the present invention may be configured to perform a refresh operation while inverting the polarity of the image data held in the memory circuit.

In the liquid crystal display device according to the embodiment of the present invention, the normal operation mode in which display is performed based on the image data supplied through the data signal line, and the memory operation in which display is performed based on the image data held in the memory circuit. It is also possible to adopt a configuration including a mode.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

The liquid crystal display device of the present invention can be suitably used for a liquid crystal display device provided with a memory circuit.

DESCRIPTION OF SYMBOLS 1, 1a, 2 Liquid crystal display device 10, 10b Display panel 10a Charge amount detection part 20 Display control circuit 21 Memory drive control part 22 PWM signal generation part 30 Source driver (data signal line drive circuit)
40 Gate driver (scanning signal line drive circuit)
50 Display Unit 60 Memory Driver 70 Backlight 80 Gate Driver / CS Driver 90 Control Signal Buffer Circuit 100 Drive Signal Generation Circuit / Video Signal Generation Circuit 110 Demultiplexer 120 Display Unit GL Gate Bus Line (Scanning Signal Line)
SL source bus line (data signal line)
CSL CS line (holding capacity wiring)
MR memory circuit

Claims (11)

1. A liquid crystal display panel for displaying an image, and a backlight for irradiating the liquid crystal display panel with light;
   A liquid crystal display device characterized by increasing the luminance of the backlight so as to compensate for a decrease in display luminance in the liquid crystal display panel due to discharge of charges held in pixels.
2. 2. The liquid crystal display device according to claim 1, wherein the luminance of the backlight is increased by widening a pulse width of a drive signal for driving the backlight.
3. The liquid crystal display device according to claim 2, wherein the pulse width of the drive signal is set based on a frame frequency.
4. 3. The liquid crystal display device according to claim 2, wherein the drive signal is a PWM signal.
5. A charge amount detection unit for detecting the amount of charge held in the pixel;
   The liquid crystal display device according to claim 2, wherein the pulse width of the drive signal is determined based on the charge amount detected by the charge amount detection unit.
6. The drive signal is a PWM signal,
   6. The liquid crystal display device according to claim 2, wherein the PWM signal has a pulse width that increases with a decrease in the amount of charge held in the pixel.
7. 2. The liquid crystal display device according to claim 1, wherein each pixel is provided with a memory circuit for holding image data, and an image is displayed based on the image data held in the memory circuit.
8. The liquid crystal display device according to claim 7, wherein a refresh operation is performed in a data holding period after image data is written.
9. The liquid crystal display device according to claim 8, wherein a refresh operation is performed while inverting the polarity of the image data held in the memory circuit.
10. 8. A normal operation mode in which display is performed based on image data supplied through a data signal line, and a memory operation mode in which display is performed based on image data held in the memory circuit. The liquid crystal display device described.
11. A method for driving a liquid crystal display device comprising a liquid crystal display panel for displaying an image and a backlight for irradiating the liquid crystal display panel with light,
    A driving method of a liquid crystal display device, wherein the luminance of the backlight is increased so as to compensate for a decrease in display luminance in the liquid crystal display panel due to discharge of charges held in pixels.

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