JPH0450997A - Liquid crystal display control circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for on/off control of a liquid crystal driving voltage (VLCD) and to reduce the electric power consumption by selecting the prescribed signal generated in a control signal generating circuit in an ordinary display state and selecting and outputting the output signal of an oscillation circuit of a low frequency in a standby state. CONSTITUTION:The signal suitable for the LCD driver generated in the control signal generating circuit 103 is selected and outputted to the shift lock LP of AC signals WF and Y drivers in the ordinary display state. On the other hand, the control signal generating circuit 103 is put into a static state and further the clock of the low frequency generated in the oscillation circuit 107 is selected and outputted as the shift lock LP of the AC signal WF and Y driver when the standby state is started by the input of the standby control. The need for the on/off control of the VLCD in the standby state is eliminated by supplying the min. required signal for not directly DC driving the LCD even in the standby state in such a manner. Further, the electric power consumption is reduced by putting the internal control signal generating circuit 103 into the static state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display control circuit capable of controlling the standby state of a liquid crystal display device (hereinafter referred to as LCD).

[Prior Art] In a system using an LCD, - when the display is not needed, the display is turned off and placed in a standby state, and when the display is needed again, the standby state is canceled and the original normal state is restored. A function to return to display may be required. This is especially important for portable devices such as handheld terminals and laptop computers that require power savings. Conventionally,
As a liquid crystal display circuit with this standby mode, L
There was one that used the inhibit function of a segment driver (hereinafter referred to as an "X driver") and a common driver (hereinafter referred to as a "Y driver") in a CD. Figure 2: 640 dots x 200
A block diagram of a dot matrix LCD is shown. 201 to 206 are X drivers, and 207 and 208 are Y drivers, both of which have inhibit input terminals.The inhibit function is a function that forcibly turns the driver output into a non-lighting state when INH="L" level. This can be controlled by directly controlling the INH terminal using the standby mode control signal 5TNBY, as shown in Figure 4, or by controlling the INH terminal with the 5TNBY signal, as shown in Figure 5. In addition to the internal blocks (data generator, timing generation circuit,
A method has been used in which the control signal generation circuit (control signal generation circuit) is placed in a static state.

[Problems to be Solved by the Invention] In the conventional example shown in FIG. 4, the LCD display can certainly be turned off, but since other control signals and data are being output, the driver inside the LCD is also operating. in a state.

That is, it is hardly possible to reduce the power consumed within the liquid crystal display control circuit and the LCD. On the other hand, in the standby state of the conventional example in Section 5, the data generator, timing generation circuit, and control signal generation circuit are all in a stationary state, so the power consumption in the liquid crystal display circuit is increased (reduced). Furthermore, since all data output and control signals input to the LCD are stopped, the power consumed by the driver inside the LCD can be almost eliminated.However,
In this case, the alternating current signal WF stops, so if the liquid crystal drive voltage (LcD) remains applied, the liquid crystal will be driven with direct current, which will significantly reduce the reliability of the liquid crystal. The operation when the input signal to the LCD stops will be briefly explained using FIG. Regarding the X driver shown in FIG. 2, even if the data DO to D3 and the Y driver shift clock/X driver latch pulse LP stop, the previous state (on/off data) is retained. ,
When the alternating current signal WF stops, it turns on/off on either the positive side or the negative side6.Originally, as shown in the X1 waveform in Figure 3, the WF
="L" level turns on/off on the negative side, WF="
When it is at H" level, it must be turned on/off on the positive side and this process is repeated. The same goes for the Y driver. For example, looking at the waveform of Y2, when WF is normally at "L" level,
The positive side is the selection level, the negative side is the non-selection level, and WF=
At "H" level, the opposite is true. However, WF °“H
- or if it stops at the "L" level, it will drive only one polarity side.Furthermore, in the case of a Y driver, normally the first line (Yl) as shown in Figure 3.
(However, if the signal stops in the middle of this process, the line that was selected at that time will remain selected. For example, Y3 will be selected.) If it stops, only the third line will be on all the time, and it will remain lit with high contrast regardless of the data of the X driver. Therefore, as in the conventional example shown in Figure 5, the signal input to the LCD will be When going into standby mode, which stops everything, it is necessary to turn off the VLCD.The same goes for returning to normal display from standby mode, be sure to turn on the LCD after canceling standby mode. In order to control this V LCD on/off, a switch to turn V Lea on/off, a circuit to control the standby on/off timing and LCD on/off timing are required. becomes.

The present invention solves these problems. (2). The purpose of the present invention is to realize a standby mode that does not require on/off control and also enables power saving.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the liquid crystal display control circuit of the present invention is characterized by having the following configuration.

1) A control signal generation circuit that generates control signals suitable for the driver IC based on the basic clock.

2) AC conversion signal, Y driver shift clock, and Y driver scanning start pulse output.

3) Standby control input to switch between normal display state and standby state.

4) Oscillator circuit with a lower frequency than the basic clock.

5) As the alternating current signal and the shift clock of the Y driver, a predetermined signal generated in the control signal generation circuit is selected in the normal display state, and in the standby state, the oscillation is performed without passing through the control signal generation circuit. Means for selecting and outputting the output signal of a circuit or a signal obtained by frequency-dividing the output of the oscillation circuit.

6) Means for controlling the control signal generation circuit to be in a static state in the standby state.

[Function] In the normal display state, a signal generated by the control signal generation circuit and suitable for the LCD driver is selected and output as the AC signal and the shift clock of the Y driver. On the other hand, when the standby state is entered by the standby control input, the control signal generation circuit first enters the standby state. Furthermore, the AC signal and Y
A low frequency clock generated by an oscillation circuit is selected and output as the shift clock of the driver. In this way, even in the standby state, the minimum necessary signal for not driving the LCD with direct current is supplied to the LCD, thereby eliminating the need for on/off control of the V LCD in the standby state. Furthermore, by placing the internal control signal generation circuit in a quiescent state, power consumption is also reduced.

[Example] FIG. 1 shows an example of the present invention. The operation will be explained below.

CK is a basic clock input, and the timing generation circuit 102 generates basic timing based on this clock. Furthermore, the control signal generation circuit 103.

Signals required for LCD control YD (Y driver scanning start pulse), WF (alternating current signal), LP
(X driver latch pulse and Y driver shift clock), X5CL (X driver shift clock), etc. are generated. The selector 105 is a selector that outputs the 6 inputs to Y when the select human power S is at the °゛H'' level, and outputs the B input to Y when it is at the ``L'' level. Therefore, during normal operation, that is, 5TNBY='' When the level is "H", a signal 111 is output to WF and a signal 112 is output to LP. Also, a signal 110 is output to YD via an AND gate 109. 107 is a low frequency oscillation circuit.
04 is a frequency dividing circuit that further divides the frequency of the clock generated at 107. Here, fosc=32KH for 107
z CR oscillation circuit is used, and the frequency dividing circuit 104
The frequency is divided by 512 and a 62.5 Hz clock is output as the signal 113. By setting 5TNBY="L" level, it enters standby mode, but when 5TNBY="L"
level, so the output of the AND gate 106 is “
The L level is fixed, and the timing generation circuit 102, control signal generation circuit 103, and data generator 101 are in a static state. Therefore, Do-D3 and X5CL also come to rest,
YD is fixed at "L" level by AND gate 109. 5TNBY="L" causes the selector 105 to select the B input, so the signal 1 is sent to WF and LP.
13 is output. Since these signals do not pass through the timing generation circuit 102 and control signal generation circuit 103,
Although it is not a signal that can display the LCD normally, it does not need to be displayed in standby mode, and the LP to deselect all Y drivers and the WF necessary for AC conversion are output in some form. It is enough if
As explained in Fig. 3, the Y drivers are sequentially shifted by LP using YD as the scanning start pulse, so in order to deselect all Y drivers, YD=”
It is sufficient to send 200 or more LPs with the power set to "L" level. (The LP frequency may be slower than normal operation.) Regarding power consumption, the basic clock usually requires 5 to 1 LP.
A clock of 0MHz is used. As mentioned above, in standby mode, CK is fixed at the "L" level by the AND gate 106, so the timing generation circuit 102, control signal generation circuit 103, and data generator 101 are stationary, and their respective power consumption is approximately O. be. The operating circuits are the oscillation circuit 107, the frequency dividing circuit 104, and the selector 1.
05 only. As mentioned above, these operate at a low frequency of about 32KH2, and their power consumption is almost negligible. (The current consumption is several uA"J, and regarding the power consumption inside the LCD, the signals given to the driver are WF and LP.
Furthermore, since these frequencies are extremely close to 62.5 Hz, power consumption can be reduced to a negligible level.

Next, a circuit diagram of the oscillation circuit 107 is shown in FIG.

As can be seen from FIG. 6, the circuit can be easily constructed using the CR oscillation circuit. 601 is 5TNBY=”
This is a NOR gate with 5 TNBY inputs so that it oscillates only at the "L" level.

R is an oscillation resistor, and here, an IMΩ resistor is used. C is also an oscillation capacitor, here it is 14PF.
capacitor is used. Although the accuracy of the CR oscillation circuit is lower than that of a crystal oscillation circuit, etc., in the standby mode of the present invention, a highly accurate frequency is not required as described above, so the CR oscillation circuit functions satisfactorily. Furthermore, if it is a CR oscillation circuit, the OR can be built into the IC circuit, and the present invention can be implemented on a monolithic IC.

In this embodiment, in order to increase the effect of power saving, the frequency dividing circuit 1
04 was used, but this was removed to simplify the circuit.
It is also possible to directly use the output of the oscillation circuit as the signal 113.

[Effects of the Invention] As described above, according to the present invention, by controlling only the 5TNEY signal without controlling the V LCD on/off,
It is possible to easily switch between the standby state and the normal display state. Moreover, the power consumption not only in the liquid crystal display control circuit of the present invention but also in the LCD can be greatly reduced. Further, according to the present invention, even if a driver without an inhibit function is used, the display can be deselected in the standby state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a block diagram of a 640x200 dot matrix LCD. FIG. 3 is an operation timing diagram of the LCD shown in FIG. 2. 4 and 5 are block diagrams of conventional liquid crystal display control circuits. FIG. 6 is a circuit diagram of the oscillation circuit 107 shown in FIG. 1. Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (1 person) Figure 1 Figure 2 Figure 4 Figure 5 F Figure 3 Figure 6

Claims (1)

[Claims] In a liquid crystal display control circuit that outputs a control signal suitable for a driver IC in a liquid crystal display device based on a basic clock, the circuit comprises: a) generating a control signal suitable for a driver IC based on a basic clock; Control signal generation circuit, b) AC signal, Y driver shift clock and Y driver scanning start pulse output, c) Standby control input for switching between normal display state and standby state, d) Oscillation at a lower frequency than the basic clock circuit, e) selecting a predetermined signal generated by the control signal generation circuit in the normal display state as the alternating current signal and the shift clock of the Y driver; and in the standby state, selecting a predetermined signal generated by the control signal generation circuit; means for selecting and outputting an output signal of the oscillation circuit or a signal obtained by frequency-dividing the output of the oscillation circuit; and f) means for controlling the control signal generation circuit to be in a static state in the standby state. A liquid crystal display control circuit characterized by: