JPH1152916A - Driving power source circuit for liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize low power consumption while maintaining the current driving ability in a driving circuit for liquid crystal display device. SOLUTION: Selective active control is applied to amplifiers, OP1 to OP5, which output plural driving voltage levels for driving a liquid crystal display device. In this case, at the rise time (shift from the non-active state to the active state) of an amplifier, control signals, OFF1 and OFF2, are generated from a control circuit 200 so that the amplifier rises with time necessary for amplifier setup and thereby selective active control of each amplifier of OP1 to OP5 can be made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit for a liquid crystal display device, and more particularly to an improvement in a power supply circuit for a liquid crystal display device for generating a drive voltage for the liquid crystal display device.

[0002]

2. Description of the Related Art A liquid crystal display panel has a structure in which two panels each having a large number of wiring electrodes are arranged so that the respective electrodes cross each other and face each other, and a liquid crystal is sandwiched between the electrodes. This is displayed by applying a predetermined voltage to each electrode of the two panels and applying a voltage to the liquid crystal.

FIG. 5 is a block diagram including the panel and a display drive system. Of the wiring electrodes of the liquid crystal display panel 24, the electrodes that are extended in the horizontal direction are called common (COM) electrodes or scanning electrodes, and the electrodes that are extended in the vertical direction are called segment (SEG) electrodes or data electrodes. The common electrode is periodically scanned by the driver 23 and driven by two values, a selected value and a non-selected value. The segment electrode is driven by a display signal by the driver 22 and outputs a binary value of a selected value and a non-selected value depending on whether a point intersecting with the common electrode line is displayed or hidden.

The output voltages V1 to V5 of the power supply circuit 20 are selected by a level selection circuit 21 so that each driver 22,
23 is supplied as a drive voltage.

FIG. 6 shows actual waveforms of the common and segment drivers 23 and 22. If the voltage difference between the common and the segment is greater than a certain value, the liquid crystal at the position where the common and the segment intersect will be displayed,
If it is less than a certain value, it is not displayed.

In order to prevent the deterioration of the liquid crystal of the panel, it is necessary to apply the above voltage in an AC manner. Therefore, in general, the drive level has a selected value and a non-selected value each having two values, and these two values are alternately selected in a cycle of a polarity switching signal (or called a frame signal). In general, the common signal and the segment signal are obtained by dividing the source oscillation (clock) by several, while the frame signal is obtained by dividing the common frequency. It will be.

In consideration of the above-described frame switching, the driving voltage of the liquid crystal is 2 (common, segment) × 2 (selection, non-selection) × 2
(Frame) = 8 kinds of levels are required at the minimum, but usually the selection level is G
ND, VLC or V1 (highest voltage of liquid crystal drive voltage)
Therefore, the driving level of the liquid crystal panel is generally set to six. These levels are generated by resistance division. If the level is used as it is as a panel driving power source, the panel driving capability is determined by the divided resistance value. .
However, in this case, since a large amount of current flows between the power supplies, there is a problem that current consumption increases.

Therefore, in the prior art, as shown in FIG. 7, a resistance dividing circuit of high resistances R1 to R5 is formed as the power supply circuit 20 of FIG. A power supply circuit is used that performs impedance conversion by the follower amplifiers OP1 to OP5 and suppresses unnecessary current flowing through the resistor without lowering the current driving capability of the liquid crystal.

However, even in this conventional example, the bias current necessary for the operation of the amplifier always flows, and the current other than the driving of the panel is always consumed, so that it is neglected for further low current consumption applications such as portable electronic devices. It is a situation that can not be done.

Therefore, as another conventional example, a function of stopping the bias current and simultaneously turning off the output (hereinafter referred to as OFF)
Or call it a standby function).
There is a method of reducing the current by turning off an unused amplifier, and an example thereof is disclosed in Japanese Patent Application Laid-Open No. 4-143793. FIG. 8 shows the overall circuit configuration, and FIG. 9 shows the timing of each level output in FIG.

The unnecessary impedance conversion amplifiers OP6 to OP9 are selectively turned off in synchronization with the frame signal FR.
It is supposed to. In addition, in FIG.
Reference numerals 8 and 30 denote inverters, 29, 33 and 34 denote transistors, 31 and 32 denote gate circuits, 35 denotes a bias voltage generating circuit, and SW7 to SW9 denote transistor switches. Please refer to.

FIG. 10 shows a configuration example of each amplifier in a drive power supply using these amplifiers. In these amplifiers used in a power supply circuit having a high resistance dividing circuit for reducing current and an amplifier, the idling currents of the differential stage and the output stage are represented by a bias voltage (Nbias in FIG. 10A and FIG. 10B). Pbias).

In FIG. 10, 36, 37, 41, 4
2, 45 to 49 are P-channel transistors;
40 to 43, 44, 50 to 53 are N-channel transistors, and C3 and C4 are phase compensation capacitors.

However, in this case, the amplifier is switched from the OFF state to the normal state (with respect to the phase compensation capacitors C3 and C4,
Until the bias corresponds to the bias during normal operation)
As shown in the general amplifier configuration example in FIG.
It takes time in proportion to C5 / $ 0 (C5 is the phase compensation capacitance value, $ 0 is the bias current). Therefore, at the timing shown in FIG. 9, even if the power consumption is low, the output value is not maintained until the amplifier operates normally (until the phase compensation capacitor is charged with the bias current in the amplifier to the predetermined operation bias level). It is not realistic because it becomes stable. In the worst case, unnecessary driving may consume current unnecessarily.

[0015]

As shown in the example of FIG. 7, in the power supply circuit having the resistance division and the amplifier structure, the useless current consumption increases. The reason is that a constant current source supplies a current to an unused amplifier.

Further, as shown in FIG. 8, when an unnecessary amplifier is turned off, the liquid crystal cannot be sufficiently driven when the operation of the amplifier is switched. The reason is that the operating speed of the amplifier can be determined by the ratio of the capacity of the constant current source to the capacity of the phase compensation. Therefore, a predetermined time is required to restart the operation of the amplifier which has been stopped. In addition, the liquid crystal panel is a capacitor and requires the most current capability at the time of output switching.

An object of the present invention is to turn off an amplifier except for a section required for normal output of an amplifier while maintaining an operation waveform of a combination structure of a conventional amplifier and a dividing resistor. An object of the present invention is to provide a driving power supply circuit for a liquid crystal display device which consumes less power.

[0018]

According to the present invention, a voltage generating means for generating a plurality of voltage levels required for driving a liquid crystal display, and a plurality of voltage followers for performing impedance conversion using each of these voltage levels as an input. Means for controlling the activation of the voltage follower means, the control means comprising: Is generated, thereby obtaining a driving power supply circuit for a liquid crystal display device.

The control means turns off the activating signal in synchronization with the one-way level transition timing of the frame pulse for the display drive signal of the liquid crystal display device, and sets the other level of the frame pulse in the other direction. The activation signal is turned on at a timing earlier than the transition timing by the margin period.

Further, the control means includes a delay circuit for delaying the frame pulse by at least one clock pulse of the liquid crystal display, a logic circuit for synthesizing an output of the delay circuit and the frame pulse to generate the activation signal. And a logic circuit for generating.

The operation of the present invention will be described. Buffer amplifier that outputs unnecessary level (voltage follower means)
Is O except for settling time for amplifier restart
Since unnecessary bias current does not flow due to the FF operation, current consumption is smaller than when all levels of amplifiers are operated. Further, since the unnecessary amplifier is turned on before the next polarity switching, the amplifier is in a steady state at the time of the next output switching, so that the liquid crystal driving capability at the time of the switching is sufficient.

[0022]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. Referring to FIG. 1, an amplifier O having a function of stopping a bias current and of turning off an output (or a standby function) is provided.
P1 to OP5 are provided, each of which receives a plurality of divided voltage levels by the resistance dividing circuit of the high resistances R1 to R5 and activates each of these input voltage levels when the liquid crystal display device is activated (when not in standby). It is derived to the driver as a voltage. These amplifiers OP1 to OP5 have a voltage follower function for impedance conversion.

The level selection circuit 100 includes amplifiers OP1 to OP
The multiplexer is configured to select the output of P5 in synchronization with the frame signal FR. The control circuit 20
0 is the selection signal of the selection circuit 100 and the amplifiers OP1 to OP
The P5 ON / OFF control signal is generated as two frame signals having different phases, and the unselected level amplifier is turned off using the signal, and the turned off amplifier is controlled so as to be turned off before being selected. Control circuit.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings. The control circuit 200 includes a delay circuit 201 and a combinational logic circuit (logic gates 202 and 2).
03), and generates a delayed frame signal FR 'having a delayed phase from the frame signal FR and the clock CLK, and the amplifier control signals OFF1 and OFF2.

The logic gate 202 is a NOR gate, and receives the frame signal FR and the delayed frame signal FR 'from the delay circuit 201 as inputs to generate an amplifier control signal OFF1. The logic gate 203 is an AND gate, and outputs the frame signal FR and the delayed frame signal F
R ′ as an input to generate an amplifier control signal OFF2. The amplifiers OP2 and OP3 are controlled by the amplifier control signal OFF1.
However, the amplifiers OP4 and OP5 are respectively activated and controlled by the amplifier control signal OFF2.

The level selection circuit 100 includes switches SW1 to SW formed by transfer gate circuits using transistors.
6, inverters 4 to 9 and pull-down transistor 1
0 and 11 are controlled in synchronization with the delayed frame signal FR '.

VLCD and VEE in FIG. 1 are power supplies, which are the highest potential and the lowest potential of the liquid crystal driving voltage. This VLC
D and VEE are divided into five by resistors R1 to R5 to generate a level for driving the liquid crystal. These R1 to R5 are several hundred kΩ ~
The resistance is as high as several MΩ, and current consumption flowing through the resistance is reduced as much as possible.

On the other hand, the amplifiers OP1 to OP5 convert the level of the high output impedance obtained by the resistance division into an impedance so that the liquid crystal current can be sufficiently driven. Each amplifier has an OFF function or a standby function of stopping the internal bias current by an external input and turning off the output.

Each output of the amplifier enters a level selection circuit 100 composed of SW1 to SW6 and inverters 4 to 9. In this level selection circuit 100, each frame is output from six levels including GND (earth level). A common selection level, which is a level required for each common output,
Four levels are selected: a common non-selection level, a segment selection level which is a level for segment output, and a segment non-selection level.

On the other hand, the ON / OFF switching of the amplifier and the switching of the level selection circuit 100 are performed by the control circuit 200.
Is controlled by a signal from The control circuit 200 is a delay circuit 2
1 and a combinational logic circuit. FIG. 1 shows a case where a synchronous delay circuit is used. FIG. 2 is a timing chart showing an example of output when a one-stage shift register is used as the synchronous delay circuit.

The logic frame signal FR and the clock CLK are input, and the delayed frame signal FR 'is output as a switching signal of the level selection circuit 100. The level of the frame signal in the power supply circuit is set to AC.
Since it is a signal to be applied in a specific manner, there is no problem if FR 'is used as a frame of the selection circuit if the period does not change.

At the same time, the ON / OF of the amplifier is determined by the combination of the two frame signals FR and FR 'having different phases.
The two-phase clocks OFF1 and OFF2 for F are generated. When the one-stage shift register 201 is used, FR 'is shifted by one clock from FR. Α of two signals
By taking ND and NOR, 2 shown in FIG.
Phase clocks OFF1 and OFF2 are obtained.

At this time, OFF1 falls one clock cycle before FR 'and rises simultaneously with the fall of FR'. On the other hand, OFF2 rises at the same time as the rise of FR ', and falls one clock cycle before FR' falls.
Therefore, if the OFF1 signal is input to each amplifier as the ON / OFF signal of OP2 and OP3, and the OFF2 signal is input to each amplifier as the ON / OFF signal of OP4 and OP5, the operation of each amplifier can be expressed as shown in FIG. Become.

In this case, OP2 and OP3 are activated when FR 'is high to select the level, but OFF1.
The signal goes low one clock before FR 'goes high,
The amplifiers OP2 and OP3 are turned on. Immediately after being turned on, output cannot be performed until a predetermined bias is charged in the phase compensation capacitor (see FIG. 11). Generally, several p as the phase compensation capacitance
F, since the bias current is several μA, τ = pF /
During the time period from μA to several μsec, the operation of the amplifier is not stabilized and cannot be sufficiently driven.

Therefore, in order to sufficiently drive the liquid crystal, it is necessary to select an output several tens of seconds after the amplifiers OP2 and O # 3 are turned on. The LCD clock is
Since it is several hundred KHz to several tens KHz, the delay for one clock is 10 μsec to several hundred μsec, and the time required for the amplifier to be turned off or to be restarted after the standby operation (inactive state) can be secured.

Since the rise of the OFF1 signal is the same as the fall of FR ', the outputs of OP2 and OP3 are not selected, and at the same time, the outputs of OP2 and OP3 are turned off.
Alternatively, the operation is performed in a standby state (inactive state), and a state in which useless current does not flow is established.

On the other hand, OP4, ΔP5 by the OFF2 signal
1 and 2, the same applies to the OFF timing and the ON timing.

As can be seen from FIG. 2B, the amplifiers other than those whose outputs are selected in the ON (active) state are off except for some sections, so that no useless current flows. The partial section is one clock cycle before the output switching, and this section is a settling time for the next operating amplifier to sufficiently drive the liquid crystal at the time of the output switching. It is impossible to switch at the same time as in the conventional example (the liquid crystal panel is a capacitive load, and the level switching requires a negative current).

Further, the actual liquid crystal drive circuit divides the source oscillation by several and further divides by the number of commons or tens of commons by several tens Hz (the period is on the order of several msec). ) Is used as the frame period, and the ratio of the current consumption in this section is μsec / m
sec is about 1/1000. As described above, it is possible to obtain a liquid crystal driving power supply circuit that consumes less liquid crystal than before without lowering the current driving capability of the liquid crystal panel.

Next, a second embodiment of the present invention will be described. FIG. 1 shows an example in which a synchronous delay circuit 201 is used. In this case, the number of shift registers is increased to two or three as the delay circuit 201, thereby delaying two clocks of source oscillation and three clocks. It can be set as the settling time before the amplifier is switched, but a delay of one clock or less is impossible in a synchronous system.

If the settling time until the restart of the operation of the amplifier is not sufficiently grasped, there is a possibility that a wasteful current in which all the amplifiers are ON may occur or the amplifier may not operate until the output is switched.

Therefore, the second embodiment uses an asynchronous delay circuit, and FIG. 3 shows the delay circuit. As described above, the operation of the operational amplifier is based on the phase compensation capacitance (C)
/ Bias current I｝. Therefore, the same bias current as the load C1 having the same capacitance value as the phase compensation capacitance equivalent to the operational amplifier used (in this case, the same bias current is obtained by applying the bias voltage used in the amplifier to the transistor). Thus, a buffer having an operation speed equivalent to that of an amplifier is used as a delay circuit.

T12 and T13 are P-channel transistors, and T10 and T11 are N-channel transistors. I1 indicates an inverter. In such a configuration, an operating margin can be created by reducing the bias current or increasing the load capacitance C1.

FIG. 4 is a block diagram showing the whole liquid crystal driving circuit using the configuration of FIG. 1, and the same parts as those of FIG. 5 are denoted by the same reference numerals. The block indicated by 25 is the circuit of FIG.

[0046]

The effect of the present invention is that the power supply circuit has a current driving capability of the liquid crystal which is lower than that of the conventional one while consuming less power than the power supply circuit of the conventional amplifier + division resistance system. The reason is that the level generation is made with high resistance to suppress useless current, and the voltage follower amplifier that receives it is turned off while the level output is not being performed to improve the current consumption and to turn off the voltage follower that was turned off. This is because control is performed to turn on the voltage forward amplifier in consideration of the operation time before the output of the amplifier is reselected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2A is a timing chart of signals of respective parts showing the operation of the circuit of FIG. 1, and FIG. 2B is a diagram showing an operation state of each voltage follower.

FIG. 3 is a diagram illustrating another form (asynchronous system) of the delay circuit in FIG. 1;

FIG. 4 is a block diagram including a liquid crystal panel when the power supply circuit for driving a liquid crystal of the present invention is used.

FIG. 5 is a block diagram including a conventional liquid crystal panel.

FIG. 6 is a diagram showing an example of a common waveform and a segment waveform which are drive waveforms of a liquid crystal.

FIG. 7 is a diagram illustrating an example of a conventional power supply circuit.

FIG. 8 is a diagram showing another example of a conventional power supply circuit.

FIG. 9 is a timing chart of each level output of FIG. 8;

FIG. 10 is a diagram illustrating a configuration example of an amplifier with an OFF function in FIG. 8;

FIG. 11 is a diagram illustrating a configuration example of a general amplifier.

[Explanation of symbols]

 Reference Signs List 22 segment driver 23 common driver 24 liquid crystal display panel 100 level selection circuit 200 control circuit 201 delay circuit 202 NOR gate 203 AND gate R1 to R5 Split resistors OP1 to OP5 Amplifier (voltage follower amplifier)

Claims (3)

[Claims] 1. A voltage generating means for generating a plurality of voltage levels required for driving a liquid crystal display, a plurality of voltage follower means for performing impedance conversion with each of these voltage levels as an input, and a selection of the voltage follower means Control means for performing active activation control, wherein the control means comprises:
A drive power supply circuit for a liquid crystal display device, wherein an activation signal to the voltage follower means is generated with a sufficient period for the output voltage of the voltage follower means to rise. 2. The control unit turns off the activation signal in synchronization with a unidirectional level transition timing of a frame pulse for a display drive signal of the liquid crystal display device, and controls the level of the frame pulse in the other direction. 2. The drive power supply circuit according to claim 1, wherein the activation signal is turned on at a timing earlier than the transition timing by the margin period. 3. The control means includes: a delay circuit for delaying the frame pulse by at least one clock pulse of a liquid crystal display; and a logic circuit for synthesizing an output of the delay circuit and the frame pulse to generate the activation signal. 3. The driving power supply circuit according to claim 2, further comprising a logic circuit that generates the driving power.