KR950010847B1 - Read/write circuit for multiple control register - Google Patents

Abstract

a plurality of control registers operated by corresponding write driving signals and for inputting data to be written through data bus to hold the input data as an output value; a decoder for output the write driving signal for operating the control register by searching the control register which displays a write signal and a plurality of address signals; and a random access memory for outputting data corresponding the address signals on the data bus, if the address signals indicating the control register are inputted to read the content of the control register.

Description

Multiple Control Register Lead / Write Circuits

1 is a block diagram illustrating a plurality of control register read / write circuits according to the related art.

2 is a block diagram illustrating a plurality of control register read / write circuits according to an embodiment of the present invention.

FIG. 3 is a partial waveform diagram of writing operations of a plurality of control register read / write circuits according to an embodiment of the present invention.

4 is a partial waveform diagram of a read operation of a plurality of control register read / write circuits according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: lead decoder 20: light decoder

31: first buffer 3i: i buffer

3j: j buffer 41: first control register

4i: i-th control register 4j: j-th control register

50: RAM 60: Decoder

71: first control register 7k: k-th control register

7n: nth control register

The present invention relates to a plurality of control register read / write circuits. More specifically, when controlling a system with a plurality of control registers, it is necessary to read back the values written in the respective control registers. The present invention relates to a plurality of control register read / write circuits that serve as a status register for all control registers by using a memory device that can read and write without having a buffer for the status register.

Conventionally, in a system controlled by a plurality of control registers, a value register is written in the control register by putting a buffer for the status register, one area for each control register, or allocating a partial area in the system memory to read back the value written in each control register. Read on.

FIG. 1 is a block diagram illustrating a plurality of control register read / write circuits proposed in the related art, in which a status register buffer is provided for each control register.

As shown in FIG. 1, a configuration of a plurality of control register read / write circuits proposed by the prior art includes a chip selector signal YCS *, a data strobe signal DS *, a read signal WT, and an address signal A0. A read decoder 10 for outputting read drive signals rd1 * to rdj * as input to? Am; A write decoder 20 for outputting a write driving signal by inputting the chip select signal YCS *, the data strobe signal DS *, the write signal WT *, and the address signals A0 to Am; J control registers 41 to 4J that operate according to the write drive signals wr1 * to wrj * outputted from the write decoder 20 and input data on a data bus and hold the output values as output values; J buffers 31 to 3j which operate in accordance with the read drive signals rd1 * to rdj * output from the read decoder 10 and output the output values of the corresponding control registers 41 to 4j on the data bus. Is done.

Referring to the operation of the plurality of control register read / write circuit proposed in the prior art configured as described above are as follows.

When power is first applied, control signals are input to the read decoder 10 and the write decoder 20 through a control bus of the central processing unit.

The chip select signal YCS *, the data strobe signal DS *, and the address signals A0 to Am are commonly input to the read decoder 10 and the write decoder 20, and the read signal WT and the write signal WT *) Has a symmetric value to input. That is, when the read signal WT is at the high level H, the write signal WT * is at the low level L, and only the read decoder 10 operates, and the read signal WT is at the low level L. The write signal WT * becomes the high level H so that only the write decoder 20 operates.

Assuming that the CPU writes some contents into the i-th control register 4i, the chip select signal YCS *, the data strobe signal DS *, and the write signal WT * applied to the write decoder 20 are assumed. Is input to the high level (H).

The write decoder 20 operates by the chip select signal YCS *, and the address signals A0 to Am containing data relating to the address of the i-th control register 4i are input to the read decoder 10. The read decoder 10 receives the input address signals A0 to Am to the write decoder 20. The write decoder 20 outputs the write driving signal wri * to the corresponding i-th control register 4i according to the input address signals A0 to Am.

When the write driving signal wri * is applied to the i-th control register 4i and the signal wri * is changed to the high level H, the write drive signal wri * is written through the data bus connected to the input terminal of the i-th control register 4i. Data is entered. Thus, the execution of the write operation is completed.

Assuming that the central processing unit reads the contents written in the i-th control register 4i, the chip select signal YCS *, the data strobe signal DS *, and the read signal WT applied to the read decoder 10 are read. Is input to the high level (H).

According to the chip select signal YCS *, the read decoder 10 operates according to the address signals A0 to Am that have data relating to the addresses of the i th control register 4i and the i th buffer 3i. The read drive signal rdi * is outputted to the i-th buffer 3i.

When the read driving signal rdi * is applied to the i-th buffer 3i and the signal rdi * changes to a high level H, the output terminal of the i-th control register 4i and the input terminal of the i-th buffer 3i are applied. Because of this connection, the i-th buffer 3i outputs the contents written in the i-th control register 4i onto the data bus. Thus, the performance of the read operation is completed.

By the operation as described above, the central processing unit performs a read / write operation of writing new contents or reading the written contents into the control register by a buffer having the same address as the control register.

However, the method of placing a status register buffer in each control register proposed in the related art increases the number of buffers as the number of control registers increases, so that when the capacity of a printed circuit board (PCB) becomes insufficient, the control registers are effectively removed. It is difficult to manage.

In addition, the method of reading / writing the contents of the control register by allocating a partial area in the system memory without setting a status register buffer separately may cause the corresponding address to change every time compiling during system programming. The disadvantage is that debugging is difficult.

Therefore, it is an object of the present invention to solve the disadvantages of the conventional art by using a single read and write memory device to act as a status register for all the control registers to save the printed circuit board and the same as the control register at any time An object of the present invention is to provide a plurality of control register read / write circuits that enable monitoring by access of an address.

The configuration of the present invention to achieve the above object comprises: n control registers which are operated by a corresponding write drive signal and receive data to be written via a data bus and maintain them as output values; A decoder for outputting a write driving signal for operating a control register indicated by the address signal from a write signal and an address signal to perform a write operation; In order to write the same data as the one written in the control register, an address signal indicating a corresponding control register is input, and the data corresponding to the address signal is received and stored through a data bus. When an address signal indicating a control register is input, a RAM for outputting data corresponding to the address signal on a data bus is provided.

When described with reference to the accompanying drawings a preferred embodiment that can be easily implemented of the present invention by the above configuration as follows.

2 is a block diagram of a plurality of control register read / write circuits according to an embodiment of the present invention.

As shown in FIG. 2, a configuration of a plurality of control register read / write circuits according to an embodiment of the present invention includes a chip select signal YCS, a write signal WT, a data strobe signal DS, and an address signal A0. A decoder 60 for inputting? Am to output the write drive signals wr1 to wrm; N control registers 71 to 7n having write drive signals wr1 to wrn outputted from the decoder 60 as clip inputs Clk, and data buses connected to the input and output terminals; The chip select signal YCS, the RAMWrite signal RWR, the RAM output enable signal ROE, and the address signals A0 to Am are input, and the RAM 50 is connected to the data bus.

The operation of the plurality of control register read / write circuits by the above configuration is as follows.

The operation of the plurality of control register read / write circuits according to the embodiment of the present invention is largely a write operation of writing data to an arbitrary control register 7k and reading of data written to an arbitrary control register 7k. The view may be divided into read operations.

3 is a partial waveform diagram of a write operation of a plurality of control register read / write circuits according to an embodiment of the present invention.

First, referring to FIG. 3, the light operation will be described below.

When the power is applied, the chip select signal YCS is changed to the high level H so that the RAM 50 and the decoder 60 are selected. In order to perform a write operation, the decoder 60 receives a write signal WT as shown in FIG. 3 (e) and a data strobe signal DS as shown in FIG. 3 as a high level (H). The ram light signal RRW as shown in (a) and the ram output enable signal ROE as shown in FIG. 3 (b) are applied to the RAM 50.

On the other hand, address signals A0 to Am as shown in FIG. 3 (c) are applied to the decoder 60 and the RAM 50.

When the write signal WT and the data strobe signal DS are applied to the input terminal of the decoder 60 at the high level H, the decoder 60 receives the address signal A0 from the input address signals A0 to Am. The control register 7k indicated by ˜Am) is found, and a light driving lead wrk as shown in FIG. 3 (d) for operating the control register 7k is outputted to the control register 7k.

The write driving signal wrk output from the decoder 60 is applied to the clock input terminal Clk of the k-th control register 7k, and is applied to the clock input terminal Clk as shown in FIG. 3 (d). When Wrk changes to the high level H, the k-th control register 7k receives data to be written through the data bus and maintains it as an output value.

As described above, the same operation is performed on the RAM 50 while data to be written to the k-th control register 7k is written.

First, when the ram light signal RWr as shown in FIG. 3 (a) and the ram output enable signal ROE as shown in FIG. 3 (b) are applied to the ram 50, the ram light signal RWR as the high level H is applied. During the period, the address signals A0 to Am applied as shown in FIG. 3 (c) are input.

The address signals A0 to Am are the same as the address signals A0 to Am applied to the decoder 60, and represent the kth control register 7k. The RAM 50 receives data to be written corresponding to the address signals A0 to Am through the data bus.

Therefore, the RAM 50 stores the contents of each control register 7k in an address area corresponding to each control register 7k.

As described above, in the write operation, contents to be written to the specific control register 7k are written not only to the control register 7k but also to the RAM 50.

4 is a partial waveform diagram of a read operation of a plurality of control register read / write circuits according to an embodiment of the present invention.

Next, referring to FIG. 4, a read operation for reading data written in an arbitrary control register 7k is as follows.

When the power is applied, the chip select signal YCS is changed to the high level H so that the RAM 50 and the decoder 60 are selected. In order to perform a read operation, the write signal WT as shown in FIG. 4 (e) is applied at the low level L to the decoder 60, and the data strobe signal DS as shown in FIG. H) is applied. On the other hand, the RAM 50 is applied to the RAMWrite signal RWR as shown in FIG. 4 (a) and the RAM output enable signal ROE as shown in FIG. 4 (b).

On the other hand, address signals A0 to Am as shown in FIG. 4C are applied to the decoder 60 and the RAM 50. When the write signal WT is applied at the low level L to the input terminal of the decoder 60 and the data strobe signal DS is applied at the high level H, the decoder 60 receives the input address signals A0 to. The control register 7k finds a control register 7k indicated by the address signals A0 to Am and outputs a write drive signal wrk as shown in FIG. 4D for operating the control register 7k. To 7k).

However, since the write driving signal wrk applied to the clock input terminal Clk of the control register 7k is the low level L as shown in the fourth (d), the control register 7k does not operate.

On the other hand, the ram 50 is applied to the RAM light signal RWr at the low level L as shown in FIG. 4 (a) and the RAM output enable signal ROE changing to the high level H as shown in the fourth (b). do.

The read operation of the RAM 50 is performed by the RAM light signal RRW of the low level L and the RAM output enable signal ROE that changes to the high level H. That is, the address signals A0 to Am applied to the RAM 50 are applied to the RAM 50 during the period in which the RAM output address signal ROE is at the high level H.

In the RAM 50, data corresponding to the address signals A0 to Am is output through the data bus in accordance with the input address signals A0 to Am. That is, the data written in the k-th control register 7k is outputted in the RAM 50 during the read operation.

As described above, in the embodiment of the present invention, the RAM 50 operates as a status register for all the control registers 71 to 7n, thereby improving the efficiency of the printed circuit board compared to the buffering method in each conventional control register. It solves the problem of making debugging difficult because the corresponding address is changed when compiling the system program, compared to the method of reading a value written in the control register by allocating some area in the system memory without having a separate buffer for reading. A plurality of control register read / write circuits can be provided.

Claims (2)

N control registers 71-7n which are operated by corresponding write drive signals wr1 to wrn to receive data to be written via the data bus and hold them as output values; In order to perform a write operation, a write drive for operating the control register 7k by finding a control register 7k indicated by the address signals A0 to Am from the write signals WT and the address signals A0 to Am. A decoder 60 for outputting a signal wrk; In order to write the same data as those written in the control registers 71 to 7n, the address signals A0 to Am representing the corresponding control registers 7k are input, and the data written to the control registers 7k is transferred to the data bus. When the address signals A0 to Am indicating the corresponding control registers 7k are input to store and receive the contents of the specific control registers 7k, data corresponding to the address signals A0 to Am is inputted. A plurality of control register read / write circuits comprising a RAM (50) for output on a data bus. 2. The RAM 50 according to claim 1, wherein contents written in the control registers 71 to 7n are simultaneously stored in the RAM 50 to operate as a status register for displaying the contents of the control registers 71 to 7n. Multiple control register lead / write circuits.