JPH08123716A - Memory system - Google Patents

Abstract

PURPOSE: To provide a memory circuit capable of compactly attaining a frame buffer for a high speed graphic display. CONSTITUTION: The memory circuit consists of a storage element 2 capable of optionally reading, writing and storing data and a computing element 1 for computing 1st data from the external and 2nd data in the element 2. The memory circuit is also provided with a register for storing a specified arithmetic function code and a register for storing specified write control data and write control in each operation unit and bit unit is executed based upon output data from the arithmetic function code storing register and the write control data storing register. Since the specification of read modifying/write modifying operation does not depend upon the data width of writing data, the memory circuit including a circuit capable of executing read modifying/write modifying operation by optional data width can be attained.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage element, and more particularly to a storage circuit suitable as a frame buffer for a high-speed graphic display. 2. Description of the Related Art With the improvement of display resolution, graphic display devices have begun to require a large-capacity memory for storing display information, that is, a frame buffer. However, since increasing the capacity of the frame buffer leads to an increase in the number of memory accesses when displaying graphic data, it is necessary to reduce the number of memory accesses in order to speed up the display. As a means for reducing the number of times of memory access, there is a method of executing arithmetic processing inside a graphic display frame buffer. FIG. 2 shows an example of a frame buffer using this method. In FIG. 2, 1 is an arithmetic unit having a 16-bit length, 2 is a memory for storing graphic data, 3 is an arithmetic function specifying register of the arithmetic unit, 4 is a write mask circuit, and D15 to D0 are 16-bit data from the data processing device. , DO15 to DO0 are read data from the memory, FC3 to FC0 are calculation function specifying data for the arithmetic unit, M15 to M0 are write control signals to the memory, A23 to A1 are 23-bit address signals from the data processing device, and WE is data processing. A write control signal from the device, FS is a latch control signal for the arithmetic function designation register, and MS is a latch control signal for the write mask circuit. The reason why the number of memory accesses is reduced in the configuration of FIG. 2 will be described. When writing a figure on a bitmap type graphic display, the figure is expressed by a set of points, and therefore the figure is drawn by repeating the point drawing. For this reason, access to the frame buffer is performed not in units of 16 bits, but in units of 1 bit or 4 bits smaller than the data width forming the memory. Also,
Generally, when writing a point, an operation with write data is required, so that an operation with memory data and a write in bit units are required. Since ordinary memory does not have these functions, the calculation is executed inside the data processing device that performs graphic drawing processing, the data of the memory address to be written is read, the bit calculation is executed, and then the data is written to the same address. Has been realized. Therefore, even when writing 1-bit data, it is necessary to access the memory twice. In the frame buffer of FIG. 2, the arithmetic unit 1 performs the memory data and the operation of the data processing device to write the data in bit units by the write mask circuit 4, and the memory access necessary for writing the 1-bit data is the data access. It only needs to be done once with the processor. Access to memory 2 is required twice: read and write, but read / write is
Since there is an access mode called “modify / write” that realizes reading and writing in one operation, it can be realized in one operation. As described above, the frame buffer shown in FIG. 2 is effective for speeding up the graphic display, but requires a large number of circuits to be added around the memory element, so that the reliability is reduced and the cost is high. There is a problem that becomes. For the frame buffer shown in FIG. 2, for example, Nikkei Electronics 1984.8.27, “1280 × 1024 pixel graphic display frame buffer 64KRA with nibble mode”
Design with M ”(P.227 to 245). SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit for realizing a compact frame buffer for high speed graphic display in order to solve the above problems. [0006] A storage element capable of arbitrarily reading, writing and storing data, and a computing unit for computing first data from the outside and second data in the storage element. The memory circuit is provided with a register for storing the specified arithmetic function code and a register for storing the specified write control data, and the operation and bit unit are performed based on the output data of the arithmetic function code storage register and the write control data storage register. Writing control is performed. With the above configuration, the designation of the modify operation of read modify write does not depend on the data width of the write data, so that the read modify write operation is executed with an arbitrary data width. A memory circuit having a built-in circuit can be realized, and for example, a frame buffer for high-speed graphic display can be made compact. An embodiment of the present invention will be described in detail below with reference to the drawings. First, the concept of the present invention will be described. In order to reduce the peripheral circuits of the frame buffer memory shown in FIG. 2, an IC (Integrated Memory), an arithmetic unit, an arithmetic function designation register, and a write mask circuit are integrated.
It is possible to make an integrated circuit). In the current graphic display, since a logical operation is mainly required as an arithmetic function, the arithmetic unit can be divided into bit units of arithmetic data. Even when using arithmetic operations, by adding a circuit that handles carry signals,
In principle, bit division is possible. Since the write mask circuit 4 is a circuit that performs write control in bit units, it is obvious that it can be divided in bit units.
However, the arithmetic function designation register 3 has a bit length determined by the number of arithmetic functions of the arithmetic unit 1 and is not related to the bit length of the arithmetic data (here, 16). Can not. Therefore, it is necessary to have the arithmetic function designation register 3 for each divided unit. Thus, it is useless to have the same function for each divided unit, but the degree of integration of the IC increases every year, and the number of elements used as a peripheral circuit with respect to the number of memory elements when integrated is increased. This is not a problem because the ratio of numbers is so small that it does not reach 1%. In the case of integration, having the arithmetic function designation register 3 for each division unit is not so problematic as described above, but it is necessary to divide the frame buffer shown in FIG. 2 into data bit units. Has a problem. In order to use the frame buffer shown in FIG. 2, it is necessary to write arithmetic function data in the arithmetic function designation register 3 and write mask data in the mask circuit 4 before actually performing memory access.
In the frame buffer of FIG. 2, both data use the data signals D <b> 15 to D <b> 0 from the processing device as input signals. Therefore, if the data is divided into bit units, it becomes a 1-bit signal. But,
Only two types of calculations can be specified in the calculation function specification register 3. Thus, it is a problem that the number of arithmetic functions changes depending on the bit configuration of the memory. According to the present invention, since the arithmetic function is specified by the data bus, the fact that it depends on the bit division of data occurs, and the specification is performed by using an address signal that does not depend on the bit division unlike the data bus. Is. Next, an embodiment of the present invention will be described. FIG.
Is the configuration of the frame buffer memory circuit of the embodiment. 1 is an arithmetic unit, 2 is a memory element, 3 is an arithmetic function designating register, 4 is a write mask circuit, Dj is 1 of 16 bits of the data signal of the data processing apparatus for graphic drawing.
Bit signals, A23 to A1 are address signals of the data processing device, WE is a write control signal of the data processing device, FS is a data set control signal for the arithmetic function designation register 3 and the write mask circuit 4, and DOj is read data of the memory element 2. , DIj are the operation result data of the operation unit 1, W
j is a write control signal for the memory element 2. FIG. 3 shows the configuration of the write mask circuit.
Reference numeral 41 is a write mask data storage register, and 42 is a gate for suppressing the write control signal WE. FIG. 4 shows a configuration example of a frame buffer using the memory circuit of FIG. FIG. 4 shows a 4-bit configuration to clarify the connection relationship. FIG. 5 shows an example in which the memory circuit of the embodiment is applied to a graphic display system. Reference numeral 6 denotes a data processing device, and reference numeral 7 denotes a decoding circuit for generating a set signal FS. The operation of the memory circuit according to the embodiment will be described below. In the embodiment, the memory circuit 5 has a capacity of 800000H to 8F.
It is assigned to address FFFFH. Here, H is an address indicating a hexadecimal number and in units of bytes. Decoding circuit 7 outputs set signal FS at addresses 900000H to 90001FH. The computing function of computing unit 1 is shown in FIG.
16 types. The data processing device 6 is, for example, 900
When FOFFH is written to the address 014H, the decode circuit 7 outputs the set signal FS,
Address signals A4 to A1 are set to 0101B (B is bit data). As a result, the arithmetic unit 1
As shown in the calculation function table, OR is selected as the calculation function. In the write mask circuit 4, one bit of 16-bit data 0F00H from the data processing device 6 is set in the write mask data storage register 41. One bit to be set is the same position as the bit position of the memory element. As a result, F0FFH is set as the write mask data. Next, a case where the data processing device 6 writes F3FFH at the address 800000H will be described. 8000
It is assumed that 0512H is stored in the address 00H. The memory access timing of the data processing device 6 is shown in FIG. Write access to the memory circuit 5 of the data processing device 6 is a read-modify-write operation as shown in FIG. 0512H is read to the DO bus at the timing of read-modify-write, and F3FFH is input to the D bus. At the next modify timing, the arithmetic unit 1 calculates the data of the D bus and the DO bus, and outputs the calculation result to the DI bus. In this case, the value of D bus is F3FFH and the value of DO bus is 0.
Since it is 512H, the data on the DI bus is F7FFH. This is because the arithmetic unit 1 selects the logical sum as the arithmetic function in the above-described operation. Finally, the data F7FFH of the DI bus is written at the timing of the read-modify-write write.
As for the write mask data, F0FFH is set, and as shown in FIG. 3, the bit of the mask data of 0 turns on the gate 42 and the 1 bit of the mask data turns off the gate 42.
Since it is F, only the 4 bits D11 to D8 execute the actual write operation, and the write operation does not occur in the remaining 12 bits. As a result, the data at the address 800000H becomes 0712H. As described above, since a part of the address signal is used as a control signal in this embodiment, a memory circuit for performing read / modify / write which can specify an arithmetic function regardless of the data division method is realized. can do. The only difference between the memory circuit of the embodiment and the ordinary memory IC is the set signal FS for setting the arithmetic function and the write mask data, and the number of pins of the IC is increased by only one pin. This does not pose a problem in forming an IC as it is. For example, a dynamic RAM having a 64K × 1 bit configuration does not use one pin, so that it is possible to use FS for this empty pin. It is apparent that this set signal may be realized in a timing sequence different from that of a normal memory access. For example, as shown in FIG.
It is possible to generate a set signal by the falling edge of the RAS signal and the WE signal, which cannot be obtained in the normal sequence of the RAM. Although the data width is 16 bits and the unit of division is 1 bit in this embodiment, it is obvious that either value may be a value other than the value described in this embodiment. In the embodiment, the designation of the arithmetic function and the designation of the write mask are performed at the same time. However, it is apparent that the designation may be performed separately. Further, the data width for designating the function of the arithmetic unit is also 4
It is clear that other than bits may be used. It is also apparent that the present embodiment may be applied to a memory having a built-in shift register and having a serial output. As is apparent from the above description, according to the present invention, the designation of the modify operation of read-modify-write does not depend on the data width of the write data, so that the read operation can be performed with an arbitrary data width. A memory circuit having a built-in circuit for executing a modify write operation can be realized, and for example, a frame buffer for high-speed graphic display can be made compact.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a memory circuit according to an embodiment. FIG. 2 is a block diagram showing a conventional frame buffer memory. FIG. 3 is a diagram showing a write mask circuit. FIG. 4 is a diagram for explaining a frame buffer configuration of the embodiment. FIG. 5 is a block diagram illustrating a configuration example of a graphic display system. FIG. 6 is a diagram for explaining an arithmetic function. FIG. 7 is a timing chart showing memory access timing. FIG. 8 is a timing chart showing set signal creation timing. [Explanation of Codes] 1 ... Arithmetic unit, 2 ... Memory element, 3 ... Arithmetic function designation register, 4 ... Write mask circuit, D15-D0 ... Input data, A23-A1 ... Address signal, WE ... Write control signal, FS ... Set signal.

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[Procedure Amendment] [Date of submission] July 17, 1995 [Procedure Amendment 1] [Document name for amendment] Specification [Item name for amendment] Invention title [Amendment method] Change [Amendment content] Name: Memory system [Procedure amendment 2] [Amendment document name] Specification [Amendment item name] Claims [Amendment method] Change [Amendment content] [Claims] 1. A memory system having a plurality of one-chip memory devices and an external device, wherein each of the plurality of one-chip memory devices includes a storage unit to which a plurality of storage positions are allocated, and an arbitrary one of a plurality of operation modes. A plurality of terminals to which a multi-bit operation instruction signal, which is a control instruction for identifying one of the terminals, is connected, the storage unit and the plurality of terminals, and a predetermined operation mode identified by the operation instruction signal. And a control unit that sets a plurality of bits of the storage unit to a predetermined logical level other than data supplied from an external device, the external device being connected to each of the plurality of one-chip memory devices. , The plurality of one-chip memory devices are supplied with the plurality of bit operation instruction signals via the plurality of terminals of the plurality of one-chip memory devices. Memory system and supplying to the plurality of terminals of the device. 2. The control unit supplies a first operation for setting external data of the one-chip memory device to a plurality of bits of the storage unit as a predetermined operation specified by at least the operation instruction signal of a plurality of bits, and a supply from the external device. Setting a plurality of bits of the storage unit to a predetermined logic level which is data other than data supplied from the outside of the one-chip memory device as a predetermined operation specified by the plurality of bits of the operation instruction signal 2. The memory system according to claim 1, wherein the memory system is selected from the following operations. [Procedure Amendment 3] [Name of Document to be Amended] Specification [Name of Item to Amend] [Correction Method] Change [Content of Amendment] [Problem to be Solved by the Invention] Another object of the present invention is to provide a memory that speeds up processing by shortening processing time for setting an operation mode in a system having a chip memory device. Another object of the present invention is to minimize access to an external device and a memory device for setting the same logic level for a plurality of bits of a storage unit of a one-chip memory device, and to speed up processing of the entire system. It is to provide a memory that can be realized. [Procedure Amendment 4] [Document name for amendment] Specification [Item name for amendment] [Correction method] Change [Content of amendment] [Means for solving the problem] In order to achieve the above-mentioned object, The invention is a memory system having a plurality of one-chip memory devices and an external device, wherein each of the plurality of one-chip memory devices includes a storage unit to which a plurality of storage positions are allocated and a plurality of operation modes. A plurality of terminals to which a plurality of bits of an operation instruction signal, which is a control instruction for specifying any one, are supplied, the storage unit and the plurality of terminals, and a predetermined number of terminals specified by the operation instruction signal. A control unit for setting a plurality of bits of the storage unit to a predetermined logic level other than data supplied from an external device according to an operation mode, Connected to each of the plurality of one-chip memory devices and supplying the operation instruction signal of the plurality of bits to the plurality of terminals of the plurality of one-chip memory devices via the plurality of terminals of each of the plurality of one-chip memory devices. The memory system is characterized by According to a preferred embodiment of the present invention, the control unit sets external data of the one-chip memory device to a plurality of bits of the storage unit as a predetermined operation specified by at least the operation instruction signal of a plurality of bits. Data other than the data supplied from the outside of the one-chip memory device as the first operation and the plurality of bits of the storage unit as the predetermined operation specified by the operation instruction signal of the plurality of bits supplied from the external device. The second operation is to set the logic level to a predetermined logic level. [Procedure Amendment 5] [Name of document to be amended] Specification [Name of item to be amended] 0007 [Amendment method] Change [Amendment content] [Operation] With the above-mentioned configuration, among the plurality of operation modes By specifying the operation mode for setting the storage position of the predetermined block of the storage unit to the predetermined logic level and setting the operation mode, the predetermined value can be set regardless of the value of the data from the outside. It is not necessary to supply external data for externally setting a predetermined logic level to each address of a storage position of a predetermined block of the storage unit. This means that it is not necessary to access the one-chip memory device and the external device at the time of setting the logical level for a predetermined block of the storage unit, and during that time, the external device can execute other processing, so that the system The processing speed can be increased. In addition, by releasing the bus such as the data bus and address bus to which the 1-chip memory device is connected from the access between the 1-chip memory device and the external device, other devices can use the released bus. The processing capacity as a whole can be greatly improved. Furthermore,
Via terminals connected to an address bus that supplies address signals commonly connected to respective storage elements of a plurality of 1-chip memory devices in the system,
Since the operation mode is set, the same operation mode signal can be collectively set for a plurality of one-chip memory devices. This allows multiple multifunctional 1 in the system.
Since it is not necessary to individually supply the operation mode signal to each chip memory device, the time for setting the operation mode can be significantly shortened. [Procedure Amendment 6] [Name of Document to be Amended] Specification [Name of Item to Amend] 0023 [Correction Method] Change [Content of Amendment] [Effect of the Invention] As is apparent from the above description, according to the present invention. For example, if an operation mode that sets a storage position of a predetermined block of a storage unit to a predetermined logic level is specified from among a plurality of operation modes and the operation mode is set, the predetermined operation is performed regardless of the value of data from the outside. Since the value can be set, it is not necessary to supply external data for setting a predetermined logic level from the outside to each address of the storage position of a predetermined block of the storage unit. This means that it is not necessary to access the one-chip memory device and the external device at the time of setting the logical level for a predetermined block of the storage unit, and during that time, the external device can execute other processing, so that the system The processing speed can be increased. In addition, by releasing the bus such as the data bus and address bus to which the 1-chip memory device is connected from the access between the 1-chip memory device and the external device, other devices can use the released bus. The processing capacity as a whole can be greatly improved. Further, since the operation mode is set via the terminal connected to the address bus that supplies the address signal commonly connected to the respective storage elements of the plurality of one-chip memory devices in the system, a plurality of operation modes are set. The same operation mode signal can be collectively set for one chip memory device. This allows
Since it is not necessary to individually supply the operation mode signal to each of the plurality of multifunctional one-chip memory devices in the system, the time for setting the operation mode can be significantly reduced. JP3

Continued front page    (72) Inventor Koichi Kimura             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Hitachi Microelectronics             Device Development Laboratory (72) Inventor Hiromichi Enomoto             1 Horiyamashita, Hadano City Hitachi, Ltd.             Kanagawa factory

Claims (1)

[Claims] 1. In a storage circuit that includes a storage element that can arbitrarily read, write, and store data, and an arithmetic unit that operates the first data from the outside and the second data in the storage element, specify a specified arithmetic function code. A register for storing and a register for storing designated write control data are provided, and operation and bit-wise write control are performed based on output data of the arithmetic function code storage register and the write control data storage register. Memory circuit. 2. The memory circuit according to claim 1, wherein a part of an address signal for the memory element is used as data for specifying an arithmetic function. 3. The memory circuit according to claim 1, wherein a part of an address signal for the memory element is used as write control data. 4. The memory circuit according to claim 1, wherein write data for the memory circuit is used as write control data. 5. The memory circuit according to claim 1, wherein the operation by the operation function code and the write control by the write control data are performed by one memory access. 6. The memory circuit according to claim 1, wherein the memory circuit is integrated into one integrated circuit.