JP2719589B2 - One-chip semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a RAM (Ramdom Acces
s Memory), especially Read-Modify-Writ of stored data
Ru <br/> relates to a one-chip semiconductor memory equipment suitable multifunctional the e operation. 2. Description of the Related Art The prior art will be described by taking image processing as shown in FIGS. 1 and 2 as an example. In FIG. 1, M1 is C
An image area corresponding to an RT (Cathode Ray Tube) screen on a one-to-one basis, M2 is a storage area in which image data to be combined is stored, and FC is data in the image area M1 and a storage area M
This is a Modify function for synthesizing the second data. Further, in FIG. 2, S1 is the data from the image area M1.
S2 is a processing step for reading data from the storage area M2, and S3 is a processing step for reading data from the storage area M2.
Step S4 is a processing step for writing the combined data obtained in step S3 to the image area M1. In the example of the image processing shown in FIG. 1, the processing steps in FIG. On the other hand, the data amount of the target image area M1 is large, usually 100K to several MBytes. Therefore, the series of processes shown in FIG.
The order is the sixth power of 0. For this reason, the following drawbacks have conventionally occurred. (1) As shown in FIG. 2, most of the processing is occupied by the bus cycle (S1, S2, S4) using the bus. Therefore, the occupancy of the bus increases, and the bus load increases. (2) The actual processing time is long due to a low-speed bus or overhead such as occupation control of the bus. (3) Furthermore, in the example of FIG. 2, the number of static steps is as small as four, but the amount of data to be handled is very large, so the number of dynamic steps becomes enormous and the processing time is long. Incidentally, a storage circuit that performs this type of processing is related to, for example, Japanese Patent Publication No. 59-26031. SUMMARY OF THE INVENTION An object of the present invention is to reduce the bus load, facilitate control , and reduce the processing time.
And to provide a chip semiconductor memory equipment. A one-chip semiconductor memory device according to a typical embodiment disclosed in the present invention selects a semiconductor memory element (1) and any one of a plurality of different modes. a plurality of terminals for inputting an instruction signal (S0 to S3) for the connected semiconductor memory device (1) to the plurality of terminals, the indication signal (S0 to S3) have been one of the selected chosen by In mode
, The data is either et subjected sheet microprocessor (Di)
A control unit (1, SEL0, SEL1) for setting a bit of the semiconductor memory element (1) to one predetermined logic level irrelevant to the plurality of instruction signals (S0 to S3). , Which is code data of a plurality of bits inputted from the terminal of (1). According to a preferred embodiment, the plurality of terminals are external terminals to which the instruction signal input from the microprocessor is input . Also, in the representative embodiment disclosed in the present invention,
The one-chip semiconductor memory device is a semiconductor memory device (1)
And any one of several different modes
A plurality of terminals for inputting instruction signals (S0 to S3) for selecting
To the semiconductor memory element (1) and the plurality of terminals.
Selected by the instruction signals (S0 to S3).
In one of the selected modes, the
Independent of the data (Di) supplied from the processor
The semiconductor memory element to one predetermined logic level
And a control unit for setting the bit of (1) unconditionally.
The instruction signals (S0 to S3) are connected to the plurality of terminals.
That it is multi-bit code data input from
Sign. According to a preferred embodiment, the plurality of terminals are
The instruction signal input from the microprocessor is
External terminal to be input. With the above arrangement, in one mode selected from a plurality of different modes by the instruction signals (S0 to S3), which are code data of a plurality of bits,
Control unit (1, SEL0, SEL1) is bit data (Di) wherein the logic value is independent of the semiconductor memory device (1) which is either found subjected sheet microprocessor (Z)
Is set. Thus, for example, the predetermined flight number of bits (Z) identical semiconductor memory device (1)
In setting the logic level of the convex, microprocessor Se
Since the setting is made irrespective of the data supplied from the processor, it is possible to provide a one-chip semiconductor memory device in which the bus load is reduced, the control is easy, and the processing time is reduced. An embodiment of the present invention will be described below. First, the focus of the embodiment will be described with reference to FIG. FIG. 3 shows a process of writing data to a D-RAM (Dynamic-Randam Access Memory) from the outside.
The RAM was a read / write cycle. In FIG.
ADR is an external address, WR is an external write request, and these two signals (ADR, WR) are given from, for example, a microprocessor. RAS is a row address strobe, CAS is a column address strobe, A is an address signal in which column and row addresses are generated in a time division manner, WE is a write enable, DO is read data, and Z is an external (microprocessor) data. These signals except for Z are control signals generated from, for example, a DRAM controller or the like. (1) As shown in FIG. 3, generally, in a read / write cycle, one memory access starts in a read cycle (I) and a write cycle (III) by a write enable WE is executed. (2) Therefore, between the read cycle (I) and the write cycle (III), the read data DO and the external data Z
Appears simultaneously (II). (3) This section (II) is set as a correction section. (4) Further, this correction control can be performed by the external data Z. Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a time chart of the D-RAM as described above. FIG. 4 is a block diagram showing one embodiment of the present invention;
5 is an explanatory diagram of the operation principle of the embodiment shown in FIG. 4, FIG. 6 is a diagram showing an example of a circuit realizing the operation principle shown in FIG.
FIG. 7 is a diagram illustrating details of the operation in FIG. 6. 4, 1 is a control circuit, 2 is a storage element, 3 is a D-RAM controller, X and Y are external data, Z is write data to the storage element, DO is read data from the storage element,
A, CAS, RAS, WE, ADR, and WR are signals of the same type as in FIG. The external data Z shown in FIG. 3 is transferred to the storage element 2 via the control circuit 1 (FIG. 4).
Has been replaced with the write data Z. As shown in FIG. 4, according to the present invention, in the control circuit 1, the read data DO is controlled and corrected by the external data X and Y, and is written into the storage element 2.
This control operation is shown in FIG. In FIG. 5, mode I is a mode in which external data Y is write data Z, mode II
Is a mode in which the read data DO is used as the write data Z. As shown in FIG. 5, the read data DO of the storage element 2 is corrected and written by external data X and Y, that is, by external control (mode II), or write processing of external data Y (mode I). Mode can be controlled. In these two modes, (i) the modes I and II are specified by the external data X, and (ii) the non-inversion and inversion of the read data DO in the mode II are specified (corrected) by the external data. FIG. 6 shows a specific example of a circuit for realizing the above operation.
FIG. 7 shows a detailed truth value of the operation. 6 and 7
As shown in the above, the present invention can be realized by a combination of two logics. Further, the above operation is performed as shown in FIG.
Execution can be completed during a memory cycle. On the other hand, the circuit shown in FIG. 6 is represented by the following logical expression (1). Z = (NOT X) .Y + X. (Y EOR DO) (1) where (NOT X) indicates the inversion of X and EOR indicates the exclusive OR. In addition, a signal "0", a signal "1", for example, bus data Di from a microprocessor and its inverted data (NOT Di) are assigned to expression (1) as possible values of data X and Y that can be controlled from the outside. , The result of the binomial logical operation as shown in FIG. 8 is obtained. However, in FIG. 8, the above NOT is represented by an overline. FIG. 9 shows an actual circuit obtained by combining this with FIG. In FIG. 9, SEL0 and SEL1 are 4-input selectors, and S0 and S0.
S1 is an input selection signal of the selector SEL0, S2 and S3 are input selection signals of the selector SEL1, and INV is an inverting element. Hereinafter, an operation example will be specifically described with reference to FIGS. 1, 8, 9, and 10. As shown in FIG. 8, the input selection signals S0 and S1 are selection signals for the selector SEL0, and the value of the data X is determined by the signals S0 and S1. Similarly, data Y is determined by input selection signals S2 and S3. As described above, possible values of these data X and Y are signal "0", signal "1", bus data Di,
Each of the selectors SEL0 and SEL1 is made one of the four signals by the input selection signals S0, S1, S2 and S3 as shown in FIG. 9 as the inverted data (NOT Di).
One is selected. FIG. 8 shows input selection signals S0, S1,
It shows the relationship between S2 and S3 and the data X and Y output from the selectors SEL0 and SEL1, and further shows the operation (the value of the write data Z) of the control circuit 1 expressed by the above equation (1). For example, image processing (OR operation:
In Case 1), the input selection signals S0, S1 = (1
By setting 1), S2, 3 = (10), X = (NOT Di) and Y = Di are selected as data X, Y, respectively. By substituting the values of these data X and Y into the equation (1) representing the operation of the control circuit 1, it can be seen that the OR operation of Z = Di + Do can be executed. Therefore, according to the present invention, in the image processing of FIG. 1, as shown in FIG. 10, the input selection signals S0, 1, 2, 3 are designated (designation of Function) in the first one step, and thereafter, it is desired to combine them. The image processing shown in FIG. 1 can be executed by simply reading the image data from the storage area M2 and performing a simple write operation on the image area M1. Further, the present invention can execute various logic functions as shown in FIG. Therefore, as shown in FIG. 11, for example, it is possible to easily draw an arbitrary moving mouse cursor. As shown in FIG. 11, the mouse cursor (M2) is moved to the image area M1.
Since the cursor must be displayed even when the image overlaps with the image inside, the function needs an EOR function. That is, in this cursor display, the processing as shown in FIG. 10 can be performed in the same manner as in the case of the above-described image synthesis (FIG. 1) with the input selection signals S0, 1 = (01), S2, 3 = (10). . Therefore, the input selection signal S
By changing the values of 0, 1, 2, and 3, various logic functions as shown in FIG. 8 can be easily executed.
Read, modify, and write to the storage element 2 can be executed only by the e operation. In this manner, by adopting the configuration as shown in FIG. 9, data Di from the microprocessor and storage element 2 are stored.
The binary logic operation shown in FIG. 8 can be performed as Modify with the read data Do. The binary logical operation is specified by the input selection signals S0 to S3. As described above, by using the embodiment, the conventional image combining process using FIGS. 1 and 2 can be simplified as shown in FIG. The embodiment described above has three functions as shown in FIG. 9, namely, a storage unit composed of the storage element 2, a control unit composed of the control circuit 1, and the selector SE.
It is divided into a selector section composed of L0 and L1. However, the function realized by the combination of the control and the selector section is the binomial logical operation function shown in FIG. 8, and this function can be easily achieved by other means. Further, according to the embodiment, the following effects can be obtained. (1) When the processing as shown in FIG. 1 is performed, the memory cycle can be reduced as shown in FIG. 10, so that the above-mentioned conventional disadvantage can be eliminated. (2) Further, the microprocessor can execute three processes of read, modify, and write in one write cycle, so that the processing time can be further shortened. (3) Since the ratio of the memory element group to the entire circuit according to the present invention is smaller than that of the memory element group, it is possible to easily form an LSI. (4) Most of the currently available 64K × 4 bit D-RAMs have one Pin as a No-Connection, and the storage element 2 and the control circuit 1 are connected to the point b shown in FIG. Even in the case where the number of pins is increased, the number of Pins does not increase, which is extremely advantageous for LSI. According to the present invention, in one mode selected from a plurality of different modes by an instruction signal which is code data of a plurality of bits, the control unit includes:
It is for setting the bit of the semiconductor memory device to a predetermined one logic level is independent of the microprocessor or we subjected the sheet to be data. Accordingly, a predetermined one of the logical number of bits of the same of the semiconductor memory device
When setting to the logical level , the microprocessor
Since is set independently of the supply to the data, reducing the bus load, the control is easy, it is possible to provide a one-chip semiconductor memory equipment having a small processing time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a conventional technique by taking image processing as an example. FIG. 2 is a flowchart of FIG. FIG. 3 is a time chart in a process of writing data to a D-RAM. FIG. 4 is a block diagram showing one embodiment of the present invention. FIG. 5 is a diagram for explaining the operation principle of FIG. 4; FIG. 6 is a diagram showing an example of a circuit for realizing the operation principle of FIG. 5; FIG. 7 is a diagram for explaining the operation of FIG. 6; FIG. 8 is a diagram illustrating a relationship between an input selection signal and a selector output. FIG. 9 is a circuit diagram for realizing FIG. 8; FIG. 10 is a flowchart when the present invention is applied to image processing. FIG. 11 is a diagram for explaining another application example of the present invention. [Description of Signs] 1 ... Control circuit, 2 ... Storage element, SEL ... Selector.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Hiroaki Aozu               292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa               Hitachi, Ltd. Microelectronics               Equipment development laboratory (72) Inventor Mitsuru Ikegami               1 Horiyamashita, Hadano-shi, Kanagawa               Inside the Kanagawa Factory

Claims (1)

(57) [Claims] A semiconductor memory element, a plurality of terminals for inputting an instruction signal for selecting any one mode from a plurality of different modes, and a plurality of terminals connected to the semiconductor memory element and the plurality of terminals, selected by the instruction signal. The selected one mode
In de, and a control unit for setting the bit of the semiconductor memory device in the logic level of one of a predetermined independent of the data being either et subjected sheet microprocessor
A one-chip semiconductor memory device , wherein the instruction signal is code data of a plurality of bits input from the plurality of terminals. 2. The plurality of terminals are input from the microprocessor
2. The one-chip semiconductor memory device according to claim 1, wherein said one-chip semiconductor memory device is an external terminal to which said instruction signal is input . 3. Select any one mode from the semiconductor memory element and a plurality of different modes
A plurality of terminals for inputting an instruction signal for being connected to the semiconductor storage element and the plurality of terminals;
The selected one mode selected by the instruction signal
Data supplied by the microprocessor.
Before a predetermined logic level that is unrelated to
The control unit that sets the bits of the semiconductor memory element unconditionally
; And a Tsu bets, multiple bits the instruction signal is inputted from said plurality of terminals
1-chip semi-conductor characterized in that it is code data of
Body storage. 4. The plurality of terminals are input from the microprocessor
External terminal to which the instruction signal is input.
A one-chip semiconductor device according to claim 3, characterized in that:
Storage device.