JP2886855B2 - Image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly to an image display device that displays image data composed of a large number of pixels. [Background of the Invention] The prior art will be described by taking an example of image processing as shown in FIGS. In FIG. 1, M1 is, for example, a CRT (Cat
hode Ray Tube) One-to-one image area corresponding to the screen, M
2 is a storage area where image data to be combined is stored, FC
Is a Modify section for synthesizing the data of the image area M1 and the data of the storage area M2. Also, in FIG.
S1 is a processing step of reading data from the image area M1,
S2 is a processing step of reading data from the storage area M2,
S3 is a processing step for synthesizing the data of the read image area M1 and the storage area M2, and S4 is a processing step of writing the synthesized data obtained in step S3 to the image area M1. In the example of the image processing shown in FIG.
In order to combine the data of M1 and the storage area M2, the processing step S3 shown in FIG. 2 executes a logical sum. On the other hand, the data amount of the target image area M1 is usually 10
The capacity is as large as 0K to several MByte. Therefore, image area M1
Is composed of a plurality of memory devices. Therefore, the series of image processing shown in FIG.
When processing in the unit, the number of repetition becomes 10 ⁶ order. For this reason, there were the following problems. (1) As shown in FIG. 2, most of the image processing is occupied by the steps S ₁ , S ₂ , and S ₄ using the bus, so that the occupancy of the bus increases and the bus load increases. (2) In addition, the actual processing (display) time becomes longer due to a low-speed bus or overhead such as bus occupation control. (3) Furthermore, in the example of FIG. 2, the number of static processing steps is as small as 4 steps, but as described above, the amount of data to be handled is extremely large, and the number of dynamic processing steps that requires substantial processing time is extremely large. And an enormous amount of processing time is required. Therefore, realization of image processing with fewer processing steps is desired. A related memory circuit for performing this type of processing is disclosed in, for example, Japanese Patent Application Laid-Open No. 59-60658. [Purpose of the Invention] An object of the present invention is to provide an image display device whose circuit design and configuration are simple when displaying image data composed of a large number of pixels. Another object of the present invention is to provide an image display device that can easily determine a display order when graphic regions on a display screen overlap. Another object of the present invention is to provide an image display device in which image processing in pixel units is easy and the circuit configuration is simple. [Summary of the Invention] In order to achieve the above object, the present invention has the following constitution. An image display apparatus for displaying a plurality of graphics in a superimposed manner, wherein a plurality of image data including the plurality of graphics are stored in units of pixels, and a plurality of image data including the plurality of graphics are stored for each pixel. And inputting a priority designating signal for designating a priority of display of the graphic, and when graphic regions included in the image data overlap with each other, priority is given to priority among the graphic regions according to the priority designating signal. A priority control unit that determines a graphic area to be displayed on the
A priority designation signal indicating the result selected by the priority control unit and the plurality of image data are input for each pixel, and image data including a graphic area determined from the plurality of image data based on the priority designation signal is output. Means to choose;
One of the selected image data and the plurality of image data is input for each pixel, the stored image data is synthesized in pixel units, and the display determined using the selected image data is performed. A logic operation unit for superimposing and outputting in an order and an operation control signal for controlling a logic operation executed by the logic operation unit based on an instruction from an image processor of the image device are input to the logic operation unit. An image display device comprising: an operation control signal input unit. Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. First, a storage circuit according to the present invention will be described. For example, the storage circuit corrects data already stored in the storage element and returns the corrected data to the storage element at the same address in order to speed up the above-described image synthesis processing (data rewriting processing). It has a writing function and a function of writing external data to the storage element. In the present invention, the storage circuit having the above two functions is realized by focusing on the following points, and will be described with reference to FIG. FIG. 3 shows a D-RAM (Dynamic-Random Acc
ess memory), and at this time, the D-RAM has a read / write cycle.
In FIG. 3, ADR is an external address, WR is an external write request, and these two signals (ADR, W
R) is provided, for example, by a microprocessor. RAS is a row address strobe, CAS is a column address strobe, A is an address signal in which column and row addresses are generated in a time-division manner, WE is a write enable, Do is read data, and Z is an external (microprocessor) data. so,
These signals except for Z are control signals generated from, for example, a DRAM controller. (I) As shown in FIG. 3, generally, in a read / write cycle, one memory access starts in a read cycle (I) and a write cycle (III) by a write enable WE is executed. (Ii) Therefore, between the read cycle (I) and the write cycle (III), a section (II) in which the read data Do and the external data Z are simultaneously present appears. (Iii) This section (II) is defined as a correction section. (Iv) Further, this correction control can be performed by the external data Z. FIG. 3 is a timing chart of the D-RAM as described above. FIG. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is an explanatory diagram of the operation principle of the embodiment shown in FIG. 4, and FIG. 6 realizes the operation principle shown in FIG. 7 is a detailed description of the operation of FIG. 6. In FIG. 4, 1 is a control circuit, 2 is a storage element, 3 is a D-RAM controller, X and Y are external data, Z is write data to the storage element, Do is read data from the storage element, A , CAS, RAS, WE, ADR, WR are the same signals as in FIG. The external data Z shown in FIG.
In the figure, the write data Z to the storage element 2 via the control circuit 1 is replaced. As shown in FIG. 4, according to the present invention, in the control circuit 1,
FIG. 5 shows this control operation in which the read data Do is controlled by the external data X and Y, corrected, and written into the storage element 2. In FIG. 5, mode I is a mode in which external data Y is write data Z, and mode II is a mode in which read data Do is write data Z. As shown in the figure, external data X and Y
In other words, the two modes of correcting and writing the read data Do of the storage element 2 (mode II) or writing the external data Y (mode I) can be controlled by external control. (I) The mode I and the mode II are designated by the external data X, and (ii) The non-inversion and inversion of the read data Do in the mode II are designated (corrected) by the external data. FIG. 6 shows a specific example of a circuit realizing the above operation. FIG. 7 shows a detailed truth value of the operation. Sixth
As shown in FIG. 7 and FIG. 7, the present invention can be implemented by a combination of two logics. The above operation can be completed within one memory cycle as shown in FIG. On the other hand, the circuit shown in FIG. 6 is represented by the following logical expression (1). Z = ・ Y + X ・ (YDo) (1) In addition, as a possible value of the data X and Y that can be controlled from the outside, a signal “0”, a signal “1”, for example, Bus data Di, its inverted data ▲
By assigning and organizing ▼, the result of the binomial logical operation as shown in FIG. 8 is obtained. FIG. 9 shows an actual circuit obtained by combining this with FIG. In FIG. 9, SEL0,1 is 4
Input selectors, S ₀ and S ₁ are input selection signals of the selector SEL ₀ , S ₂ and S ₃ are input selection signals of the selector SEL 1, and INV is an inverting element. Hereinafter, the operation will be specifically described with reference to FIGS. 1, 8, 9 and 10. As shown in FIG. 8, the input selection signals S ₀ and S ₁
EL0 a selection signal, the data X by the signal S _0, S ₁
Determine the value of. Similarly, according to the input selection signals S ₂ and S ₃ ,
Data Y is determined. The possible values of these data X and Y are signal "0", signal "1", bus data Di and its inverted data ▲ ▼ as described above, and as shown in FIG. ₀ , S ₁ , S ₂ , S ₃ , each selector SEL0,1
Respectively, one of the above four signals is selected.
FIG. 8 shows the input selection signals S ₀ , S ₁ , S ₂ , S ₃ and the selectors SEL 0,
1 shows the relationship with the output data X, Y, and furthermore, the operation of the control circuit 1 (write data Z
Value). For example, in the image processing (OR operation: case 1) as shown in FIG. 1, the input selection signals S ₀ , S ₁ = (1
By setting 1), S ₂ , ₃ = (10), data X and Y are X
= ▲ ▼, Y = Di is selected. By substituting the values of these data X and Y into the equation (1) representing the operation of the control circuit 1, it can be seen that the OR operation of Z = Di + Do can be executed. Therefore, according to the present invention, the image processing for the data in the image areas M1 and M2 constituted by the plurality of memory devices shown in FIG. 1 is performed in the first step as shown in FIG. Designate S ₀ , ₁ , ₂ , ₃ (Function designation), then read the image data to be synthesized from the storage area M2,
The image processing shown in FIG. 1 can be executed only by a simple write operation to the image area M1. Further, the present invention can execute various logic functions as shown in FIG. Therefore, it is possible to easily draw, for example, an arbitrarily moving mouse cursor as shown in FIG. As shown in FIG. 11, even when the mouse cursor (M ₂ ) overlaps the image in the image area M1, the mouse cursor (M ₂ ) must display the cursor. Therefore, the function requires the EOR function. That is, in this cursor display, input selection signals S _{0, 1} = (01), the S _{2, 3} = (10) as the processing as FIG. 10 in the same manner as in the synthesis of the image as described above (Figure 1) It can be carried out. Therefore, by changing the values of the input selection signals S ₀ , ₁ , ₂ , and ₃ , various logic functions as shown in FIG. 8 can be easily executed, and reading from the storage element 2 can be performed only by a simple write operation. . Modify. Light can be executed. In this way, by adopting the configuration as shown in FIG. 9, the data Di from the microprocessor and the read data Do of the storage element 2 are read.
The binary logic operation shown in FIG. 8 can be performed as Modify. Note binary logic operation is designated by the input selection signal S ₀ to S _3. By using the present invention described above, FIG.
The conventional image synthesizing process using the figure can simplify the process as shown in FIG. The embodiment of the present invention described above has three functions as shown in FIG. 9, namely, a storage unit composed of the storage element 2, a control unit composed of the control circuit 1, and the selector SEL.
It is divided into a selector section composed of 0 and 1. However, the function realized by the combination of the control unit and the selector unit is the binomial logical operation function shown in FIG. 8, and this function can be easily achieved by other means. On the other hand, image processing usually requires processing when graphics and the like as shown in FIGS. 12 and 13 overlap. That is,
When the figure on the storage area M2 is displayed over the figure on the image area M1 as shown in FIG. 12, and the figure on the image area M1 is displayed over the figure on the storage area M2 as shown in FIG. There are cases. The processing shown in FIGS. 12 and 13 is difficult to perform during one memory access cycle only by the above-described logic function (FC section shown in FIG. 9). However, if the storage circuit of the present invention is applied, it can be easily dealt with by adding a simple logic circuit and a selector circuit. This embodiment will be described with reference to FIGS. 14, 15, and 16. FIG. It should be noted that FC in FIG. 14 indicates a part in which the above-described logic function is implemented as hardware, as shown in FIG. In the present embodiment, for example, the values of the input selection signals S ₀ , S ₁ , S ₂ , and S ₃ of the selector SEL0 and the selector SEL1 are set to ( ₀ , ₀ , ₀ , ₁ ).
And the logic function unit FC operates in the Pass mode. In FIG. 14, 4 is a priority control unit, SEL2 is a two-input selector, P is a priority designation signal, S4 is an input selection signal of the selector SEL2, Di 'is image data from the storage area M2, M1 is an image area, Di Is a selection signal from the selector SEL2, and Do is image data from the image area M1 (the storage element 2 shown in FIG. 9).
, Z represents the same signal as the output signal of the control circuit 1 shown in FIG. For simplicity of explanation, the graphic area is set to logic "1" and the base area is set to logic "0" as shown in FIG. Here, the priority control unit 4 and the selector SEL2 operate according to the truth table shown in FIG. That is, when it is desired to display the graphic in the storage area M2 on the graphic in the image area M1 as shown in FIG. 12, the priority specifying signal P is set to "0", and as shown in FIG. As described above, when the image data Di 'and Do are both data in the graphic area ("1"), the data Di' in the storage area M2 is preferentially selected by the selector SEL2. When the priority designation signal P is designated as "1", image processing is performed as shown in FIG. 13 in accordance with the truth table of FIG. That is, when the graphic areas ("1") overlap, either the graphic area of the image area M1 or the graphic area of the storage area M2 is selected by the priority designation signal P, and the area where the graphic area does not exist is selected. Selects the data of the image area M1 as a background. FIG. 16 shows a specific circuit diagram of the priority control section 4 shown in FIG. In FIG. 16, reference numeral 40 denotes a three-input NAND circuit;
Is a two-input NAND circuit. In order to apply the principle of this priority determination to color data having a plurality of bits of information per pixel, the circuit must be as shown in FIG. In FIG. 17, 5 is a graphic area (COL) of the image area M1.
A comparison / determination unit for determining 3) and a comparison / determination unit 6 for determining the graphic area (COL1) of the storage area M1. Here, FIG. 17 shows a case where the priority determination unit 4, the logic function FC, and the selector SEL2 are in the same memory chip.
4 illustrates a case of a pixel (4 bits) configuration. As can be seen from FIG. 17, if the present invention is used, even in the case of color data, it is possible to easily process the overlapping of images by adding, for example, the comparison determination units 5 and 6 outside. It is also apparent that the present embodiment may be applied to a memory having a built-in shift register and having a serial output. According to this embodiment, the following effects can be obtained. (1) When the processing shown in Fig. 1 is executed,
As shown in the figure, the memory cycle can be shortened, so that the conventional problem described above can be solved. (2) Further, according to the present invention, three processes of read, modify, and write can be executed in one write cycle, so that a high-speed process can be realized. (3) Furthermore, priority processing when images overlap is
As shown in FIGS. 15, 16 and 17, this can be handled with a few simple logic gates. (4) Also, color data can be easily realized by adding a comparison determination unit for a graphic area (code data of 2 bits or more) externally. (5) Compared with the memory element group, the scale of the circuit configuration required for realizing the present invention is very small, and therefore, is extremely advantageous for implementing LSi in the same chip. [Effects of the Invention] According to the configuration of the present invention, the following effects can be obtained. When displaying image data composed of a large number of pixels, it is possible to provide an image display device whose circuit design and configuration are simple. Further, it is possible to provide an image display device that can easily determine a display order when graphic regions on a display screen overlap. Further, it is possible to provide an image display device in which image processing in pixel units is easy and the circuit configuration is simple.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining graphic synthesis, FIG. 2 is a flowchart showing processing when the graphic synthesis of FIG. 1 is performed by a conventional technique, and FIG. 4 is a timing chart showing the operation, FIG. 4 is a diagram for explaining the configuration of the memory with a logical function, FIG. 5 is a diagram for explaining the operation mode of the memory shown in FIG. 4, and FIG. 6 is a logical function 7 and 8 are diagrams for explaining a detailed truth value, FIG. 9 is a block diagram showing a configuration of a memory with a logical function, and FIG. 10 is a diagram shown in FIG. FIG. 11 is a flowchart showing a graphic synthesizing process when a memory is used, FIG. 11 is a diagram for explaining graphic synthesizing when an EOR logic function is used, and FIG.
FIG. 13, FIG. 13 is a diagram for explaining the graphic synthesis targeted by the present invention, FIG. 14 is a diagram for explaining one embodiment of the present invention, and FIG. 15 is a detailed operation logic of the present invention. FIG. 16 is a circuit diagram showing one embodiment of the present invention, and FIG. 17 is a diagram for explaining one embodiment when color data is used. 1 ... control circuit, 2 ... memory element, 4 ... priority control unit, SEL0,1,2 ... selector.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroaki Aotsu 292, Yoshida-cho, Totsuka-ku, Yokohama-shi Inside the Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Hiromichi Enomoto 1-Horiyamashita, Hadano-shi, Hitachi Hitachi, Ltd. Inside the Tokoro Kanagawa Plant (72) Tadashi Kyoda 1 Horiyamashita, Hadano City Inside the Kanagawa Plant, Hitachi, Ltd. (56) References JP-A-59-188764 (JP, A) JP-A-57-687 (JP, A) JP-A-58-129552 (JP, A) JP-A-48-93234 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 15/62 G06F 12/00 G06F 3 / 00 G09G 5/00

Claims (1)

(57) [Claims] An image display apparatus for displaying a plurality of graphics in a superimposed manner, wherein: a means for storing a plurality of image data including the plurality of graphics in pixel units; and a plurality of image data including the plurality of graphics in each pixel, And inputting a priority designating signal for designating a priority of display of the graphic, and when graphic regions included in the image data overlap with each other, priority is given to priority among the graphic regions according to the priority designating signal. A priority control unit that determines a graphic area to be displayed, a priority designation signal indicating a result selected by the priority control unit, and the plurality of image data are input for each pixel, and the plurality of the plurality of image data are input based on the priority designation signal. Means for selecting image data including a graphic area determined from the image data; and selecting one of the selected image data and the plurality of image data as pixels. A logical operation unit for inputting each of the image data, synthesizing the stored image data in pixel units, and using the selected image data to overlap and output in a determined display order; and an image processor of the image device. Based on the instructions of
An image display device, comprising: an operation control signal input unit that inputs an operation control signal for controlling a logical operation performed by the logical operation unit to the logical operation unit.