JPH0863386A - Storage circuit - Google Patents

Abstract

PURPOSE: To provide the storage circuit with the bus load reduced and with the shorter processing time. CONSTITUTION: A storage element 2 capable of performing reading, writing, and preserving data in provided with a control circuit 1 which stores the 1st mode storing the 1st data in a storage element 2 from the 1st data from the outside and the 2nd data in the storage element 2, the 2nd mode storing the 2nd data again in the storage element 2, and the 3rd mode storing the inverse data of the 2nd data again in the storage element 2. Thus, the storage circuit with the bus load reduced and with the shorter processing time can be provided.

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a RAM (Ramdom Acces)
s Memory), especially Read-Modify-Writ of stored data.
The present invention relates to a multifunctional memory circuit suitable for e-operation. 2. Description of the Related Art The prior art will be described by taking the image processing as shown in FIGS. 1 and 2 as an example. In FIG. 1, M1 is C
An image area corresponding one-to-one with an RT (Cathode Ray Tube) screen, M2 is a storage area in which image data to be combined is stored, and FC is data in the image area M1 and storage area M.
It is a Modify function for synthesizing the data of 2. Further, in FIG. 2, S1 is the data from the image area M1.
ad processing step, S2 is a processing step of reading data from the storage area M2, and S3 is a read image area M.
1 is a processing step for synthesizing the data in 1 and the storage area M2, and S4 is a writing processing step for writing the synthesized data obtained in step S3 into the image area M1. In the example of the image processing shown in FIG. 1, the processing steps in FIG. 2 have a logical sum function because they are simply synthesized. On the other hand, the amount of data in the target image area M1 is large, usually 100K to several MBytes. Therefore, in the series of processes shown in FIG. 2, even when the data is processed in Byte units, the number of repetitions is on the order of 10 6 power. Therefore, conventionally, the following drawbacks have occurred. That is, (1) As shown in FIG. 2, in this processing, most of them are occupied by bus cycles (S1, S2, S4) using the bus. Therefore, the occupation rate of the bus increases and the bus load increases. (2) Further, the actual processing time is long due to a low-speed bus and overhead such as bus occupancy control. (3) Further, in the example of FIG. 2, the number of static steps is as small as 4, but the amount of data to be handled is so large that the number of dynamic steps becomes enormous and the processing time is long. A related memory circuit for performing this type of processing is, for example, Japanese Patent Publication No. 59-26031.
Publication. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit which eliminates the above-mentioned drawbacks of the prior art, reduces the bus load, and shortens the processing time. In order to achieve the above object, the present invention has the following two functions in order to speed up the above-described image synthesizing process (data rewriting process). It is a memory circuit that has both. A) A processing function of correcting the data already stored in the storage element and rewriting the correction data in the storage element at the same address. B) A general external data write processing function to the storage element. Further, in the present invention, the memory circuit having the above two functions is realized by focusing on the following points.
Will be explained. Figure 3 shows the external D-RAM (Dynami
c-Randam Access Memory), and the D-RAM was set to a read / write cycle at this time. In FIG. 3, ADR is an external address, WR is a write request from the outside, and these two signals (ADR, WR) are given from, for example, a microprocessor. Further, RAS is a row address strobe, CAS is a column address strobe, A is an address signal in which column and row addresses are generated in a time division manner, WE is write enable, DO is read data, and Z is data from an external (microprocessor). And these signals are Z
Is a control signal generated from, for example, a DRAM controller. That is, (1) As shown in FIG. 3, generally, in the read / write cycle, one memory access starts in the read cycle (I) and the write cycle (III) by the write enable WE is executed. (2) Therefore, between the read cycle (I) and the write cycle (III), the read data DO and the external data Z
The section (II) in which is present at the same time appears. (3) This section (II) is used as a correction section, and (4) this correction control can be performed by the external data Z. An embodiment of the present invention will be described below with reference to FIGS. 3 to 11. FIG. 3 is a time chart of the D-RAM as described above. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is an explanatory diagram of an operation principle of the embodiment shown in FIG. 4, and FIG. 6 is a diagram showing an example of a circuit realizing the operation principle shown in FIG. , FIG. 7 is a diagram for explaining the details of the operation of FIG. In FIG. 4, 1 is a control circuit, 2 is a storage element, 3 is a D-RAM controller, X and Y are external data, Z is write data to the storage element, and DO is read data from the storage element. , A, CAS, RAS, WE, A
DR and WR are signals of the same type as those in FIG. 3 described above. In addition,
The external data Z shown in FIG. 3 is replaced here with the write data Z to the storage element 2 via the control circuit 1 (FIG. 4). As shown in FIG. 4, according to the present invention, in the control circuit 1, the read data DO is controlled by the external data X and Y.
Correct and write to storage element 2. This control operation is shown in FIG. In FIG. 5, mode I is a mode in which the external data Y is the write data Z, and mode II is a mode in which the read data DO is the write data Z. As shown in FIG. 5, the read data DO of the storage element 2 is corrected and written by the external data X and Y, that is, by the control from the outside (mode I
I) or writing process of external data Y (mode I),
The two modes can be controlled. These two modes are controlled by (i) mode I, II designation by external data X
(Ii) The designation (correction) of non-inversion and inversion of the read data DO in the mode II is performed by the external data. FIG. 6 shows a concrete circuit example for realizing the above-mentioned operation. The detailed truth value of the operation is shown in FIG. As shown in FIGS. 6 and 7, the present invention can be realized by combining two logics. The above-described operation can be completed within one memory cycle as shown in FIG. On the other hand, the circuit shown in FIG. 6 is expressed by the following logical expression (1). Z = (NOT X) · Y + X · (Y EOR DO) (1) where (NOT X) represents the inversion of X, and EOR represents the exclusive OR. Further, as the possible values of the data X and Y which can be controlled from the outside, in the equation (1), the signal "0", the signal "1", for example, the bus data D from the microprocessor is used.
When i and its inverted data (NOT Di) are assigned and arranged, a binomial logical operation result as shown in FIG. 8 is obtained. However, in FIG. 8, the NOT is represented by an overline. FIG. 9 shows this as an actual circuit in combination with FIG. In FIG. 9, SEL0 and 1 are 4-input selectors, S0 and S1 are input selection signals of the selector SEL0, S2 and S3 are input selection signals of the selector SEL1,
INV is an inverting element. Hereinafter, an operation example will be specifically described with reference to FIGS. 1, 8, 9, and 10. As shown in FIG. 8, input selection signals S0, S1
Is a selection signal of the selector SEL0.
The value of the data X is determined by S1. Similarly, the data Y is determined by the input selection signals S2 and S3. The possible values of these data X and Y are as described above.
The signal "0", the signal "1", the bus data Di, and its inverted data (NOT Di) are used, and the selectors SEL are selected by the input selection signals S0, S1, S2 and S3 as shown in FIG.
One of the above four signals is selected for 0 and 1, respectively. FIG. 8 shows input selection signals S0, S1, S2, S3.
And the data X and Y which are the outputs of the selectors SEL0 and SEL, and the operation of the control circuit 1 (the value of the write data Z) that can be expressed by the equation (1). For example,
Image processing as shown in FIG. 1 (OR operation: Case 1)
Then, the input selection signals S0, S1 = (11), S2, 3 =
By setting (10), the data X and Y are respectively X = (N
OT Di), Y = Di is selected. By substituting the values of these data X and Y into the equation (1) representing the operation of the control circuit 1, it is understood that the OR operation of Z = Di + Do can be executed. Therefore, according to the present invention, in the image processing of FIG. 1, as shown in FIG. 10, it is desired to specify the input selection signals S0, 1, 2, and 3 (specification of Function) in the first one step, and to synthesize after that. Read image data from storage area M2
However, the image processing shown in FIG. 1 can be executed only by a simple write operation to the image area M1. Further, the present invention can execute various logical functions as shown in FIG. Therefore, as shown in FIG. 11, it is possible to easily draw a mouse cursor that moves arbitrarily. As shown in FIG. 11, even if the mouse cursor (M2) overlaps the image in the image area M1, the cursor must be displayed. Therefore, the function requires the EOR function. That is, in this cursor display, the input selection signals S0,1 =
The processing as shown in FIG. 10 can be performed in the same manner as the above-described image composition (FIG. 1) with (01), S2, 3 = (10). Therefore, various logical functions as shown in FIG. 8 can be easily executed by changing the values of the input selection signals S0, 1, 2, 3 and further, the read / modify with the memory element 2 can be performed only by a simple write operation. , Lights can be executed. By adopting the configuration as shown in FIG. 9 in this manner, the binary logic operation shown in FIG. 8 can be performed as Modify between the data Di from the microprocessor and the read data Do of the storage element 2. The binomial logical operation is designated by the input selection signals S0 to S3. By using the embodiment as described above, the conventional image synthesizing process using FIG. 1 and FIG.
The processing can be simplified as shown in 0. The embodiment described above has three functions as shown in FIG. 9, that is, a storage unit including the storage element 2, a control unit including the control circuit 1, and selectors SEL0 and SEL1. Divided into divisions. However, the function realized by the combination of the above control and the selector section is the binomial logical operation function shown in FIG. 8, and this function can be easily achieved by other means. As described above, according to the present invention, the following effects can be obtained. (1) When the processing shown in FIG. 1 is performed, the memory cycle can be reduced as shown in FIG.
It is possible to eliminate the above-mentioned conventional defects. (2) In addition, the microprocessor can perform three operations of read, modify and write in one write cycle.
Since one process can be executed, the processing time can be further shortened and the processing time can be further increased. (3) Compared with the memory element group, the ratio of the circuit according to the present invention to the whole circuit is small, so that it is possible to easily form an LSI. (4) Most of the 64K × 4bit D-RAMs currently on the market have one Pin as No-Connection.
Therefore, even if the point b shown in FIG. 10 is reached, that is, even if the memory element 2 and the control circuit 1 are integrated into an LSI, the number of Pins does not increase, which is extremely advantageous for integration into an LSI.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining a conventional technique by taking image processing as an example. FIG. 2 is a flowchart of FIG. FIG. 3 is a time chart in the data writing process to the D-RAM. FIG. 4 is a block diagram showing an embodiment of the present invention. 5 is a diagram for explaining the operation principle of FIG. 4; 6 is a diagram showing an example of a circuit that realizes the operation principle of FIG. FIG. 7 is a diagram for explaining the operation of FIG. FIG. 8 is a diagram showing a relationship between an input selection signal and a selector output. 9 is a circuit diagram for realizing FIG. 8. FIG. FIG. 10 is a flowchart when the present invention is applied to image processing. FIG. 11 is a diagram for explaining another application example of the present invention. [Explanation of Codes] 1 ... Control circuit, 2 ... Storage element, SEL ... Selector.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroaki Aozu             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi, Ltd. Microelectronics             Equipment Development Laboratory (72) Inventor Mitsuru Ikegami             Hitachi, Ltd. 1 Horiyamashita, Hadano City, Kanagawa Prefecture             Factory Kanagawa factory

Claims (1)

[Claims] 1. In a storage element capable of arbitrarily reading, writing, and storing data, a first mode for storing the first data in the storage element from external first data and second data in the storage element And a control circuit capable of taking a second mode for storing the second data again in the storage element and a third mode for storing inverted data of the second data in the storage element again. A memory circuit characterized by. 2. In claim 1, the selection of the three modes in the control circuit is performed by adding a third data input from the outside to distinguish the first mode from other second and third modes. Is controlled by the third data, and the designation of the second and third modes is controlled by the first data. 3. In claim 2, two selectors for selecting one data from a plurality of input data are provided.
A memory circuit, wherein one selector output of one selector is the first data and the other selector output is the third data, and each of the two selectors can be independently selected and controlled. 4. In claim 3, the numbers of inputs of the two selectors are both 4 inputs, and the 4 inputs are respectively
The fixed logic “0”, the fixed logic “1”, the external data whose logic arbitrarily changes to “0” or “1”, and the inverted data of the external data are used as the respective inputs, and the assigned 4
A storage circuit characterized in that two input data are independently selected and controlled by the two selectors and combined. 5. The storage circuit according to claim 2, wherein the storage element and the control circuit are arranged in an arbitrary data length (bit number) or an arbitrary data capacity. 6. 6. The memory circuit according to claim 5, wherein the arbitrarily arranged memory element group and the control circuit group are incorporated in the same LSI. 7. The storage circuit according to claim 4, wherein the storage element, the control circuit, and the two selectors are arranged in an arbitrary data table (number of bits) or an arbitrary data capacity. . 8. 8. The memory circuit according to claim 7, wherein the arbitrarily arranged memory element group, the control circuit group and the two selector groups are incorporated in the same LSI. 9. The memory circuit according to claim 2 or 3, wherein the memory circuit has a function equivalent to a combination of the control circuit and the two selectors. Ten. 10. The storage circuit according to claim 9, wherein the means is arranged with an arbitrary data length (number of bits) or an arbitrary data capacity. 11. 11. The memory circuit according to claim 10, wherein the means group is incorporated in the same LSI.