JP2001005719A - Information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing system which can easily rewrite data of a storage element in a memory device fast irrelevantly to inputted data. SOLUTION: The information processor has the storage element 2, a one-chip memory device which has a terminal for inputting an indication signal indicating a mode of read or write operation, and a control unit which performs the read or write operation of the storage element according to an indication signal inputted from the terminal; and the control unit is equipped with a generating means which generates a write signal ('1' or '0') to the storage element and writes the write signal from the generating means to the storage element according to the indication signal inputted from the terminal prior to the read or write operation of the storage element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a RAM (Ramdom).
The present invention relates to an information processing system having an Access Memory. In particular, the present invention relates to an information processing system for executing a Read-Modify-Write operation of stored data.

[0002]

2. Description of the Related Art The prior art will be described by taking image processing as shown in FIGS. 1 and 2 as an example. In FIG. 1, M1 is C
An image area corresponding one-to-one with an RT (Catdode Ray Tube) screen, M2 is a storage area storing image data to be synthesized, and FC is an image area for synthesizing data of the image area M1 and data of the storage area M2. This is a Modify function. In FIG. 2, S1 is a processing step of reading data from the image area M1, S2 is a processing step of reading data from the storage area M2, and S3 is a processing step of reading data from the storage area M2.
A processing step for synthesizing the data of the read image area M1 and the storage area M2, and step S4 is a step of writing the synthesized data obtained in step S3 to the image area M1.

In the example of the image processing shown in FIG. 1, the processing steps in FIG.

[0004] On the other hand, the data amount of the target image area M1 is usually as large as 100K to several MByte. Therefore, the series of processing shown in FIG. 2 has the number of repetitions on the order of 106 even when data is processed in units of bytes.

For this reason, the following problems have conventionally occurred. That is, (1) as shown in FIG. 2, in this processing, most of the bus cycles (S1, S
2, S4). Therefore, the occupancy of the bus increases, and the bus load increases.

(2) The actual processing time is long due to a low-speed bus or overhead such as control of bus occupation.

(3) Furthermore, in the example of FIG. 2, the number of static steps is as small as four, but the amount of data to be handled is very large, so the number of dynamic steps becomes enormous and the processing time is long.

[0008] A storage circuit for performing this type of processing is disclosed in, for example, JP-A-59-60658.
Publication.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art by easily and quickly rewriting data to a storage element inside a memory device regardless of data from an external device. It is an object of the present invention to provide a one-chip memory device capable of performing such operations. Another object of the present invention is to provide an information processing system capable of easily and rapidly rewriting data in a storage element irrespective of input data.

[0010]

In order to achieve the above object, the present invention provides a memory element, a terminal for inputting an instruction signal for instructing a read or write operation mode, and an instruction signal input from the terminal. Execution means for executing a read or write operation to the storage element based on the one-chip memory device, wherein the execution means includes a generation means for generating a write signal to the storage element, Prior to a read or write operation on a storage element, a write signal (“1” or “0”) from the generation means is written to the storage element based on an instruction signal input from the terminal. This is a featured one-chip memory device.

Further, the present invention consists of a storage circuit having the following two functions in order to speed up the above-described image synthesizing process (data rewriting process).

A) A processing function of correcting data already stored in the storage element and writing the corrected data again to the storage element at the same address.

B) A function of writing general external data to a storage element.

In the present invention, the storage circuit having the two functions described above is realized by focusing on the following points.
This will be described with reference to FIG. FIG. 3 shows an external D-RAM (Dynam
ic-Ramdom Access Memory), and at this time, the D-RAM has a read / write cycle. In FIG. 3, ADR is an external address, WR is an external write request, and these two signals (ADR, WR) are given from, for example, a microprocessor. RAS is a row address loss strobe, CAS is a column address strobe, A is an address signal in which column and row addresses are generated in a time-division manner, W
E is a write enable, DO is read data, and Z is data from the outside (microprocessor). These signals except for Z are control signals generated from, for example, a DRAM controller or the like.

That is, (I) As shown in FIG. 3, generally, in a read / write cycle, one memory access corresponds to the read cycle (I)
And write cycle by write enable WE
(III) is executed.

(II) Therefore, the above read cycle (I)
Between read data DO and write cycle (III).
(II) in which the data and the external data Z simultaneously exist.

(III) This section (II) is set as a correction section. (IV) Further, this correction control can be performed by the external data Z.

Further, as an aspect of the present invention, there is also an information processing system having the following configuration.

A plurality of semiconductor memory elements for storing data, and an operation which is any one of the plurality of operations, and instructs an operation for writing write data supplied from outside to the memory element. A one-chip memory device having a first terminal for receiving an instruction signal, and a second terminal for receiving a write enable signal, the memory element, the first terminal and the second terminal being connected to the second terminal, A control unit for controlling a write operation for executing writing of the write data to the storage element in accordance with an operation represented by one of a plurality of operation instruction signals, the control unit being connected to the one-chip memory device; The operation instruction signal is supplied to the first terminal of the chip memory device. And an external device for supplying the write enable signal to the second terminal of the one-chip memory device, the external device being configured to operate when the write enable signal reaches a predetermined logic level. And supplying the operation instruction signal to the control unit via the first terminal of the one-chip memory device.

Further, the operation instruction signal is as follows:
It may be a control command bit supplied from the external device.

Further, the external device may be a microprocessor.

Further, the first terminal and the second terminal may be external terminals to which the operation instruction signal and the write enable signal are supplied.

Further, the predetermined logic level may be a low level.

[0024] Other aspects of the information processing system include the following.

A plurality of semiconductor storage elements for storing data and an operation instruction signal indicating an arbitrary one of a plurality of operations, the write data being written to the storage element and supplied from the outside. A first terminal for receiving an instruction signal for an operation for writing to the storage element, and a second terminal for receiving a write enable signal
And the storage element of the one-chip memory device, the first terminal and the second terminal,
A one-chip memory device, comprising: a control unit configured to control a write operation for executing writing of the write data from the first terminal to the storage element according to an operation represented by one of the operation instruction signals; Connected to a one-chip memory device, supplying the operation instruction signal and the write data to the first terminal of the one-chip memory device, and applying the write enable signal to the second terminal of the one-chip memory device An external device for supplying the operation instruction signal to the one-chip memory device via the first terminal when the write enable signal is set to a predetermined logic level. To the control unit.

Further, the operation instruction signal is as follows:
It may be a control command bit supplied from the external device.

[0027] The external device may be a microprocessor.

Further, the first terminal and the second terminal are external terminals, the first terminal is supplied with an operation instruction signal, and the second terminal is supplied with a write enable signal. May be done.

Further, the predetermined logic level is:
It may be a low level.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 3 is a time chart of the D-RAM as described above. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is an explanatory diagram of the operation principle of the embodiment shown in FIG. 4, and FIG. 6 is a diagram showing an example of a circuit which realizes the operation principle shown in FIG. FIG. 7 is a diagram for explaining the details of the operation of FIG.

In FIG. 4, 1 is a control circuit, 2 is a storage element, 3 is a D-RAM controller, X and Y are external data, Z is write data to the storage element, and DO is read data from the storage element. , A, CAS, RAS, WE, A
DR and WR are the same kind of signals as in FIG. In addition,
The external data Z shown in FIG. 3 is rewritten here (FIG. 4) into the write data Z to the storage element 2 via the control circuit 1.

As shown in FIG. 4, according to the present invention, in the control circuit 1, read data DO is controlled by external data X and Y,
Correct and write to storage element 2. This control operation is shown in FIG.

In FIG. 5, mode I is a mode in which external data Y is used as write data Z, and mode II is a mode in which read data DO is used as write data Z. As shown in FIG. 5, the read data DO of the storage element 2 is corrected and written by external data X and Y, that is, by external control (mode II), or write processing of external data Y (mode I). Mode can be controlled. This 2
In the control of the two modes, (I) modes I and II are designated by external data X, and (II) non-inversion and inversion of read data DO in mode II are designated (corrected) by external data.

FIG. 6 shows a specific example of a circuit for realizing the above operation. FIG. 7 shows a detailed truth value of the operation. As shown in FIGS. 6 and 7, the present invention can be realized by a combination of two logics.

The operation described above can be completed within one memory cycle as shown in FIG. On the other hand, the circuit shown in FIG. 6 is represented by the following logical expression (Equation 1).

[0036]

(Equation 1)

As possible values of the data X and Y that can be controlled from the outside, the signal "0", the signal "1", for example, the bus data Di from the microprocessor (external device), Allocate inverted data Di ',
By rearranging, a binomial logical operation result as shown in FIG. 8 is obtained. FIG. 9 shows an actual circuit obtained by combining this with FIG. In FIG. 9, SEL0 and SEL1 are four-powered selectors, S0 and S1 are input selection signals of the selector SEL0,
S2 and S3 are input selection signals of the selector SEL1, INV
Is an inversion element. As shown in FIG. 9, there is provided a means for generating "0" and "1" signals.
It is apparent that the signals of "1" and "1" are input to the selectors SEL0 and SEL1.

Hereinafter, an operation example will be specifically described with reference to FIGS. 1, 8, 9, and 10. FIG.

As shown in FIG. 8, external input selection signals S0,
S1 is a selection signal of the selector SEL0.
The value of the data X is determined by 0 and S1. Similarly, data Y is determined by input selection signals S2 and S3.
The possible values of these data X and Y include, as described above, internally generated signal "0", signal "1", bus data Di from the microprocessor, and inverted data D thereof.
i ′, and input selection signals S0, S1, S input from a microprocessor (external device) as shown in FIG.
2 and S3, each of the selectors SEL0 and SEL1 selects one of the four signals. FIG. 8 shows input selection signals S0, S1, S2, S3 and selector SEL.
The relationship between data X and Y, which are outputs of 0 and 1, is shown, and the operation of the control circuit 1 (write data Z
Value). For example, in the image processing (OR operation: Case 1) as shown in FIG. 1, the input selection signals S0,
By setting S1 = (11), S2, 3 = (10), X = inverted Di 'and Y = Di are selected for data X and Y, respectively. By substituting the values of these data X and Y into the equation (Equation 1) representing the operation of the control circuit 1, O = Z = Di + Do
It can be seen that the R operation can be performed. Therefore, according to the present invention, the image processing of FIG. 1 designates the input selection signals S0, 1, 2, 3 in the first step as shown in FIG.
ion), the operation mode is set in advance, and then the image data to be synthesized is read from the storage area M2,
The image processing shown in FIG. 1 can be executed only by a simple Write operation on the image area M1. Further, the present invention can execute various logic functions as shown in FIG.

Therefore, as shown in FIG. 11, for example, it is possible to easily draw an arbitrary moving mouse cursor.
As shown in FIG. 11, even when the mouse cursor (M2) overlaps the image in the image area M1, the cursor must be displayed.
R function is required. That is, in this cursor display, the input selection signals S0,1 = (01), S2,3 = (1
0), the processing can be performed as shown in FIG. 10 in the same manner as in the case of the above-described image composition (FIG. 1). Therefore, by changing the values of the input selection signals S0, 1, 2, and 3 input from the outside, various logic functions as shown in FIG. 6 can be easily executed, and the storage element 2 can be executed only by a simple Write operation. Read, modify, and write.

With the configuration as shown in FIG. 9, the binomial logical operation shown in FIG. 8 can be performed as a modification of the data Di from the microprocessor and the read data Do of the storage element 2. The binary logical operation is specified by the input selection signals S0 to S3.

Further, for example, the input selection signals S0, S1 =
By specifying (00), S2, 3 = (00) or (10), internally generated signal “0” or signal “1” is selected as data X, Y and stored as Z = 0 or 1. The device can be written.

As described above, by using the embodiment, the conventional image synthesizing process using FIGS.
The processing can be simplified as shown in FIG. The embodiment described above has three functions as shown in FIG. 9, namely, a storage unit composed of the storage element 2, a control unit composed of the control circuit 1, and a selector composed of the selectors SEL0 and SEL1. Divided into parts. However, the function realized by the combination of the control and the selector section is the binomial logical operation function shown in FIG. 8, and this function can be easily achieved by other means.

As described above, according to the present embodiment, the following effects can be obtained.

(1) When the processing as shown in FIG. 1 is performed, the memory cycle can be reduced as shown in FIG.
The above-described disadvantages in the related art can be eliminated.

(2) Since the microprocessor can execute three processes of read, modify, and write in one write cycle, the processing time can be further shortened.

(3) Compared to the memory element group, the ratio of the memory element group to the entire circuit according to the present invention is small, so that it is possible to easily implement an LSI.

(4) 64K × 4 bits currently on the market
In many D-RAMs, one Pin is No-Conn.
and up to the four points shown in FIG.
That is, even when the storage element 2 and the control circuit 1 are formed into an LSI, the number of Pins does not increase, which is extremely advantageous for the LSI.

[0049]

According to the present invention, the memory device has signal generating means for generating a write signal ("1" or "0") for the storage element, and the data of the storage element is written using the write signal. Since it is configured to be rewritten, there is an effect that data can be easily and rapidly rewritten to a storage element inside the memory device regardless of data from an external device.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a conventional technique by taking image processing as an example.

FIG. 2 is a flowchart of FIG.

FIG. 3 is a time chart in a process of writing data to a D-RAM.

FIG. 4 is a block diagram showing one embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation principle of FIG. 4;

FIG. 6 is a diagram showing an example of a circuit for realizing the operation principle of FIG. 5;

FIG. 7 is a diagram for explaining the operation of FIG. 6;

FIG. 8 is a diagram illustrating a relationship between an input selection signal and a selector output.

FIG. 9 is a circuit diagram for realizing FIG. 8;

FIG. 10 is a flowchart when the present invention is applied to image processing.

FIG. 11 is a diagram for explaining another application example of the present invention.

[Explanation of symbols]

 1 ... control circuit, 2 ... storage element, SEL ... selector.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroaki Aotsu 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inventor Mitsuru Ikegami Horiyamashita, Hadano-shi, Kanagawa No. 1 Inside Hitachi Ltd. Kanagawa Factory

Claims (10)

[Claims] 1. An information system for processing information, comprising: a plurality of semiconductor storage elements for storing data; and an operation which is an arbitrary one of the plurality of operations, the operation being supplied to the storage element from the outside. A one-chip memory device having a first terminal for receiving an instruction signal for instructing an operation for writing write data to be written, and a second terminal for receiving a write enable signal; the storage element; and the first terminal A control unit connected to the second terminal and controlling a write operation for executing writing of the write data to the storage element according to an operation represented by one of the instruction signals of the plurality of operations; The one-chip memory device is connected to the one-chip memory device, An external device that supplies the operation instruction signal to one terminal and supplies the write enable signal to the second terminal of the one-chip memory device; An information processing system, wherein when the logic level reaches a predetermined logic level, the operation instruction signal is supplied to the control unit via the first terminal of the one-chip memory device. 2. The information processing system according to claim 1, wherein the operation instruction signal is a control command bit supplied from the external device. 3. The information processing system according to claim 1, wherein said external device is a microprocessor. 4. The information system according to claim 1, wherein the first terminal and the second terminal are connected to the operation instruction signal and the write enable signal. An information processing system, which is an external terminal supplied. 5. The information processing system according to claim 1, wherein said predetermined logic level is a low level. 6. An information processing system for processing information, comprising: a plurality of semiconductor storage elements for storing data; and an operation instruction signal indicating an arbitrary one of a plurality of operations, wherein A first terminal for receiving an operation instruction signal for writing written and externally supplied write data to the storage element; a second terminal for receiving a write enable signal; A storage element, the first
And a write operation for writing the write data from the first terminal to the storage element in accordance with an operation represented by one of the operation instruction signals. A one-chip memory device having a control unit, the one-chip memory device being connected to the one-chip memory device, supplying the operation instruction signal and the write data to the first terminal of the one-chip memory device; An external device for supplying the second terminal of the one-chip memory device, wherein the external device outputs the operation instruction signal when the write enable signal is set to a predetermined logic level. The control of the one-chip memory device via a first terminal Information processing system and supplying the knit. 7. The information processing system according to claim 6, wherein the operation instruction signal is a control command bit supplied from the external device. 8. The information processing system according to claim 6, wherein said external device is a microprocessor. 9. The information processing system according to claim 6, wherein said first terminal and said second terminal are external terminals, and said first terminal is an external terminal. Is supplied with an operation instruction signal, and the second terminal is supplied with a write enable signal. 10. The information processing system according to claim 6, wherein said predetermined logic level is a low level.