JPH06215559A - Page memory access system - Google Patents

Abstract

PURPOSE:To provide a high speed page memory access even for the cases to read and to write picture data with characters which have a small amount of same row address data and have many data in a row address direction. CONSTITUTION:A RAS generation section 2 gives row address/strobe signals to a DRAM 1 which is used as a page memory and a CAS generation section 3 sends column address/strobe signals to the DRAM 1. An address transforming section 5 equally divides logical column addresses of the DRAM 1 into 2<n> parts and address transforms continuous 2<n> lines, which exist in the divided same logical column address region, so that these lines are assigned to same physical row addresses of the DRAM 1. At a selector 4, the addresses transformed by the section 5 are resolved into row and column addresses and are given to the DRAM 1. By performing the address transformation described above, (2<n>-1) times of a RAS precharge time and a load time are reduced for every 2n lines of the logical addresses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a page memory access method suitable for high speed access control of a DRAM (dynamic random access memory) having a high speed access mode such as a static column mode or a high speed page mode. is there.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an outline of a conventional DRAM access method. In FIG. 7, 1 is DR
AM, 2 is a RAS generator, 3 is a CAS generator, and 4 is a selector. A 16-bit DRAM continuous logical address is shown in FIG. 8, but in the access method of FIG. 7, it is decomposed into a vertical row address and a horizontal column address for access. Note that FIG.
In, the address is represented in hexadecimal notation.

FIG. 9 is a diagram showing a 16-bit DRAM physical row and column address. In FIG. 9, m of the physical address P (m, n) is a row address, and n
Is the column address. This address signal is sent to the DRAM
To give 1 to 1, for example, an address given by 18 bits is divided into upper 9 bits and lower 9 bits by the selector 4, the upper 9 bits are given as a row address first, and then the lower 9 bits are given as a column address. .

When the row address is given,
The RAS (row address strobe signal) is output from the RAS generator 2, the row address is latched at the falling edge thereof, and then the CA is applied when the column address is applied.
CAS (column address strobe signal) is output from the S generation unit 3, and the column address is latched at the falling edge thereof.

FIG. 10 is a timing chart when the m-th line is continuously accessed. In FIG.
RAS ,! The "!" In CAS indicates negative logic. A is an address signal given to the DRAM 1. When the row address m is given from the selector 4 ,! When RAS falls, the row address m is latched at that point. Subsequently, the selector 4 outputs the column addresses 0, 1, ... In sequence, but when the first column address 0 is output, the! When CAS falls, column address 0 is latched and then! CA
While S is at the low level, the switched address value is latched every time the column address is switched.

As a technique for improving the processing speed in such a DRAM access method, for example, there is a technique disclosed in Japanese Patent Laid-Open No. 1-100794. After accessing the DRAM, the D
RAS of DRAM when there is no access request to RAM
Is kept in the active state and the loss time is reduced when the same row address is accessed next time. According to this conventional technique, even if the DRAM is being accessed and the memory or I / O other than the DRAM is interrupted during the access to the DRAM, the high-speed access mode of the DRAM is not interrupted. Therefore, the system stores data in continuous addresses. It is effective when used as a memory.

[0007]

[Problems to be Solved by the Invention]

(Problem) However, in the above-described conventional technology, when writing or reading data such as characters having a small amount of data at the same row address and a large amount of data in the row address direction, the row address is often changed. There is a problem that the RAS precharge time and the row address load time are required for each line.

(Explanation of Problems) FIG. 11 is a diagram showing a state in which a character image is written in the page memory. Row addresses R _{2 to} R ₇ , column addresses C ₁ and C ₂ ,
It is assumed that the character image “F” is written.

FIG. 12 is a timing chart when writing the character image of FIG. First, after writing the row address R ₂ in order to write the second line ,!
RAS is lowered and the row address R ₂ is latched. Then, after outputting the column address C ₁ ,! The CAS is lowered and the column address C ₁ is latched, one word of data is written to the address (R ₂ , C ₁ ), the column address C ₂ is output, and the address (R ₂ , C 1
₂ ) Write one word of data to. Next, to write the third line of data ,! The same processing as when writing the second line is repeated after the RAS is once returned to the high level.

Thus, every time the line changes! RAS
Need to be once returned to the high level, and the RAS precharge time and the load time as shown in FIG. 12 are necessary, and the data read takes time accordingly.
Moreover, in a normal page memory, when writing a character having a small amount of data at the same row address and a large amount of data in the row address direction as in the case shown in FIG. Become. Therefore, the number of RAS precharges and the number of row address loads increase, and the processing time is delayed. By the way, in the case of FIGS. 11 and 12, the RAS precharge count is 6 times,
The row address must be loaded 6 times. An object of the present invention is to solve such a problem.

[0011]

In order to solve the above-mentioned problems, in the page memory access method of the present invention, a RAS generating section for generating a row address / strobe signal and a CAS generating section for generating a column address / strobe signal are provided. , An address conversion unit that divides the logical column address of the page memory into 2 ⁿ equal parts and performs address conversion so that consecutive 2 ⁿ lines in the divided same logical column address area are assigned to the same physical row address of the page memory. And a selector that gives the row address and the column address whose addresses have been converted to the page memory.

[0012]

[Operation] The address conversion unit divides the logical column address of the page memory into 2 ⁿ equal parts, and assigns consecutive 2 ⁿ lines in the divided same logical column address area to the same physical row address of the page memory. The address is converted as described above, and the converted address signal is applied to the DRAM through the selector. Therefore, the logical address 2 ⁿ
The RAS precharge time and the load time can be reduced (2 ⁿ -1) times for each line, and even when writing or reading data such as characters having a small amount of data at the same row address and a large amount of data in the row address direction. It enables high-speed page memory access.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an outline of the present invention. Reference numerals correspond to those in FIG. 7, and 5 is an address conversion unit. In the present invention, the address conversion unit 5 is provided before the selector 4 of the conventional access control circuit shown in FIG. The address conversion unit 5 divides the logical column address of the page memory into 2 ⁿ equal parts and assigns consecutive 2 ⁿ lines in the divided same logical column address area to the same physical row address of the page memory. Convert address.

Here, the function of the address conversion unit 5 will be described by taking the case where n = 1, that is, the case where the logical column address of the page memory is equally divided into two. FIG. 3 is a diagram showing the page memory space before and after the address conversion. FIG. 3A shows the page memory space before address conversion, and FIG. 3B shows the page memory space after address conversion. In this way, the second before conversion
The first half 2a of the column address of the line is moved to the second half of the column address of the first line after the conversion, and the first half 3a of the column address of the third line before the conversion is moved to the first half of the column address of the second line after the conversion. Also, the first before conversion
After conversion, the column address latter half 1b of the line is moved to the column address former half of the first line of the row address latter half after conversion, and the column address latter half 2b of the second line before conversion is
After conversion, it is moved to the second half of the column address of the first line of the second half of the row address. The address conversion unit 5 performs such address conversion.

The address conversion unit 5 is, for example, the selector 4
It can be realized by changing the connection of the address input terminal of. FIG. 2 is a diagram showing a case where the connection of the selector terminal is changed to perform the address conversion. This selector 4 has address input terminals of 1A, 1B, 2A, ...
.., 18 for 9B and 9 for address output terminals 1Y to 9Y
It has an individual terminal and a select B terminal. Then, by switching the select column signal SELCOL applied to the select B terminal, 1A, 2A, ..., 9A and 1B, 2B, ..., 9B are selected and output to the address output terminals 1Y to 9Y. The terminals 1A, 2A, ...
.., 9A assigned to row addresses, terminals 1B, 2B ,.
.., 9B are assigned to column addresses to switch between row addresses and column addresses.

When the address translation is not performed, FIG.
The most significant bit PMA of the address signal to the terminal 1A as shown in
17 is applied to the second bit P of the address signal at the terminal 2A.
MA16 is applied, and the ninth bit PMA9 of the address signal is applied to the terminal 9A in the same manner. Further, the tenth bit PMA8 of the address signal is given to the terminal 1B, and the terminal 2
The 11th bit PMA7 of the address signal is given to B, and the least significant bit P of the address signal is similarly applied to the terminal 9B.
Give MA0. Then, the select column signal SE
Each time LCOL is switched, address output terminals 1Y-9
Address signal PMA17 to PMA9 of upper 9 bits for Y
And the lower 9-bit address signals PMA8 to PMA0 are alternately output.

On the other hand, in the case of performing the address conversion as in the present invention, the tenth bit PMA8 of the address signal is applied to the terminal 1A instead of the most significant bit PMA17 as shown in FIG. 9A are sequentially shifted one by one, and the most significant bits PMA17 to PMA of the address signal.
10 is given, and the 9th bit PMA9 is given to the terminal 1B instead of the 10th bit PMA8 of the address signal, and the terminals 2B to 9B are the same as in the case of FIG.
In this way, the address conversion as shown in FIG. 3 can be performed only by changing the terminal connection of the selector. The relationship between the logical address and the physical address after the address conversion is as follows.

FIG. 4 is a diagram showing a detailed relationship between a logical address and a physical address when n = 1. Figure 4 (a)
Indicates the logical address of the page memory, and FIG.
Shows the correspondence between the logical address and the physical address in the page memory after the address conversion. That is, P (x, y) in FIG. 4B indicates that the logical address (x, y) corresponds to the position on the physical address where it is shown.

Next, a case where the character "F" is written in the page memory whose address has been converted will be described. FIG. 5 shows n
It is a figure which shows an example of the character data on a logical space and a physical space in the case of = 1. When the character “F” as shown in FIG. 5A is written in the logical space, the actual DRAM is
It is written as shown in FIG. In this way, the character data originally having 6 lines is written in 3 lines.

FIG. 6 is a timing chart when writing the character data of FIG. Since the character data is written in 3 lines, the row address is R _1,
Three addresses _, R _{2 and} R ₃ , are output, and each time the row address is changed, C _1, C ₂ and C _{m + 1, are used} as column addresses _.
It outputs four addresses Cm _{+ 2} . After all, according to the present invention, to write a 2-word 6-line character, the RAS
3 precharges and 3 row address loads
The number of times the column address is loaded is 12 times.

On the other hand, in the conventional method, as shown in FIG.
As described with reference to FIG. 12, when writing the same 2-word 6-line character, the RAS precharge count is 6
The number of times of row address loading was 6, and the number of times of column address loading was 12 times. Therefore, according to the present invention, the time for writing the character of 2 words and 6 lines by 3 times of RAS precharge and 3 times of row address loading is shortened.

In the above embodiment, the address conversion of the address conversion unit is performed by changing the connection of the address input terminal of the selector, but it is also possible to use an address conversion circuit separately. Further, in the above embodiment, the DRA
The case of writing data to M has been described, but the same can be applied to the case of reading data from DRAM.

[0023]

As described above, according to the page memory access method of the present invention, the RAS precharge time and the load time of (2 ⁿ -1) times for every 2 ⁿ lines of the logical address can be reduced, and the same row can be reduced. High-speed page memory access is possible even when writing or reading data such as characters having a small amount of address data and a large amount of data in the row address direction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of the present invention.

FIG. 2 is a diagram showing a case where address conversion is performed by changing the connection of selector terminals.

FIG. 3 is a diagram showing a page memory space before and after performing address conversion.

FIG. 4 is a diagram showing a detailed relationship between a logical address and a physical address when n = 1.

FIG. 5 is a diagram showing an example of character data in a logical space and a physical space when n = 1.

FIG. 6 is a timing chart when writing the character data of FIG.

FIG. 7 is a block diagram showing an outline of a conventional DRAM access method.

FIG. 8 is a diagram showing a 16-bit DRAM continuous logical address.

FIG. 9 is a diagram showing 16-bit DRAM physical row and column addresses.

FIG. 10 is a timing chart when continuously accessing the m-th line.

FIG. 11 is a diagram showing a state in which a character image is written in a page memory.

FIG. 12 is a timing chart when writing the character image of FIG. 11.

[Explanation of symbols]

1 ... DRAM, 2 ... RAS generator, 3 ... CAS generator,
4 ... selector, 5 ... address conversion unit

Claims (1)

[Claims] 1. A RAS generating section for generating a row address / strobe signal, a CAS generating section for generating a column address / strobe signal, and a logical column address of a page memory are divided into 2 ⁿ equal parts, and the divided parts are the same. An address conversion unit that performs address conversion so as to assign consecutive 2 ⁿ lines in the logical column address area to the same physical row address of the page memory, and a selector that gives the address-converted row address and column address to the page memory. Page memory access method characterized by having